TW202239004A - 半導體元件及其製作方法 - Google Patents

半導體元件及其製作方法 Download PDF

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TW202239004A
TW202239004A TW110110033A TW110110033A TW202239004A TW 202239004 A TW202239004 A TW 202239004A TW 110110033 A TW110110033 A TW 110110033A TW 110110033 A TW110110033 A TW 110110033A TW 202239004 A TW202239004 A TW 202239004A
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polymer block
gate
layer
fin structure
semiconductor device
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張家瑋
郭家銘
莊博仁
莊馥戎
王韶韋
王俞仁
張家源
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聯華電子股份有限公司
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Priority to TW110110033A priority Critical patent/TW202239004A/zh
Priority to US17/225,066 priority patent/US11545557B2/en
Publication of TW202239004A publication Critical patent/TW202239004A/zh
Priority to US17/994,375 priority patent/US11876122B2/en

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Abstract

一種半導體元件，包含一基底，具有一鰭狀結構；一閘極結構，覆蓋該鰭狀結構；一聚合物塊，位於該閘極結構和該鰭狀結構之間的一拐角處，其中該聚合物塊包含鄰近該閘極結構的一側壁的一氮化層；以及一源極/汲極區，位於該鰭狀結構上。

Description

半導體元件及其製作方法
本發明係有關於半導體技術領域，特別是有關於一種半導體鰭狀場效電晶體（fin-type field effect transistor，FinFET）元件及其製作方法。
由於積體電路的尺寸減小，對於具有高驅動電流及小尺寸的電晶體的需求增加，因而發展出鰭狀場效電晶體（FinFET）。FinFET元件的通道形成於鰭片的側壁和頂表面上，使得FinFET元件具有較大的通道寬度，進而可以增加電晶體的驅動電流。
FinFET元件係先利用蝕刻等方式圖案化一基底表面的矽層，形成一鰭狀的矽結構，再於鰭狀的矽結構上形成絕緣層與虛設多晶矽閘極，然後以離子佈植製程與回火製程等步驟於鰭狀的矽結構中形成源極/汲極區，並以磊晶製程在源極/汲極區中形成如SiP等磊晶層，後續，再進行置換金屬閘極（replacement metal gate，RMG）製程，將虛設多晶矽閘極以金屬閘極取代。
然而，現有作法在進行虛設多晶矽閘極的去除步驟時，可能會造成源極/汲極區中的SiP磊晶層被蝕除，在源極/汲極區中形成孔洞缺陷，導致製程良率下降。
本發明的主要目的在提供一種半導體元件及其製作方法，以解決上述現有技術的不足和缺點。
本發明一方面提供一種半導體元件，包含一基底，具有一鰭狀結構；一閘極結構，覆蓋該鰭狀結構；一聚合物塊，位於該閘極結構和該鰭狀結構之間的一拐角處，其中該聚合物塊包含鄰近該閘極結構的一側壁的一氮化層；以及一源極/汲極區，位於該鰭狀結構上。
根據本發明實施例，該氮化層包含一氮化的氧化矽膜。
根據本發明實施例，該聚合物塊包含一氧化矽層，在該氮化的氧化矽膜上。
根據本發明實施例，該閘極結構是一金屬閘極。
根據本發明實施例，該源極/汲極區包含一SiP磊晶層。
根據本發明實施例，該鰭狀結構設置在一溝槽隔離區域上方。
根據本發明實施例，該半導體元件另包含一密封層，設於該閘極結構的側壁上和該聚合物塊上。
根據本發明實施例，該密封層包含一碳摻雜氮氧化矽層。
本發明另一方面提供一種形成半導體元件的方法，包含：提供一基底，該基底上具有一鰭狀結構；在該鰭狀結構上形成一虛設閘極，其中，在該虛設閘極與該鰭狀結構之間的拐角處形成有一聚合物塊；對該聚合物塊進行一氮電漿處理，從而在鄰近該虛設閘極的側壁的該聚合物塊下方形成一氮化層；在對該聚合物塊進行該氮電漿處理之後，在該虛設閘極的側壁和該聚合物塊上形成一密封層；在該鰭狀結構的一源極/汲極區上生長一磊晶層；以及用一金屬閘極置換該虛設閘極。
根據本發明實施例，該氮化層包含一氮化的氧化矽膜。
根據本發明實施例，該聚合物塊包含一氧化矽層，在該氮化的氧化矽膜上。
根據本發明實施例，該磊晶層包含SiP。
根據本發明實施例，該虛設閘極是一虛設多晶矽閘極。
根據本發明實施例，該密封層包含一碳摻雜氮氧化矽層。
在下文中，將參照附圖說明細節，該些附圖中之內容亦構成說明書細節描述的一部份，並且以可實行該實施例之特例描述方式來繪示。下文實施例已描述足夠的細節俾使該領域之一般技藝人士得以具以實施。
當然，亦可採行其他的實施例，或是在不悖離文中所述實施例的前提下作出任何結構性、邏輯性、及電性上的改變。因此，下文之細節描述不應被視為是限制，反之，其中所包含的實施例將由隨附的申請專利範圍來加以界定。
本發明係有關於半導體鰭狀場效電晶體（FinFET）元件及其製作方法。如前所述，FinFET元件係先利用蝕刻等方式圖案化一基底表面的矽層，以於基底中形成一鰭狀的矽結構，再於鰭狀的矽結構上形成絕緣層與虛設多晶矽閘極，再以離子佈植製程與回火製程等步驟於鰭狀的矽結構中形成源極/汲極區，並以磊晶製程在源極/汲極區中形成SiP等磊晶層，後續，再以置換金屬閘極（replacement metal gate，RMG）製程，將虛設多晶矽閘極以金屬閘極取代。
然而，在進行虛設多晶矽閘極的去除步驟時，有時會造成源極/汲極區中的SiP磊晶層被蝕除，並在源極/汲極區中形成孔洞缺陷，導致製程良率下降。本發明能夠具體解決上述現有技術的問題。
請參閱第1圖至第6圖，其為依據本發明實施例所繪示的半導體元件1的製作方法示意，其中，第1圖為依據本發明實施例所繪示的半導體元件1的上視圖，第2至6圖為依據本發明實施例所繪示的半導體元件1的側視立體圖。
如第1圖和第2圖所示，提供一基底100，例如，半導體基底。在基底100上形成有一鰭狀結構F，例如，鰭狀的矽結構，然後，在鰭狀結構F上形成一閘極介電層110，再於閘極介電層110上形成一虛設閘極120，例如，虛設多晶矽閘極。根據本發明實施例，鰭狀結構F設置在一溝槽隔離區域SI上方。
此時，在虛設閘極120的側壁120s和該鰭狀結構之間的拐角處會形成一聚合物塊（polymer block）P，又稱為鰭轉角氧化物（fin corner oxide，FCO）。上述聚合物塊P主要是由形成虛設多晶矽閘極120時的殘留矽氧化而成的矽氧物所構成的。後續，在進行虛設閘極120的去除步驟時，蝕刻劑（etchant）可能會蝕刻聚合物塊P，並導致源極/汲極區中的SiP磊晶層被蝕除，因而在源極/汲極區中形成孔洞缺陷。
如第3圖所示，對聚合物塊P進行一氮電漿處理NPT，氮離子穿過聚合物塊P，在鄰近虛設閘極120的側壁120s的聚合物塊P下方形成一氮化層PN。根據本發明一實施例，氮化層PN包含氮化的氧化矽膜。根據本發明一實施例，聚合物塊P可以包含一氧化矽層PO，在氮化的氧化矽膜上。
如第4圖所示，在對聚合物塊P進行氮電漿處理NPT之後，接著在虛設閘極120的側壁120s和聚合物塊P上形成一密封層130。根據本發明一實施例，密封層130可以包含一碳摻雜氮氧化矽（SiOCN）層，但不限於此。
如第5圖所示，接著在鰭狀結構F的一源極/汲極區150上生長一磊晶層EP。根據本發明實施例，磊晶層EP可以包含SiP。
如第6圖所示，最後進行一RMG製程，用一金屬閘極220置換虛設閘極120。由於上述RMG製程為周知技術，因此其細節不另贅述。例如，上述RMG製程可以包含一虛設多晶矽閘極去除（dummy poly removal，DPR）步驟，用蝕刻方式去除虛設閘極120。在進行DPR步驟時，氮化層PN可以抵擋蝕刻，故不會發生源極/汲極區中的SiP磊晶層被蝕除，也因此在源極/汲極區150中不會形成孔洞缺陷。
結構上，從第3圖和第6圖可看出本發明一種半導體元件1包含：一基底100，具有一鰭狀結構F；一閘極結構220，覆蓋鰭狀結構F；一聚合物塊P，位於閘極結構220和鰭狀結構F之間的一拐角處，其中聚合物塊P包含鄰近閘極結構220的一側壁的一氮化層PN；以及一源極/汲極區150，位於鰭狀結構F上。
根據本發明實施例，如第3圖所示，氮化層PN包含一氮化的氧化矽膜。根據本發明實施例，聚合物塊P包含一氧化矽層PO，在該氮化的氧化矽膜上。
根據本發明實施例，閘極結構220是一金屬閘極。根據本發明實施例，源極/汲極區150包含一SiP磊晶層EP。根據本發明實施例，鰭狀結構F設置在一溝槽隔離區域SI上方。
根據本發明實施例，半導體元件1另包含一密封層130，設於閘極結構220的側壁上和聚合物塊P上。根據本發明實施例，密封層130包含一碳摻雜氮氧化矽層。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
1:半導體元件 100:基底 110:閘極介電層 120:虛設閘極 120s:側壁 130:密封層 150:源極/汲極區 220:金屬閘極 EP:磊晶層 F:鰭狀結構 NPT:氮電漿處理 P:聚合物塊 PN:氮化層 PO:氧化矽層 SI:溝槽隔離區域
第1圖至第6圖為依據本發明實施例所繪示的半導體元件的製作方法示意，其中，第1圖為依據本發明實施例所繪示的半導體元件的上視圖，第2至6圖為依據本發明實施例所繪示的半導體元件的側視立體圖。
100:基底
110:閘極介電層
120:虛設閘極
120s:側壁
F:鰭狀結構
NPT:氮電漿處理
P:聚合物塊
PN:氮化層
PO:氧化矽層
SI:溝槽隔離區域

Claims (14)

  1. 一種半導體元件，包含： 一基底，具有一鰭狀結構； 一閘極結構，覆蓋該鰭狀結構； 一聚合物塊，位於該閘極結構和該鰭狀結構之間的一拐角處，其中該聚合物塊包含鄰近該閘極結構的一側壁的一氮化層；以及 一源極/汲極區，位於該鰭狀結構上。
  2. 根據請求項1所述的半導體元件，其中，該氮化層包含一氮化的氧化矽膜。
  3. 根據請求項2所述的半導體裝置，其中，該聚合物塊包含一氧化矽層，在該氮化的氧化矽膜上。
  4. 根據請求項1所述的半導體元件，其中，該閘極結構是一金屬閘極。
  5. 根據請求項1所述的半導體元件，其中，該源極/汲極區包含一SiP磊晶層。
  6. 根據請求項1所述的半導體元件，其中，該鰭狀結構設置在一溝槽隔離區域上方。
  7. 根據請求項1所述的半導體元件，其中，另包含： 一密封層，設於該閘極結構的側壁上和該聚合物塊上。
  8. 根據請求項1所述的半導體元件，其中，該密封層包含一碳摻雜氮氧化矽層。
  9. 一種形成半導體元件的方法，包含： 提供一基底，該基底上具有一鰭狀結構； 在該鰭狀結構上形成一虛設閘極，其中，在該虛設閘極與該鰭狀結構之間的拐角處形成有一聚合物塊； 對該聚合物塊進行一氮電漿處理，從而在鄰近該虛設閘極的側壁的該聚合物塊下方形成一氮化層； 在對該聚合物塊進行該氮電漿處理之後，在該虛設閘極的側壁和該聚合物塊上形成一密封層； 在該鰭狀結構的一源極/汲極區上生長一磊晶層；以及 用一金屬閘極置換該虛設閘極。
  10. 根據請求項9所述的方法，其中，該氮化層包含一氮化的氧化矽膜。
  11. 根據請求項10所述的方法，其中，該聚合物塊包含一氧化矽層，在該氮化的氧化矽膜上。
  12. 根據請求項9所述的方法，其中，該磊晶層包含SiP。
  13. 根據請求項9所述的方法，其中，該虛設閘極是一虛設多晶矽閘極。
  14. 根據請求項9所述的方法，其中，該密封層包含一碳摻雜氮氧化矽層。
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