TW202010047A - 用於堆疊積體電路的混合接合技術 - Google Patents

用於堆疊積體電路的混合接合技術 Download PDF

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TW202010047A
TW202010047A TW108113664A TW108113664A TW202010047A TW 202010047 A TW202010047 A TW 202010047A TW 108113664 A TW108113664 A TW 108113664A TW 108113664 A TW108113664 A TW 108113664A TW 202010047 A TW202010047 A TW 202010047A
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die
bonding
substrate
tsv
interconnect structure
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TW108113664A
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TWI733099B (zh
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吳國銘
王俊智
楊敦年
林杏芝
劉人誠
高敏峰
林永隆
黃詩涵
陳奕男
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台灣積體電路製造股份有限公司
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Abstract

本發明一些實施例提供一種三維(3D)積體電路(IC)。在一些實施例中，一第二IC晶粒藉由一第一接合結構接合至一第一IC晶粒。該第一接合結構接觸該第一IC晶粒之一第一互連結構及該第二IC晶粒之一第二互連結構，且具有混合接合在一起之一第一部分及一第二部分。一第三IC晶粒藉由一第三接合結構接合至該第二IC晶粒。該第三接合結構包括貫穿該第二IC晶粒之該第二基板放置之一第二TSV (貫穿基板通路)且包含根據本發明之各種實施例之各種接合結構。

Description

用於堆疊積體電路的混合接合技術
本發明實施例係有關用於堆疊積體電路的混合接合技術。
半導體行業已藉由縮減最小構件尺寸而不斷改良積體電路(IC)之處理能力及功率消耗。然而，近年來，製程限制已使得難以繼續縮減最小構件尺寸。將二維(2D) IC堆疊成三維(3D) IC已成為繼續改良IC之處理能力及功率消耗之一潛在方法。
本發明的一實施例係關於一種三維(3D)積體電路(IC)，其包括：一第一IC晶粒，其包括一第一基板及該第一基板上方之一第一互連結構；一第二IC晶粒，其包括一第二基板及該第二基板上方之一第二互連結構，其中該第二IC晶粒藉由一第一接合結構接合至該第一IC晶粒，該第一接合結構包括接觸該第一互連結構之一第一部分及接觸該第二互連結構之一第二部分，其中該第一部分及該第二部分混合接合在一起；及一第三IC晶粒，其包括一第三基板及該第三基板上方之一第三互連結構，其中該第三IC晶粒藉由一第三接合結構接合至該第二IC晶粒，其中該第三接合結構配置於相對於對應互連結構之該第二IC晶粒之背側與該第三IC晶粒之背側之間，且包括貫穿該第二基板放置之一第二TSV (貫穿基板通路)及貫穿該第三基板放置之一第三TSV。
本發明的一實施例係關於一種三維(3D)積體電路(IC)，其包括：一第一IC晶粒；一第二IC晶粒，其包括一第二基板及該第二基板上方之一第二互連結構，該第二IC晶粒具有一前側及與該前側相對之一背側，其中該第一IC晶粒藉由一第一接合結構接合至該第二IC晶粒之該前側；及一第三IC晶粒，其包括一第三基板及該第三基板上方之一第三互連結構，其中該第三IC晶粒藉由一第三接合結構接合至該第二IC晶粒之該背側，其中該第三接合結構包括貫穿該第二基板放置且直接接合至該第三IC晶粒之一導電構件之一第二TSV (貫穿基板通路)，該導電構件具有沿與該第二TSV之一側壁相反之一方向傾斜之一側壁。
本發明的一實施例係關於一種用於製造一個三維(3D)積體電路(IC)之方法，該方法包括：提供且接合一第一IC晶粒及一第二IC晶粒，該第一IC晶粒包括一第一基板及該第一基板上方之一第一互連結構且該第二IC晶粒包括一第二基板及該第二基板上方之一第二互連結構，其中該第二IC晶粒藉由一第一接合結構接合至該第一IC晶粒，該第一接合結構包括接觸該第一互連結構之一第一部分及接觸該第二互連結構之一第二部分；薄化該第二基板且貫穿該第二基板形成一第二TSV；提供且接合一第三IC晶粒及一第四IC晶粒，該第三IC晶粒包括一第三基板及該第三基板上方之一第三互連結構且該第四IC晶粒包括一第四基板及該第四基板上方之一第四互連結構，其中該第四IC晶粒藉由一第二接合結構接合至該第三IC晶粒，該第二接合結構包括接觸該第三互連結構之一第一部分及接觸該第四互連結構之一第二部分；薄化該第三基板且貫穿該第三基板形成一第三TSV；及透過該第二TSV及該第三TSV接合該第二基板及該第三基板。
本揭露提供用於實施本揭露之不同特徵之許多不同實施例或實例。下文描述組件及配置之特定實例以簡化本揭露。當然，此等僅僅係實例且並非意欲於限制性。例如，在下文描述中一第一構件形成於一第二構件上方或上可包含其中第一構件及第二構件經形成為直接接觸之實施例，且亦可包含其中額外構件可形成於第一構件與第二構件之間，使得第一構件及第二構件可不直接接觸之實施例。另外，本揭露可在各項實例中重複元件符號及/或字母。此重複出於簡化及清楚之目的且本身不指示所論述之各項實施例及/或組態之間的一關係。
此外，為便於描述，空間相對術語(諸如「在…下面」、「在…下方」、「下」、「在…上方」、「上」及類似者)可在本文中用來描述一個元件或構件與另一(其他)元件或構件之關係，如圖中所繪示。空間相對術語意欲於涵蓋除圖中所描繪之定向以外裝置或設備在使用或操作中之不同定向。裝置或設備可以其他方式定向(旋轉90度或按其他定向)且據此可同樣解釋本文中所使用之空間相對描述詞。甚至，術語「第一」、「第二」、「第三」、「第四」及類似者僅僅係通用識別符且因而可在各種實施例中互換。例如，雖然在一些實施例中一元件(例如，一導電線)可被稱為「第一」元件，但在其他實施例中該元件可被稱為「第二」元件。
三維(3D)積體電路(IC)包括彼此上下堆疊且接合之複數個二維(2D) IC晶粒。用來製造3D IC之方法之一者包含首先面對面接合一第一IC晶粒及一第二IC晶粒。第一IC晶粒及第二IC晶粒包括各自半導體基板、半導體基板之間的各自互連結構。互連結構包括交替金屬線堆疊(例如，水平佈線)及金屬通路(例如，垂直佈線)。面對面接合意謂著使第一IC晶粒及第二IC晶粒之各自接合結構放置於互連結構之間。接著，可自第二IC晶粒之一背側執行一薄化製程以薄化第二基板，且將一第三IC晶粒接合至第二IC晶粒。可將第三IC晶粒自一前側接合至第二IC晶粒之背側，即，形成一正面-背面接合，且自第三IC晶粒之一背側暴露一半導體基板。亦可將第三IC晶粒自一背側接合至第二IC晶粒之背側，即，形成一背對背接合，且自第三IC晶粒之一前側暴露一互連結構。接著，可繼續將一第四IC晶粒接合至第三IC晶粒之經暴露側。隨著技術發展且電路變得越來越複雜，可將更多2D IC晶粒堆疊在一起。當3D IC包含三個或五個以上堆疊式2D IC晶粒時，製造週期變得非常長。需要改良效率且縮短製造週期。
鑑於前述內容，本申請案之各項實施例係關於一種用來製造3D IC且改良製造週期之「並行」方法。亦揭露可以一更及時方式形成之一改良式混合接合結構之各項實施例。例如參考圖1至圖3，將多個晶粒(諸如四個IC晶粒10、20、30及40)垂直地堆疊於一起以形成3D IC。在一些實施例中，多個晶粒可分成兩個或更多個子群組以便接合且接著接合在一起。例如，一第一IC晶粒10及一第二IC晶粒20可接合在一起，且一第三IC晶粒30及一第四IC晶粒40可同時接合在一起或至少具有重疊之處理時間。接著，可將經接合子群組接合在一起。與其中多個晶粒接連地接合在一起之一循序製造製程相比，此「並行」製造製程縮短整個製造週期。下文揭露一些實例接合製程及接合結構。
如圖1中所展示，可藉由一第一接合結構132將一第一IC晶粒10及一第二IC晶粒20面對面接合在一起。第一IC晶粒10包括一第一基板100及第一基板100上方之一第一互連結構104。基板100及下文所描述之其他基板可包含一半導體晶圓、一半導體晶圓之一部分、一半導體晶粒或其他適用基板。第一互連結構104包括交替地堆疊於一第一ILD層110 (層間介電質層)中之第一複數個金屬線106及第一複數個金屬通路108。第二IC晶粒20包括一第二基板200及該第二基板上方之一第二互連結構204。第二互連結構204包括交替地堆疊於一第二ILD層210中之第二複數個金屬線206及第二複數個金屬通路208。接合製程可為包含導體至導體接合及介電質至介電質接合製程之一混合接合製程。第一接合結構132包括接觸第一互連結構104之一第一部分132a及接觸第二互連結構204之一第二部分132b。第一接合結構132可包括各自接合介電質層136、236、各自重佈層114、214、各自虛設重佈層116、216及各自接合接點112、212。重佈層114、214及各自虛設重佈層116、216凹入至接合介電質層136、236中且彼此直接接觸以界定一導體至導體介面。重佈層114、214、虛設重佈層116、216以及下文所描述之其他重佈層及虛設重佈層係出於接合目的而製作。重佈層及虛設重佈層自一俯視圖看可具有矩形、圓形或其他適用形狀。重佈層及虛設重佈層可由Cu、Al、W、Au、Ti、Pt、Co、另一合適材料或其等之組合製成。接合介電質層136、236及下文所描述之其他接合介電質層可由氧化矽、氮氧化矽、氮化矽、硼矽酸鹽玻璃(BSG)、磷矽酸鹽玻璃(PSG)、硼磷矽酸鹽玻璃(BPSG)、氟化矽酸鹽玻璃(FSG)、低介電係數材料、另一合適材料或其等之組合製成。可使用一化學氣相沉積(CVD)製程、一原子層沉積(ALD)製程、一旋塗製程、另一適用製程或其等之組合沉積接合介電質層136、236及下文所描述之其他接合介電質層。接合介電質層136、236可彼此直接接觸以界定可與一導體至導體介面對準之一介電質至介電質介面。接合接點112、212分別自重佈層114、214延伸至互連結構104、204。接著，自一背側薄化第二基板200以準備一後續接合製程。薄化製程可包括一化學機械拋光(CMP)製程及/或其他薄化技術。貫穿第二基板200形成一第二TSV (貫穿基板通路) 218。可藉由以下步驟形成第二TSV 218：貫穿第二基板200將一貫穿基板溝槽開口1602形成至第二ILD層210中以暴露第二互連結構204之金屬線206之一者，接著將一導電材料填充至貫穿基板溝槽開口1602中。第二TSV 218可具有與第二基板200之一頂表面共面或高於第二基板200之一頂表面之一頂表面。
類似地，如圖2中所展示，可藉由一第二接合結構232將一第三IC晶粒30及一第四IC晶粒40面對面接合在一起。該第三IC晶粒包括一第三基板300及該第三基板上方之一第三互連結構304。第三互連結構304包括交替地堆疊於一第三ILD層310中之第三複數個金屬線306及第三複數個金屬通路308。第四IC晶粒40包括一第四基板400及該第四基板上方之一第四互連結構404。第四互連結構404包括交替地堆疊於一第四ILD層410中之第四複數個金屬線406及第四複數個金屬通路408。第二接合結構232包括接觸第三互連結構304之一第一部分232a及接觸第四互連結構404之一第二部分232b。第二接合結構232亦可包括各自接合介電質層336、436、各自重佈層314、414、各自虛設重佈層316、416及各自接合接點312、412。重佈層314、414及各自虛設重佈層316、416凹入至接合介電質層336、436中且彼此直接接觸。接合接點312、412分別自重佈層314、414延伸至互連結構304、404。接著，自一背側薄化第三基板300以準備一後續接合製程。貫穿第三基板300形成一第三TSV (貫穿基板通路) 318。
如圖3中所展示，藉由一第三接合結構332透過第二TSV 218及第三TSV 318將第二基板200及第三基板300接合在一起。圖2中所展示之製程可同時或在至少與執行圖1中所展示之製程重疊之一時間框架中執行。接著，可將來自圖1及圖2之製程之工件接合在一起。以此方式，可顯著減少所需之製造時間週期。第三接合結構332可不同於第一接合結構132或第二接合結構232。在一些實施例中，第二TSV 218與第三TSV 318直接接觸，且第二基板200與第三基板300直接接觸。第二TSV 218及第三TSV 318可具有沿相反方向傾斜之側壁。在圖3之一自上而下方向上，第三TSV 318之更接近於第三接合結構332之一接合介面之一上部分向外傾斜，而第二TSV 218之更接近於第三接合結構332之一接合介面之一上部分向內傾斜。第二TSV 218及第三TSV 318可具有實質上相同之橫向尺寸。
IC晶粒10、20、30、40可分別包括分佈於基板100、200、300、400內之一或多個半導體裝置102、202、302、402，且運用藉由互連結構104、204、304、404及接合結構132、232、332界定之導電路徑彼此電耦合。半導體裝置102、202、302、402可為例如MOSFET、IGFET、MIM電容器、快閃記憶體單元或類似者。
圖4展示根據一些額外實施例之3D IC之一截面圖。放置於接合介電質層220、320內且在第二TSV 218與第三TSV 318之間，第三接合結構332可進一步包括彼此直接接合之一對重佈層224、324及彼此直接接合之一對虛設重佈層226、326。一對接合接點222、322分別耦合至重佈層224、324。一第二接合金屬線236及一第二接合金屬通路238可放置於第二TSV 218與重佈層224之間。一第三接合金屬線336及一第三接合金屬通路338可放置於第三TSV 318與重佈層324之間。接合金屬線236、336及接合金屬通路238、338提供額外佈線靈活性。
圖5展示根據一些額外實施例之3D IC之一截面圖。該對重佈層224、324可直接接觸各自第二接合金屬線236及第三接合金屬線336。藉由自第三接合結構332省略圖4中所展示之該對接合接點222、322，簡化製造製程且縮短製造時間。
圖6至圖8展示3D IC之一背對背接合結構之各種區域截面圖。應注意，所揭露接合結構標記為「332」，且可為可併入至圖3中所展示之第三接合結構332中或替換圖3中所展示之第三接合結構332之一些額外實施例。所揭露接合結構亦可獨立或併入至其他適用3D IC中。如圖6中所展示，一組重佈層324、接合金屬線336及接合金屬通路338可放置於一接合介電質層320內且在第二TSV 218與第三TSV 318之間。重佈層324、接合金屬線336及接合金屬通路338之側壁可沿相同方向(例如，如圖中所展示般全部向外)傾斜，且與第三TSV 318之彼等側壁相同。如圖7中所展示，一組接合接點702、接合金屬線336及接合金屬通路338可放置於接合介電質層320內且在第二TSV 218與第三TSV 318之間。接合接點702、接合金屬線336及接合金屬通路338之側壁可沿相同方向(例如，如圖中所展示般全部向外)傾斜，且與第三TSV 318之彼等側壁相同。如圖8中所展示，一組接合金屬線336及接合金屬通路338可放置於接合介電質層內320且直接接觸第二TSV 218及第三TSV 318。接合金屬線336及接合金屬通路338之側壁可沿相同方向(例如，如圖中所展示般全部向外)傾斜，且與第三TSV 318之彼等側壁相同。接合金屬線336及接合金屬通路338提供額外佈線靈活性。藉由省略先前實施例之接合接點或重佈層，進一步減小製造時間週期。
圖9至圖14展示根據一些實施例之包含一正面-背面接合結構之3D IC之截面圖。在圖9中，可藉由一第一接合結構132將一第一IC晶粒10及一第二IC晶粒20面對面接合在一起。第一IC晶粒10包括一第一基板100及第一基板100上方之一第一互連結構104。第一互連結構104包括交替地堆疊於一第一ILD層110 (層間介電質層)中之第一複數個金屬線106及第一複數個金屬通路108。第二IC晶粒20包括一第二基板200及在一前側904處放置於第二基板200上方之一第二互連結構204。第二互連結構204包括交替地堆疊於一第二ILD層210中之第二複數個金屬線206及第二複數個金屬通路208。第一接合結構132包括接觸第一互連結構104之一第一部分132a及接觸第二互連結構204之一第二部分132b。第一接合結構132可包括各自接合介電質層136、236、各自重佈層114、214、各自虛設重佈層116、216及各自接合接點112、212。重佈層114、214及各自虛設重佈層116、216凹入至接合介電質層136、236中且彼此直接接觸。接合接點112、212分別自重佈層114、214延伸至互連結構104、204。藉由一第三接合結構332將一第三IC晶粒30接合至第二IC晶粒20之一背側902。第三IC晶粒30包括一第三基板300及該第三基板上方之一第三互連結構304。第三互連結構304包括交替地堆疊於一第三ILD層310中之第三複數個金屬線306及第三複數個金屬通路308。第三接合結構332包括貫穿第二基板200放置之一第二TSV 218及直接接合至第二TSV 218之一接合接點322。接合接點322將第二TSV 218連接至第三IC晶粒30之最接近於第二IC晶粒20之金屬線306之一者。第二TSV 218及接合接點322可具有沿相反方向傾斜之側壁。接合接點322具有小於第二TSV 218之彼橫向尺寸之一橫向尺寸。可藉由在將第三IC晶粒30接合至第二IC晶粒20之前在第三IC晶粒30上方形成一接合介電質層320來形成接合接點322。接著，貫穿接合介電質層320形成一接觸孔以暴露第三互連結構304之金屬線306之一者，接著將一導電材料填充至該接觸孔中。接著，將第三IC晶粒30上下倒置以將接合接點322直接接合至第二TSV 218，該第二TSV 218可具有與第二基板200之一頂表面共面或高於第二基板200之一頂表面之一頂表面。一介電質襯層230可沿著第二TSV 218及第二IC 20之背側902形成於第二基板200上且接合至接合介電質層320。
圖10展示根據一些額外實施例之3D IC之一截面圖。在圖10中，第二IC晶粒20包括第二TSV 218及直接放置於第二TSV 218上之一接合接點222。第二TSV 218及接合接點322可具有沿相同方向傾斜(即，如圖中所展示般向內傾斜)之側壁。接合接點222接合至第三IC晶粒30之金屬線306之最接近於第二IC晶粒20之一者。可藉由在將第二IC晶粒20接合至第三IC晶粒30之前在第二IC晶粒20上方形成一接合介電質層220來形成接合接點222。接著，貫穿接合介電質層220形成一接觸孔以暴露第二TSV 218，接著將一導電材料填充至該接觸孔中。接著，將接合接點222直接接合至第三互連結構304之金屬線306之一者。
圖11展示根據一些額外實施例之3D IC之一截面圖。在圖11中，第三接合結構332之第二TSV 218係貫穿第二基板200放置且直接接合至第三IC晶粒30之最接近於第二IC晶粒20之金屬線306之一者。第二TSV 218及金屬線306可具有沿相反方向傾斜之側壁。第二TSV 218具有小於金屬線306之一橫向尺寸(例如，一長度)之一橫向尺寸。一介電質襯層230可沿著第二TSV 218及第二IC 20之背側形成於第二基板200上且接合至第三ILD層310。介電質襯層230可與第三IC晶粒30之最接近於第二IC晶粒20之金屬線306直接接觸。藉由省略先前實施例之接合接點，進一步減小製造時間週期。
圖12展示根據一些額外實施例之3D IC之一截面圖。在圖12中，一接合重佈層324及一接合接點322係由一接合介電質層320環繞，放置於第三互連結構304上，且電耦合至第三IC晶粒30之最接近於第二IC晶粒20之金屬線306之一者。第二TSV 218係貫穿第二基板200放置且直接接合至接合重佈層324。第二TSV 218及接合重佈層324可具有沿相反方向傾斜之側壁。第二TSV 218具有大於接合重佈層324之彼橫向尺寸之一橫向尺寸。一介電質襯層230可沿著第二TSV 218及第二IC 20之背側形成於第二基板200上且接合至第三ILD層310。介電質襯層230可與接合重佈層324及接合介電質層320直接接觸。藉由省略形成附接至第二基板之一接合重佈層及一接合接點，減小製造時間週期。可藉由在將第三IC晶粒30接合至第二IC晶粒20之前在第三IC晶粒30上方形成接合介電質層320來形成接合重佈層324及接合接點322。接著，貫穿接合介電質層320形成一接觸孔以暴露第三互連結構304之金屬線306之一者，且在覆蓋該接觸孔之接合介電質層之一上部分內形成一溝槽開口。將一導電材料填充於接觸孔及溝槽開口中。接著，將第三IC晶粒30上下倒置以將重佈層324直接接合至第二TSV 218。在接合製程之前，可沿著第二TSV 218及第二IC 20之背側在第二基板200上形成介電質襯層230，該介電質襯層230可在接合製程期間黏附至接合介電質層320。
圖13展示根據一些額外實施例之3D IC之一截面圖。在圖13中，第二IC晶粒20之第二TSV 218及第三IC晶粒30之金屬線306透過由一第二接合介電質層220環繞之一第二接合接點222及由一第三接合介電質層320環繞之一第三接合接點322電耦合。第二接合接點222及第三接合接點322可接合在一起且可具有沿相反方向傾斜之側壁。第二接合介電質層220可在接合製程期間黏附至第三接合介電質層320。
圖14展示根據一些額外實施例之3D IC之一截面圖。在圖14中，一接合重佈層224及一接合接點222係由一接合介電質層220環繞，放置於第二基板200上，且電耦合至第二TSV 218。接合重佈層224直接接合至第三IC晶粒30之最接近於第二IC晶粒20之金屬線306之一者。金屬線306及接合重佈層224可具有沿相反方向傾斜之側壁。可藉由在將第三IC晶粒30接合至第二IC晶粒20之前在第二IC晶粒20上方形成接合介電質層220來形成接合重佈層224及接合接點222。接著，貫穿接合介電質層220形成一接觸孔以暴露第二TSV 218，且在覆蓋該接觸孔之接合介電質層220之一上部分內形成一溝槽開口。在接觸孔及溝槽開口中填充一導電材料以形成接合接點222及接合重佈層224。接著，將第三IC晶粒30接合至重佈層224。第三ILD層310可在接合製程期間黏附至接合介電質層220。
參考圖15至圖19，一系列截面圖1500至1900繪示用於製造具有垂直地堆疊於一起之複數個2D IC之3D IC之一方法之一些實施例。
如由圖15之截面圖1500所繪示，形成一第一IC晶粒10及一第二IC晶粒20且將其等接合在一起。在第一基板100中形成各種裝置元件102。裝置元件102之實例包含電晶體、二極體、記憶體裝置或其他合適元件。可使用各種製程來形成裝置元件102，包含沉積、蝕刻、佈植、光微影、退火及/或其他合適製程。在覆蓋裝置元件102之第一基板100上形成一第一互連結構104。第一互連結構104包含交替地堆疊於一第一ILD層110 (層間介電質層)中之第一複數個金屬線106及第一複數個金屬通路108。第一ILD層110可包含多個介電質子層。第一互連結構104之形成可涉及多個沉積、圖案化及平坦化製程。平坦化製程可包含化學機械拋光(CMP)製程。在一些實施例中，執行一平坦化製程，使得一些金屬線106之頂表面經暴露且與第一ILD層110之頂表面實質上共面。在第一互連結構104上形成一第一接合介電質層120，且一第一接合接點112、一第一重佈層114及一第一虛設重佈層116可形成為凹入至第一接合介電質層136中。為簡單起見，其在此不重複，但可以類似於形成第一IC晶粒10之一方式形成一第二IC晶粒20。第二IC晶粒20包括一第二基板200及該第二基板上方之一第二互連結構204。第二互連結構204包括交替地堆疊於一第二ILD層210中之第二複數個金屬線206及第二複數個金屬通路208。一第二接合接點212、一第二重佈層214及一第二虛設重佈層216可形成為凹入至一第一接合介電質層136中且覆蓋第二互連結構204。接合製程可為包含重佈層114、214及虛設重佈層116、216之導體至導體接合以及接合介電質層136、236之介電質至介電質接合之一混合接合製程。
如由圖16之截面圖1600及圖17之截面圖1700所繪示，貫穿第二基板200形成一第二TSV (貫穿基板通路) 218。在圖16中，首先自一背側薄化第二基板200。薄化製程可包括一化學機械拋光(CMP)製程及/或其他薄化技術。貫穿第二基板200形成一貫穿基板溝槽開口1602至第二ILD層210中以暴露第二互連結構204之金屬線206之一者，接著將一導電材料填充至該貫穿基板溝槽開口中。在一些實施例中，使用一光微影製程及一蝕刻製程來形成貫穿基板溝槽開口1602。在一些實施例中，貫穿基板溝槽開口1602之側壁實質垂直於基板200之頂表面。在一些其他實施例中，貫穿基板溝槽開口1602具有歪斜或傾斜側壁。在一些實施例中，隨著蝕刻製程變深，溝槽逐漸變得更窄，即，溝槽向內傾斜。應明白，其他連接結構可具有相同傾斜構件以便更好地填充。例如，自第二IC晶粒20之一前側來看，金屬線206、金屬通路208、重佈層214、虛設重佈層216及接合接點212分別自遠離第二基板200之一上側至更接近於第二基板200之一下側變得更窄，即，如圖16中所展示般向外傾斜(意謂著該構件沿圖16之自上而下方向變得更寬)。自第一IC晶粒10之一前側來看，金屬線106、金屬通路108、重佈層114、虛設重佈層116及接合接點112分別自遠離第二基板100之一上側至更接近於第二基板100之一下側變得更窄，即，如圖16中所展示般向內傾斜(意謂著該構件沿圖16之自上而下方向變得更窄)。一介電質襯層230可形成於第二IC晶粒20之背側上且沿著貫穿基板溝槽開口1602形成於導電材料與第二基板200之間。導電材料可由例如鋁、銅、鋁銅、一些其他導電材料、前述之組合或類似者形成。導電材料可例如藉由氣相沉積、原子層沉積、電化學佈植、一些其他生長或沉積製程、或前述之組合而形成。在圖17中，回蝕且移除導電材料之過量部分以形成第二TSV 218。第二TSV 218可具有與介電質襯層230之彼頂表面共面之一頂表面。若不存在介電質襯層230或自第二基板200之背側移除介電質襯層230，則第二TSV 218亦可具有與第二基板200之一上表面或頂表面對準之一上表面或頂表面。回蝕製程可包含一平坦化製程，例如一CMP製程。
如由圖18之截面圖1800所繪示，在一第二接合介電質層220內形成一重佈層224、一虛設重佈層226及一接合接點222。仍使用圖16中所描述之定義，自第二IC晶粒20之一背側來看，重佈層224、虛設重佈層226及接合接點222分別自遠離第二基板200之一上側至更接近於第二基板200之一下側變得更窄，即，如圖18中所展示般向內傾斜(意謂著該構件沿圖18之自上而下方向變得更窄)。可藉由貫穿接合介電質層320形成複數個接觸孔以觸及第二TSV 218來形成接合重佈層224及虛設重佈層226及接合接點322。接著，在第二接合介電質層220之一上部分內形成複數個溝槽開口。一些溝槽開口覆蓋接觸孔。在接觸孔及溝槽開口中填充一導電材料，接著進行一平坦化製程。應明白，儘管上文描述一通路優先雙鑲嵌類製程以形成重佈層224及接合接點222，但亦可使用其他製程，諸如溝槽優先雙鑲嵌製程或單鑲嵌製程。
如由圖19之截面圖1900所繪示，一第三IC晶粒30接合至第二IC晶粒20之背側。第三IC晶粒30可包括一第三基板300及第三基板300上方之一第三互連結構304。第三互連結構304包括交替地堆疊於一第三ILD層310中之第三複數個金屬線306及第三複數個金屬通路308。將接合重佈層224及虛設重佈層226接合至第三IC晶粒30之最接近於第二IC晶粒20之金屬線306。可藉由構件之側壁之傾斜方向來偵測第三IC晶粒30及第二IC晶粒20之一接合介面。仍使用圖16中所描述之定義，自第三IC晶粒30之一前側來看，金屬線306及金屬通路308如圖19中所展示般向外傾斜(意謂著構件沿圖19之自上而下方向變得更寬)。因此，金屬線306及金屬通路308之側壁沿與接合重佈層224及虛設重佈層226之傾斜方向(向內)相反之一方向(向外)傾斜。儘管圖中未展示，但可沿著金屬線306、重佈層224及虛設重佈層226之各自側壁及底表面而非沿著其中金屬線306接合至重佈層224或虛設重佈層226之接合介面形成阻障襯層。
應注意，圖15至圖19繪示用來形成具有對應於圖14之一結構之3D IC之一些實施例之一些實例製造製程。應明白，圖15至圖19中所展示之製程可經更改以如其他圖中所展示般形成3D IC之一些其他實施例。例如，可將第三IC晶粒30上下倒置以背側接合至第二IC晶粒20以形成圖4至圖8中所展示之結構；可在將第三IC晶粒30接合至第二IC晶粒20之前在第三互連結構310上形成接合介電質層320及接合接點322以準備圖9中所展示之結構；可省略在第二互連結構210上形成重佈層224以為圖10中所展示結構準備第二IC晶粒20，可進一步省略在第二互連結構210上形成接合接點222以為圖11中所展示之結構準備第二IC晶粒20，且依此類推。應明白，形成於兩個IC晶粒之間的組件有助於提供更好(例如，更平坦)接合介面，且額外金屬線有助於提供更靈活佈線。然而，額外接合組件層係製程耗時的。隨著平坦化製程改良，可減少或省略彼等層，此將減小製程週期時間。
圖20展示形成一積體電路裝置之一方法2000之一流程圖之一些實施例。儘管關於圖1至圖3描述方法2000，但將明白，方法2000不限於圖1至圖3中所揭露之此等結構，而是取而代之可獨立於圖1至圖3中所揭露之結構。類似地，將明白，圖1至圖3中所揭露之結構不限於方法2000，而是取而代之可獨立作為獨立於方法2000之結構。而且，儘管所揭露方法(例如，方法2000)在下文被繪示及描述為一系列動作或事件，但將明白，此等動作或事件之所繪示排序不應被解釋為具限制意義。例如，一些動作可以不同順序發生及/或與除本文中所繪示及/或描述之彼等動作或事件之外的其他動作或事件同時發生。另外，可能不需要所有所繪示動作來實施本文描述之一或多個態樣或實施例。此外，本文中所描繪之動作之一或多者可在一或多個單獨動作及/或階段中執行。
在2002，提供且接合一第一IC晶粒及一第二IC晶粒。第一IC晶粒包括一第一基板及該第一基板上方之一第一互連結構。第二IC晶粒包括一第二基板及該第二基板上方之一第二互連結構。藉由一第一接合結構將第二IC晶粒接合至第一IC晶粒，該第一接合結構包括接觸第一互連結構之一第一部分及接觸第二互連結構之一第二部分。
在2004，薄化第二基板。貫穿第二基板形成一第二TSV。例如，圖1展示對應於動作2002及動作2004之一截面圖100之一些實施例。
在2006，提供且接合一第三IC晶粒及一第四IC晶粒。第三IC晶粒包括一第三基板及該第三基板上方之一第三互連結構。第四IC晶粒包括一第四基板及該第四基板上方之一第四互連結構。藉由一第二接合結構將第四IC晶粒接合至第三IC晶粒，該第二接合結構包括接觸第三互連結構之一第一部分及接觸第四互連結構之一第二部分。
在2008，薄化第三基板。貫穿第三基板形成一第三TSV。例如，圖2展示對應於動作2006及動作2008之一截面圖200之一些實施例。
在2010，透過第二TSV及第三TSV接合第二基板及第三基板。例如，圖3展示對應於動作2010之一截面圖300之一些實施例。
將明白，儘管本文件通篇參考實例性結構論述本文中所描述之方法論之態樣，但彼等方法論不受限於所提出之對應結構。相反，方法論(及結構)應被視為彼此獨立且能夠無關於圖中所描繪之特定態樣之任一者而獨立及實踐。另外，本文中所描述之層可以任何合適方式形成，諸如利用旋塗、濺鍍、生長及/或沉積技術等。
鑑於前述內容，本申請案之一些實施例提供一種3D IC。一第一IC晶粒包括一第一基板上方之一第一互連結構。一第二IC晶粒藉由一第一接合結構接合至該第一IC晶粒且包括一第二基板上方之一第二互連結構。該第一接合結構包括接觸該第一互連結構之一第一部分及接觸該第二互連結構之一第二部分。該第一部分及該第二部分混合接合在一起。一第三IC晶粒包括一第三基板及該第三基板上方之一第三互連結構。該第三IC晶粒藉由一第三接合結構接合至該第二IC晶粒。該第三接合結構配置於相對於對應互連結構之該第二IC晶粒之背側與該第三IC晶粒之背側之間，且包括貫穿該第二基板放置之一第二TSV (貫穿基板通路)及貫穿該第三基板放置之一第三TSV。
此外，本申請案之其他實施例提供另一3D IC。該3D IC包括一第一IC晶粒及一第二IC晶粒，該第二IC晶粒具有一前側及與該前側相對之一背側。該第一IC晶粒藉由一第一接合結構接合至該第二IC晶粒之該前側。一第三IC晶粒藉由一第三接合結構接合至該第二IC晶粒之該背側。該第三接合結構包括貫穿該第二基板放置且直接接合至一導電構件之一第二TSV (貫穿基板通路)，該導電構件具有沿與該第二TSV之一側壁相反之一方向傾斜之側壁。
又進一步，本申請案之其他實施例提供一種用於製造3D IC之方法。接合一第一IC晶粒及一第二IC晶粒。該第一IC晶粒包括一第一基板及該第一基板上方之一第一互連結構。該第二IC晶粒包括一第二基板及該第二基板上方之一第二互連結構。該第二IC晶粒藉由一第一接合結構接合至該第一IC晶粒，該第一接合結構包括接觸該第一互連結構之一第一部分及接觸該第二互連結構之一第二部分。接合一第三IC晶粒及一第四IC晶粒。該第三IC晶粒包括一第三基板及該第三基板上方之一第三互連結構，且該第四IC晶粒包括一第四基板及該第四基板上方之一第四互連結構。該第四IC晶粒藉由一第二接合結構接合至該第三IC晶粒，該第二接合結構包括接觸該第三互連結構之一第一部分及接觸該第四互連結構之一第二部分。分別薄化該第二基板及該第三基板，且分別貫穿該第二基板及該第三基板形成一第二TSV及一第三TSV。透過該第二TSV及該第三TSV接合該第二基板及該第三基板。
前述內容概述若干實施例之特徵，使得熟習此項技術者可更好地理解本揭露之態樣。熟習此項技術者應明白，其等可容易使用本揭露作為設計或修改用於實行本文中所介紹之實施例之相同目的及/或達成相同優點之其他製程及結構之一基礎。熟習此項技術者亦應認知，此等等效構造不背離本揭露之精神及範疇，且其等可在不背離本揭露之精神及範疇之情況下在本文中作出各種改變、置換及更改。
10‧‧‧第一積體電路(IC)晶粒 20‧‧‧第二IC晶粒 30‧‧‧第三IC晶粒 40‧‧‧第四IC晶粒 100‧‧‧第一基板/截面圖 102‧‧‧半導體裝置/裝置元件 104‧‧‧第一互連結構 106‧‧‧第一複數個金屬線 108‧‧‧第一複數個金屬通路 110‧‧‧第一層間介電質層(ILD) 112‧‧‧第一接合接點 114‧‧‧第一重佈層 116‧‧‧第一虛設重佈層 120‧‧‧第一接合介電質層 132‧‧‧第一接合結構 132a‧‧‧第一部分 132b‧‧‧第二部分 136‧‧‧第一接合介電質層 200‧‧‧第二基板/截面圖 202‧‧‧半導體裝置 204‧‧‧第二互連結構 206‧‧‧第二複數個金屬線 208‧‧‧第二複數個金屬通路 210‧‧‧第二ILD層 212‧‧‧第二接合接點 214‧‧‧第二重佈層 216‧‧‧第二虛設重佈層 218‧‧‧第二貫穿基板通路(TSV) 220‧‧‧第二接合介電質層 222‧‧‧第二接合接點 224‧‧‧重佈層 226‧‧‧虛設重佈層 230‧‧‧介電質襯層 232‧‧‧第二接合結構 232a‧‧‧第一部分 232b‧‧‧第二部分 236‧‧‧接合介電質層/第二接合金屬線 238‧‧‧第二接合金屬通路 300‧‧‧第三基板/截面圖 302‧‧‧半導體裝置 304‧‧‧第三互連結構 306‧‧‧第三複數個金屬線 308‧‧‧第三複數個金屬通路 310‧‧‧第三ILD層 312‧‧‧接合接點 314‧‧‧重佈層 316‧‧‧各自虛設重佈層 318‧‧‧第三TSV 320‧‧‧第三接合介電質層 322‧‧‧第三接合接點 324‧‧‧重佈層 326‧‧‧虛設重佈層 332‧‧‧第三接合結構 336‧‧‧接合介電質層/第三接合金屬線 338‧‧‧第三接合金屬通路 400‧‧‧第四基板 402‧‧‧半導體裝置 404‧‧‧第四互連結構 406‧‧‧第四複數個金屬線 408‧‧‧第四複數個金屬通路 410‧‧‧第四ILD層 412‧‧‧接合接點 414‧‧‧重佈層 416‧‧‧各自虛設重佈層 436‧‧‧接合介電質層 702‧‧‧接合接點 902‧‧‧背側 904‧‧‧前側 1500‧‧‧截面圖 1600‧‧‧截面圖 1602‧‧‧貫穿基板溝槽開口 1700‧‧‧截面圖 1800‧‧‧截面圖 1900‧‧‧截面圖 2000‧‧‧方法 2002‧‧‧動作 2004‧‧‧動作 2006‧‧‧動作 2008‧‧‧動作 2010‧‧‧動作
當結合附圖閱讀時，自下文詳細描述最好地理解本揭露之態樣。應注意，根據標準行業實踐，各種構件不一定按比例繪製。事實上，為清楚論述起見，可任意增大或減小各種構件之尺寸。
圖1至圖3繪示根據一些實施例之用於製造包含一背對背接合結構之三維(3D)積體電路(IC)之一方法之一系列截面圖。
圖4及圖5繪示根據一些替代實施例之包含一背對背接合結構之3D IC之截面圖。
圖6至圖8繪示根據一些額外實施例之包含一背對背接合結構之3D IC之各種區域截面圖。
圖9至圖14繪示根據一些實施例之包含一正面-背面接合結構之3D IC之截面圖。
圖15至圖19繪示根據一些實施例之用於製造包含一正面-背面接合結構之三維(3D)積體電路(IC)之一方法之一系列截面圖。
圖20繪示根據一些實施例之形成一積體電路裝置之方法之流程圖。
10‧‧‧第一積體電路(IC)晶粒
20‧‧‧第二IC晶粒
30‧‧‧第三IC晶粒
40‧‧‧第四IC晶粒
100‧‧‧第一基板/截面圖
102‧‧‧半導體裝置/裝置元件
104‧‧‧第一互連結構
106‧‧‧第一複數個金屬線
108‧‧‧第一複數個金屬通路
110‧‧‧第一層間介電質層(ILD)
112‧‧‧第一接合接點
114‧‧‧第一重佈層
116‧‧‧第一虛設重佈層
132‧‧‧第一接合結構
200‧‧‧第二基板/截面圖
204‧‧‧第二互連結構
210‧‧‧第二ILD層
212‧‧‧第二接合接點
214‧‧‧第二重佈層
216‧‧‧第二虛設重佈層
218‧‧‧第二貫穿基板通路(TSV)
220‧‧‧第二接合介電質層
222‧‧‧第二接合接點
224‧‧‧重佈層
226‧‧‧虛設重佈層
232‧‧‧第二接合結構
236‧‧‧接合介電質層/第二接合金屬線
238‧‧‧第二接合金屬通路
300‧‧‧第三基板/截面圖
304‧‧‧第三互連結構
310‧‧‧第三ILD層
312‧‧‧接合接點
314‧‧‧重佈層
316‧‧‧各自虛設重佈層
318‧‧‧第三TSV
320‧‧‧第三接合介電質層
322‧‧‧第三接合接點
324‧‧‧重佈層
326‧‧‧虛設重佈層
332‧‧‧第三接合結構
336‧‧‧接合介電質層/第三接合金屬線
338‧‧‧第三接合金屬通路
400‧‧‧第四基板
402‧‧‧半導體裝置
404‧‧‧第四互連結構
406‧‧‧第四複數個金屬線
408‧‧‧第四複數個金屬通路
410‧‧‧第四ILD層
412‧‧‧接合接點
414‧‧‧重佈層
416‧‧‧各自虛設重佈層

Claims (20)

  1. 一種三維(3D)積體電路(IC)，其包括： 一第一IC晶粒，其包括一第一基板及該第一基板上方之一第一互連結構； 一第二IC晶粒，其包括一第二基板及該第二基板上方之一第二互連結構，其中該第二IC晶粒藉由一第一接合結構接合至該第一IC晶粒，該第一接合結構包括接觸該第一互連結構之一第一部分及接觸該第二互連結構之一第二部分，其中該第一部分及該第二部分混合接合在一起；及 一第三IC晶粒，其包括一第三基板及該第三基板上方之一第三互連結構，其中該第三IC晶粒藉由一第三接合結構接合至該第二IC晶粒，其中該第三接合結構配置於相對於對應互連結構之該第二IC晶粒之背側與該第三IC晶粒之背側之間，且包括貫穿該第二基板放置之一第二TSV (貫穿基板通路)及貫穿該第三基板放置之一第三TSV。
  2. 如請求項1之3D IC， 其中該第二TSV與該第三TSV直接接觸，且該第二基板與該第三基板直接接觸。
  3. 如請求項1之3D IC， 其中該第三接合結構進一步包括放置於該第二TSV與該第三TSV之間的一接合金屬線及一接合金屬通路。
  4. 如請求項3之3D IC， 其中該第三接合結構進一步包括放置於該第二TSV與該第三TSV之間的一重佈層。
  5. 如請求項4之3D IC， 其中該接合金屬線與該重佈層直接接觸。
  6. 如請求項1之3D IC， 其中該第一互連結構包括交替地堆疊於一第一ILD層(層間介電質層)中之第一複數個金屬線及第一複數個金屬通路； 其中該第二互連結構包括交替地堆疊於一第二ILD層中之第二複數個金屬線及第二複數個金屬通路；且 其中該第三互連結構包括交替地堆疊於一第三ILD層中之第三複數個金屬線及第三複數個金屬通路。
  7. 如請求項6之3D IC， 其中該第二TSV覆蓋該第二互連結構，觸及最接近於該第二基板之該第二複數個金屬線之一者；且 其中該第三TSV覆蓋該第三互連結構，觸及最接近於該第三基板之該第三複數個金屬線之一者。
  8. 如請求項1之3D IC， 其中該第一接合結構之該第一部分包括一第一接合介電質層、一第一重佈層及自該第一重佈層延伸至該第一互連結構之一第一接合接點； 其中該第一接合結構之該第二部分包括一第二接合介電質層、一第二重佈層及自該第二重佈層延伸至該第二互連結構之一第二接合接點； 其中該第一接合介電質層及該第二接合介電質層直接接觸以界定一介電質至介電質介面，其中該第一重佈層及該第二重佈層直接接觸以界定與該介電質至介電質介面對準之一導體至導體介面。
  9. 如請求項1之3D IC，其進一步包括： 一第四IC晶粒，其包括一第四基板及該第四基板上方之一第四互連結構，其中該第四IC晶粒藉由一第二接合結構接合至該第三IC晶粒，該第二接合結構包括接觸該第三互連結構之一第一部分及接觸該第四互連結構之一第二部分，其中該第一部分及該第二部分混合接合在一起。
  10. 如請求項3之3D IC， 其中該第三接合結構不同於該第一接合結構或該第二接合結構。
  11. 一種三維(3D)積體電路(IC)，其包括： 一第一IC晶粒； 一第二IC晶粒，其包括一第二基板及該第二基板上方之一第二互連結構，該第二IC晶粒具有一前側及與該前側相對之一背側，其中該第一IC晶粒藉由一第一接合結構接合至該第二IC晶粒之該前側；及 一第三IC晶粒，其包括一第三基板及該第三基板上方之一第三互連結構，其中該第三IC晶粒藉由一第三接合結構接合至該第二IC晶粒之該背側，其中該第三接合結構包括貫穿該第二基板放置且直接接合至該第三IC晶粒之一導電構件之一第二TSV (貫穿基板通路)，該導電構件具有沿與該第二TSV之一側壁相反之一方向傾斜之一側壁。
  12. 如請求項11之3D IC，其中該第二IC晶粒之該背側接合至該第三IC晶粒之一前側。
  13. 如請求項12之3D IC，其中該第二TSV藉由一接合接點接合至該第三IC晶粒之該前側，該接合接點具有小於該第二TSV之一橫向尺寸。
  14. 如請求項12之3D IC，其中該第二TSV藉由一接合金屬線接合至該第三IC晶粒之該前側，該接合金屬線具有大於該第二TSV之彼橫向尺寸之一橫向尺寸。
  15. 如請求項12之3D IC，其中該第二TSV藉由一接合重佈層接合至該第三IC晶粒之該前側，該接合重佈層具有大於該第二TSV之彼橫向尺寸之一橫向尺寸。
  16. 如請求項11之3D IC，其中該第三接合結構配置於與該第三IC晶粒之該第三互連結構相對之該第二IC晶粒之該背側與該第三IC晶粒之一背側之間，且進一步包括貫穿該第三基板放置之一第三TSV。
  17. 如請求項11之3D IC，其中一接合接點放置於該第二TSV與該第三IC晶粒之最接近於該第二IC晶粒之一金屬線之間且與該第二TSV及該第三IC晶粒之最接近於該第二IC晶粒之一金屬線直接接觸。
  18. 如請求項11之3D IC，其中該第三接合結構進一步包括直接接合至該第二TSV之一重佈層及將該重佈層連接至該第三IC晶粒之最接近於該第二IC晶粒之一金屬線之一接合接點。
  19. 一種用於製造一個三維(3D)積體電路(IC)之方法，該方法包括： 提供且接合一第一IC晶粒及一第二IC晶粒，該第一IC晶粒包括一第一基板及該第一基板上方之一第一互連結構且該第二IC晶粒包括一第二基板及該第二基板上方之一第二互連結構，其中該第二IC晶粒藉由一第一接合結構接合至該第一IC晶粒，該第一接合結構包括接觸該第一互連結構之一第一部分及接觸該第二互連結構之一第二部分； 薄化該第二基板且貫穿該第二基板形成一第二TSV； 提供且接合一第三IC晶粒及一第四IC晶粒，該第三IC晶粒包括一第三基板及該第三基板上方之一第三互連結構且該第四IC晶粒包括一第四基板及該第四基板上方之一第四互連結構，其中該第四IC晶粒藉由一第二接合結構接合至該第三IC晶粒，該第二接合結構包括接觸該第三互連結構之一第一部分及接觸該第四互連結構之一第二部分； 薄化該第三基板且貫穿該第三基板形成一第三TSV；及 透過該第二TSV及該第三TSV接合該第二基板及該第三基板。
  20. 如請求項19之方法，其進一步包括： 在該第二基板及該第三基板之該接合之前，在該第二基板或該第三基板上形成一接合介電質層；及 在該接合介電質層內形成一對接合金屬線及一對重佈層，該等重佈層分離該等接合金屬線。
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