TW201947678A - 覆晶封裝基板之製法及其結構 - Google Patents

覆晶封裝基板之製法及其結構 Download PDF

Info

Publication number
TW201947678A
TW201947678A TW107115944A TW107115944A TW201947678A TW 201947678 A TW201947678 A TW 201947678A TW 107115944 A TW107115944 A TW 107115944A TW 107115944 A TW107115944 A TW 107115944A TW 201947678 A TW201947678 A TW 201947678A
Authority
TW
Taiwan
Prior art keywords
conductive
flip
package substrate
chip package
insulating
Prior art date
Application number
TW107115944A
Other languages
English (en)
Other versions
TWI713842B (zh
Inventor
周保宏
余俊賢
許詩濱
郭同堯
Original Assignee
恆勁科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 恆勁科技股份有限公司 filed Critical 恆勁科技股份有限公司
Priority to TW107115944A priority Critical patent/TWI713842B/zh
Priority to CN201810894212.7A priority patent/CN110473788A/zh
Priority to JP2018203464A priority patent/JP2019197881A/ja
Priority to US16/404,856 priority patent/US11476204B2/en
Publication of TW201947678A publication Critical patent/TW201947678A/zh
Application granted granted Critical
Publication of TWI713842B publication Critical patent/TWI713842B/zh
Priority to US17/891,184 priority patent/US20220406734A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

一種覆晶封裝基板之製法及其結構，該製法係包括於將複數具有導電柱之絕緣層相互堆疊，使各該導電柱相互接觸疊置，以令該些絕緣層與該些導電柱作為該覆晶封裝基板之核心層結構，故藉由本發明所製作之該核心層結構，能依需求而製作出小端面尺寸之導電柱，因此當該核心層結構之厚度增加時，不僅能增加該覆晶封裝基板之剛性強度而避免發生板翹，且更保有能將導電柱之端面尺寸微小化設計的彈性，因而能於該核心層結構上製作高密度佈設的電性連接點、細線路間距及高密度佈線之線路層者。

Description

覆晶封裝基板之製法及其結構
本發明係有關一種覆晶封裝基板技術，尤指一種半導體封裝製程用之覆晶封裝基板之製法及其結構。
隨著產業應用的發展，近年來逐漸朝向5G高頻通訊、AR、VR等發展，因此更需要研發高階半導體的封裝技術，以應用於諸如人工智慧(AI)晶片、高階晶片、多晶片等之半導體覆晶封裝或多晶片封裝，而在此封裝需求之下，封裝尺寸勢必越來越大，疊層數也越來越高，導致線路設計更是朝高密度、細線路間距、高電性連接點數等方向設計，藉以滿足上揭晶片之封裝需求。
目前在高階晶片封裝及應用的缺點是現有的覆晶封裝基板，因要配合高集積尺寸晶片(如AI晶片等)之封裝，且為了滿足更多的電性連接點數量、大量且複雜的線路需求、以及避免板翹現象之發生，所以勢必要加厚其核心層尺寸，但也因而造成該核心層之通孔(Through hole)之斷面尺寸變大，致使其電性連接點之間距也變大，故導致在單位面積內之電性連接點之數量變少、線路密度變低、線路間距 變大，而為了滿足上揭需求，只好將覆晶封裝基板的尺寸變得更大、更厚，因而造成封裝作業變得更加困難。
因此，現有業界是使用大尺寸的覆晶封裝基板，如45*45、70*70或80*80等大尺寸覆晶封裝基板結構，以承載如人工智慧(AI)晶片、高階晶片或多晶片等高積集尺寸晶片來進行封裝。如第1A圖所示，該電子裝置1係包括：一電路板18、一設於該電路板18上之大尺寸版面覆晶封裝基板1a、以及一結合於該覆晶封裝基板1a上之高集積尺寸半導體晶片19。具體地，如第1B圖所示，該覆晶封裝基板1a係包括一核心層10、設於該核心層10上、下兩側面上之增層(Build up)結構11、及設於該增層結構11上之防焊層12，其中，該核心層10具有導電通孔100以電性連接該增層結構11之線路層110，且該增層結構11復包含至少一包覆該些線路層110之介電層111，並令該防焊層12外露出該增層結構11最外側之線路層110，俾供作為電性連接點112，以藉由焊錫材料13結合該電路板18及該半導體晶片19。
習知核心層10之製作中，係採用玻纖配合環氧樹酯所組成之基材，如BT(Bismaleimide Triazine)或FR5等，再於其上進行導電通孔100製程，如機械鑽孔、雷射鑽孔或雙錐狀盲孔(如第1C圖所示之導電通孔100’)等成孔步驟，再於孔中電鍍導電層或再填入填充材(如第1B及1C圖所示之全部導電通孔100,100’、或如第1D圖所示之導電材100a與絕緣材100b)。
然而，習知應用於大尺寸的覆晶封裝基板1a會產生明顯缺點，例如：該核心層10係採用玻纖配合環氧樹酯所組成之基材，因該覆晶封裝基板1a於各層間材料之熱膨脹係數(Coefficient of thermal expansion，簡稱CTE)不一致，因而於封裝時易產生板翹，致使其與該半導體晶片19之間連接不良(如焊錫材料13’未接合或斷裂)、或於焊接時，其與該電路板18之間會發生連接不良(如焊錫材料13”未接合或斷裂)，更嚴重的是可能因為應力關係，會造成該半導體晶片19本身的電性失效、或該半導體晶片19破裂。
因此，業界遂有將該核心層10之厚度h加厚，如厚度h從原本0.8公厘(mm)(其搭配0.1mm的孔徑w)增加至1.2mm(其需搭配0.2mm以上的孔徑w)，以增加該覆晶封裝基板1a之剛性強度，藉以改善板翹問題，但卻因而產生更多的缺點，如下：
第一、單位面積內之電性連接點的數量無法增加。具體地，加厚該核心層10之結果，造成在傳統技術之下勢必讓該些導電通孔100,100’的端面尺寸變大(即該孔徑w變大)，進而造成該些導電通孔100,100’的間距變大，故導致單位面積內電性連接點的數量變少。
第二、線路間距變大及線路密度變低。具體地，加厚該核心層10之結果，造成在傳統技術之下勢必讓該些導電通孔100,100’的端面尺寸變大而佔用佈線面積，導致其上方線路層110之線路佈線面積縮減，進而難以製作細線路間距或高密度線路之線路層110。
第三、該導電通孔100,100’內更難完成電鍍及順利填入填充材。具體地，加厚該核心層10之結果，將導致該些導電通孔100,100’變深，因而更難以在變深的導電通孔100,100’內完成電鍍，甚至產生包孔現象，亦難以將填充材100b順利的填入變深的導電通孔100,100’內。
第四、該導電通孔100,100’之加工成本與難度隨著該核心層10加厚而變高。具體地，茲因習知核心層10是採用含玻纖之介電材來加厚該核心層10以改善板翹之問題，但是於該材質上以雷射或機械鑽孔進行較深的導電通孔100,100’加工時，不但難以製造出細小端面尺寸之導電通孔100,100’，更因而致使製作成本居高不下。
因此，如何克服習知技術中之種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失，本發明提供一種覆晶封裝基板之製法，係包括：提供一承載板，且於該承載板上形成有一第一絕緣層；於該第一絕緣層中形成複數第一導電柱；於該第一絕緣層上形成至少一第二絕緣層，以令該第一與第二絕緣層作為絕緣部：於該第二絕緣層中形成複數第二導電柱，使該第一與第二導電柱相互接觸疊置以作為導電部，以令該絕緣部與該複數導電部作為核心層結構，且該核心層結構具有相對之第一表面與第二表面；移除該承載板；以及於該核心層結構之第一與第二表面上同時或分次形成線路部，且該線路部係電性連接該導電柱。
本發明亦提供一種覆晶封裝基板之製法，係包括：提供一承載板，且於該承載板上形成有相互接觸疊置之複數導電柱，以令該些導電柱作為導電部；形成一絕緣部於該承載板上以包覆該導電部，以令該絕緣部與該導電部作為核心層結構，且該核心層結構具有相對之第一表面與第二表面；移除該承載板；以及於該核心層結構之第一與第二表面上同時或分次形成線路部，且該線路部係電性連接該導電部。
本發明復提供一種覆晶封裝基板之製法，係包括：提供一絕緣部，其具有相對之第一側與第二側；於該絕緣部之第一側上形成複數第一通孔；於該絕緣部之第二側上形成對應該第一通孔的複數第二通孔，使相對應的該第一通孔與該第二通孔相連通；於該第一通孔中形成第一導電柱，且於該第二通孔中形成第二導電柱，使該第一與第二導電柱相互接觸疊置以作為導電部，以令該絕緣部與該導電部作為核心層結構，且該核心層結構具有相對之第一表面與第二表面；以及於該核心層結構之第一與第二表面上同時或分次形成線路部，且該線路部係電性連接該導電部。
前述之覆晶封裝基板之製法中，該導電柱的製作方式係為電鍍、沉積或填塞導電材製程。
本發明又提供一種覆晶封裝基板，係包括：複數導電部，且每一導電部係具有相互接觸疊置之至少一第一導電柱與至少一第二導電柱；絕緣部，係包覆該複數導電部，以令該絕緣部與該些複數導電部作為核心層結構，且該核 心層結構具有相對之第一表面與第二表面；以及線路部，係設於該核心層結構之第一表面及/或第二表面上並電性連接該導電部。
前述之覆晶封裝基板之製法及其結構中，至少二搭疊之該導電柱之端面尺寸係可相同或不相同。例如，第一導電柱之端面尺寸與第二導電柱之端面尺寸係相同或不相同。
前述之覆晶封裝基板之製法及其結構中，形成該絕緣部之材質可為不包含玻纖之有機介電材(如防焊材)或不包含玻纖之無機介電材(如絕緣氧化物)。具體地，該有機介電材之種類更包含鑄模化合物、環氧模壓樹脂(EMC)或底層塗料。
前述之覆晶封裝基板之製法及其結構中，該線路部係為單層線路形式或增層形式。
前述之覆晶封裝基板之製法及其結構中，該導電部係直接或間接電性連接該線路部。
由上可知，本發明之覆晶封裝基板之製法及其結構中，當為了增加該覆晶封裝基板之剛性強度而增加該絕緣部之厚度時，該導電部之端面尺寸無需增大，甚至能縮小，故相較於習知技術，本發明之覆晶封裝基板不僅具有足夠之剛性強度以避免封裝件發生板翹，且該導電部之端面尺寸可依需求朝微小化設計，因而能增加單位面積內電性連接點之數量，以及製作出細線路間距之高密度線路層，進而能滿足高集積晶片之封裝需求者。
1‧‧‧電子裝置
1a‧‧‧覆晶封裝基板
10‧‧‧核心層
100,100’‧‧‧導電通孔
100a‧‧‧導電材
100b‧‧‧絕緣材
11‧‧‧增層結構
110‧‧‧線路層
111‧‧‧介電層
112‧‧‧接點
12‧‧‧防焊層
13,13’,13”‧‧‧焊錫材料
18‧‧‧電路板
19‧‧‧半導體晶片
2,2’,2”‧‧‧核心層結構
2a,2a’,4a‧‧‧絕緣部
2b,4b,5a,5b,5c‧‧‧導電部
2c,2c’,4c,4c’‧‧‧線路部
20‧‧‧承載板
20a‧‧‧第一表面
20b‧‧‧第二表面
21‧‧‧第一絕緣層
21a‧‧‧表面
210,410‧‧‧第一通孔
22,42‧‧‧第一導電柱
220,240,420,440‧‧‧導電墊部
22a‧‧‧端面
23‧‧‧第二絕緣層
230,430‧‧‧第二通孔
24,44‧‧‧第二導電柱
250,350‧‧‧第一線路層
260,360,56‧‧‧第二線路層
3,3’,4,4’‧‧‧覆晶封裝基板
3”,4”‧‧‧電子封裝件
30‧‧‧電子元件
31‧‧‧導電凸塊
32‧‧‧底膠
35‧‧‧第一線路結構
351‧‧‧第一介電層
352,362‧‧‧電性接觸墊
36‧‧‧第二線路結構
361‧‧‧第二介電層
37a,37b‧‧‧絕緣保護層
38‧‧‧焊錫凸塊
39‧‧‧導電元件
40a‧‧‧第一側
40b‧‧‧第二側
46‧‧‧金屬材
50‧‧‧第三導電柱
80‧‧‧種子層
90‧‧‧阻層
900‧‧‧開口區
91‧‧‧第一阻層
910‧‧‧第一開口區
92‧‧‧第二阻層
920‧‧‧第二開口區
S‧‧‧凹凸狀
H,h,L,t1,t2‧‧‧厚度
a,d1,d2,t,t’,r,r’‧‧‧寬度
w‧‧‧孔徑
第1A圖係為習知電子裝置之剖視示意圖；第1B圖係為習知封裝基板之剖視示意圖；第1C及1D圖係為各種習知導電通孔之剖視示意圖；第2A至2F圖係為本發明之覆晶封裝基板之製法之第一實施例之剖視示意圖；第2B’圖係為第2B圖之上視示意圖，第2C’圖係為第2C圖之另一實施例，第2D’圖係為第2D圖之上視示意圖，第2E’圖係為第2E圖之局部立體圖，第2F’圖係為第2F圖之另一實施例；第2F-1圖係為第2F圖之再一實施例；第2F-2圖係為第2F’圖之另一實施例；第2G圖係為第2F-1圖之應用之剖視示意圖；第2G’圖係為第2F-2圖之應用之剖視示意圖；第3A至3G圖係為本發明之覆晶封裝基板之製法之第二實施例之剖視示意圖；第3G’圖係為第3G圖之另一實施例；第3H圖係為第3G圖之應用之剖視示意圖；第3H’圖係為第3G’圖之應用之剖視示意圖；第4A至4D圖係為本發明之覆晶封裝基板之製法之第三實施例之剖視示意圖；第4D’圖係為第4D圖之另一實施例；第4E圖係為第4D圖之應用之剖視示意圖；第4E’圖係為第4D’圖之應用之剖視示意圖；以及第5A至5E圖係為本發明之覆晶封裝基板之核心層結 構之不同實施例的剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”、“第三”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2F圖係為本發明之覆晶封裝基板3,3’之製法之第一實施例的剖視示意圖。
如第2A圖所示，先依封裝需求決定核心層結構2(如第2E圖所示)的厚度尺寸，並據此決定該核心層結構2的分層層數(本實施例係分為二層)；之後，再據以於一承載板20上形成一第一絕緣層21，且藉由圖案化製程，於該第一絕緣層21上形成複數第一通孔210。
於本實施例中，該第一絕緣層21係以鑄模方式、塗佈 方式或壓合方式形成於該承載板20上，且形成該第一絕緣層21之材質係為不包含玻纖之有機介電材(如防焊材)或不包含玻纖之無機介電材(如絕緣氧化物)。具體地，該有機介電材之種類更包含鑄模化合物(Molding Compound)、環氧模壓樹脂(Epoxy Molding Compound，簡稱EMC)或底層塗料(Primer)。
再者，茲因該第一絕緣層21的厚度薄，因此藉由雷射方式即可輕易且快速地形成所需細小端面尺寸之第一通孔210。
如第2B圖所示，於該第一絕緣層21之第一通孔210中形成第一導電柱22。
於本實施例中，該第一導電柱22之周面未延伸有線路，如第2B’圖所示。
再者，該第一導電柱22的製作方式，除了電鍍或沉積製程之外，亦可採用直接在該第一通孔210中填塞導電材(如錫膏、導電膠等)之方式製作。
如第2C圖所示，於該第一絕緣層21上形成一第二絕緣層23，且藉由圖案化製程，於該第二絕緣層23上形成複數對應外露各該第一導電柱22之第二通孔230。
於本實施例中，該第二絕緣層23係以鑄模方式、塗佈方式或壓合方式形成於該第一絕緣層21上，且形成該第二絕緣層23之材質係為不包含玻纖之有機介電材(如防焊材)或不包含玻纖之無機介電材(如絕緣氧化物)。具體地，該有機介電材之種類更包含鑄模化合物、環氧模壓樹脂 (EMC)或底層塗料。
再者，茲因該第二絕緣層23之厚度薄，所以藉由雷射方式即可輕易且快速地形成所需細小端面尺寸之第二通孔230。
又，該第二通孔230之寬度t係可相同或相異於該第一通孔210之寬度r(本實施例係t<r)；或者，如第2C’圖所示之實施例，該第二通孔230之寬度t’亦可大於該第一通孔210之寬度r’(本實施例係t’>r’)。
如第2D圖所示，接續第2C圖之製程，於該第二絕緣層23之第二通孔230中以電鍍、沉積或填塞導電材等製程形成第二導電柱24，且該第二導電柱24係接觸堆疊於該第一導電柱22上，其中，該第一導電柱22之寬度d1(約為0.06mm)與該第二導電柱24之寬度d2(約為0.04mm)係不相同，使該第一導電柱22與該第二導電柱24的端面交界處呈凹凸狀S，如階梯。
於本實施例中，該第二導電柱24之周面未延伸有線路，如第2D’圖所示。
如第2E圖所示，移除全部該承載板20，以外露出該第一導電柱22之端面22a與該第一絕緣層21之表面21a。
於本實施例中，該第一絕緣層21與該第二絕緣層23可視為絕緣部2a，且該第一導電柱22與該第二導電柱24可視為堆疊柱狀導電部2b(如第2E’圖所示)，以令該絕緣部2a與該導電部2b作為該覆晶封裝基板3之核心層結構2，其具有相對之第一表面20a與第二表面20b。
再者，利用堆疊方式製作該核心層結構2，不僅可製作總厚度夠厚者，且可維持小孔徑及細間距之設計。例如，以該核心層結構2所需之厚度L為1.2mm為例，使用兩層絕緣層之各層厚度t1,t2均為0.6mm的兩次疊加方式(如第2D圖所示)、或使用三層絕緣層之各層厚度均為0.4mm的三次疊加方式(如第5A至5D圖所示)，故各個絕緣層之厚度較薄，因而能製作出端面尺寸細小之導電柱，進而可有效增加單位面積內之電性連接點的數量、增加佈線密度及縮減線路間距。
又，該絕緣部2a之鑄模化合物或底層塗料之剛性佳而能抗板翹，因而該承載板20之移除，該核心層結構2不會發生板翹之情況，故可完全移除該承載板20。
如第2F圖所示，於該核心層結構2上形成線路部2c，其可為單層線路形式，如包含一形成於該第一表面20a上之第一線路層250，且該第一線路層250係電性連接該第一導電柱22，亦可包含一同時或分次形成於該核心層結構2之第二表面20b上的第二線路層260，且該第二線路層260係電性連接該第二導電柱24，其中，該第一線路層250係直接電性連接該第一導電柱22，且該第二線路層260係直接電性連接該第二導電柱24。應可理解地，如第2F’圖所示，該第一線路層250可藉由導電墊部220間接電性連接該第一導電柱22，且該第二線路層260亦可藉由導電墊部240間接電性連接該第二導電柱24。
於本實施例中，該線路部2c’亦可為增層形式，即依 需求設計佈設線路之層數。具體地，如第2F-1圖所示之覆晶封裝基板3’，該線路部2c’可包含一形成於該核心層結構2之第一表面20a上的第一線路結構35，其包括至少一第一介電層351及複數結合該第一介電層351之第一線路層350，其中，該第一線路層350可直接(不透過導電墊部220)電性連接該第一導電柱22或可透過該導電墊部220間接電性連接該第一導電柱22(如第2F-2圖所示)，且該第一線路結構35上可形成一絕緣保護層37a，以令該絕緣保護層37a外露出最外側第一線路層350，俾供作為結合焊錫凸塊(圖略)之電性接觸墊352。同理地，該線路部2c’亦可包含一同時或分次形成於該核心層結構2之第二表面20b上的第二線路結構36，其包括至少一第二介電層361及複數結合該第二介電層361之第二線路層360，其中，該第二線路層360可直接(不透過導電墊部240)電性連接該第二導電柱24(如第2F-1圖所示)或可透過該導電墊部240間接電性連接該第二導電柱24(如第2F-2圖所示)，且該第二線路結構36上亦可形成一絕緣保護層37b，以令該絕緣保護層37b外露出最外側第二線路層360，俾供作為結合焊錫凸塊38之電性接觸墊362。
再者，該第一與第二介電層351,361可為環氧樹脂(Epoxy)，如ABF、預浸材或環氧模壓樹脂(EMC)，且該絕緣保護層37a,37b可為防焊材，如感光型油墨、ABF或(非感光型介電材(如EMC)等。
又，該線路部2c,2c’透過該導電墊部220,240電性連 接該第一或第二導電柱22,24，可獲得額外的散熱效益。
另外，於後續製程中，如第2G或2G’圖所示之電子封裝件3”之結構中，可於該覆晶封裝基板3’之第二線路層260或該覆晶封裝基板3’之電性接觸墊362上以覆晶方式藉由複數導電凸塊31及/或該些焊錫凸塊38設置電子元件30，再以底膠32包覆該些導電凸塊31及/或該些焊錫凸塊38、或以封裝層(圖略)包覆該電子元件30。另一方面，於該覆晶封裝基板3之第一線路層250上或該覆晶封裝基板3’之電性接觸墊352上接置如焊球之導電元件39，俾供外接一電路板(圖略)。
所述之電子元件30係為主動元件、被動元件或其二者組合，其中，該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。
所述之封裝層可為壓合製程用之薄膜、模壓製程用之封裝膠體或印刷製程用之膠材等，且形成該封裝層之材質係為聚醯亞胺(PI)、乾膜(dry film)、環氧樹脂(epoxy)或封裝材，並無特別限制。
再者，當為了增加該覆晶封裝基板3,3’之剛性強度而增加該核心層結構2(或該絕緣部2a)之厚度L(如由0.8mm增至1.2mm或1.6mm)時，該導電部2b之端面(該第一導電柱22之寬度d1或該第二導電柱24之寬度d2)係可設計為0.04mm至0.06mm，其遠小於習知鑽孔製程之0.1mm或0.2mm以上的孔徑，故相較於習知技術，該導電部2b之端面可依需求朝微小化設計，因而能增加其上方線路層 (該第一線路層250,350或第二線路層260,360)之線路佈線密度，以及能增加單位面積內該電性接觸墊352,362之數量。
又，該絕緣部2a可採用高剛性的材料以抗板翹，使該核心層結構2之厚度L無需進一步加厚(如維持0.8mm，兩層絕緣層之各層厚度t1,t2均為0.4mm)，即可得到高剛性強度的覆晶封裝基板3,3’，且該第一導電柱22之寬度d1或該第二導電柱24之寬度d2仍可為0.04mm至0.06mm。
另外，於該核心層結構2之其它實施例中，該導電部2b之導電柱的堆疊層數、各段導電柱之端面尺寸大小(可相同或相異)、或該線路層之佈設方式等均可依需求設計。如第5A至5C圖所示之三層堆疊結構，該導電部5a,5b,5c係包含相互堆疊之第一導電柱22、第二導電柱24及第三導電柱50，且該三個導電柱之端面尺寸可相同或相異，如第5A圖所示呈現粗、中、細者，如第5B圖所示呈現粗、細、粗者，如第5C圖所示呈現細、粗、細者等態樣。再如第5D圖所示，該導電部5a上可不形成第二線路層260。如第5E圖所示，該第二線路層56之寬度a可小於該導電部2b之端面寬度(或該第二導電柱24之寬度d2)。
第3A至3G圖係為本發明之覆晶封裝基板3,3’之製法之第二實施例的剖視示意圖。本實施例與第一實施例之差異在於核心層結構之製程，其它製程大致相同，故以下不再贅述相同處。
如第3A圖所示，於一承載板20上形成一第一阻層91， 且藉由圖案化製程，於該第一阻層91上形成複數第一開口區910。
於本實施例中，該第一阻層91係為光阻，其利用影像轉移方式(曝光及顯像)形成圖案化開口區。
如第3B圖所示，於該第一阻層91之第一開口區910中電鍍或沉積形成第一導電柱22。
如第3C圖所示，於該第一阻層91上形成一第二阻層92，且藉由圖案化製程，於該第二阻層92上形成複數對應外露各該第一導電柱22之第二開口區920。
於本實施例中，該第二阻層92係為光阻，其利用影像轉移方式(曝光及顯像)形成圖案化開口區。
再者，該第二開口區920之寬度係可相同或相異於該第一開口區910之寬度。
如第3D圖所示，於該第二阻層92之第二開口區920中電鍍或沉積形成第二導電柱24，且該第二導電柱24係接觸堆疊於該第一導電柱22上。
如第3E圖所示，移除該第一與第二阻層91,92，以令該第一與第二導電柱22,24作為導電部2b。
如第3F圖所示，於該承載板20上形成一絕緣部2a’以包覆該導電部2b，以令該絕緣部2a’與該導電部2b作為核心層結構2’，其類似第2D圖所示之核心層結構2(兩者差異在於該絕緣部2a,2a’)。
如第3G或3G’圖所示，後續之製程係如接續第2D圖之製程，如第2E至2G圖所示之移除該承載板20、形成 該線路部2c,2c’(可依需求形成該導電墊部220,240)及封裝作業(如第3H或3H’圖所示)等製程。
第4A至4D圖係為本發明之覆晶封裝基板4,4’之製法之第三實施例的剖視示意圖。本實施例與第一實施例之差異在於核心層結構之製程，其它製程大致相同，故以下不再贅述相同處。
如第4A圖所示，提供一絕緣部4a，其具有相對之第一側40a與第二側40b，且於該絕緣部4a之第一側40a上形成複數第一通孔410，再於該絕緣部4a之第二側40a上相對應之處形成複數第二通孔430，使該相對應之第一通孔410與該第二通孔430相連通。
如第4B圖所示，於該絕緣部4a之第一側40a與第二側40b上及第一與第二通孔410,430中形成種子層80。接著，分別形成一阻層90於該絕緣部4a之第一側40a與第二側40b上，且該些阻層90分別形成有複數開口區900，以連通該第一通孔410與第二通孔430及外露該絕緣部4a之第一側40a與第二側40b上之部分種子層80。
如第4C圖所示，於該些開口區900、該第一通孔410與第二通孔430中形成金屬材46，且該第一通孔410中之金屬材46作為第一導電柱42，該第二通孔430中之金屬材46作為第二導電柱44，使該第一與第二導電柱42,44一體疊置成形以作為導電部4b，以令該絕緣部4a與該複數導電部4b作為核心層結構2”。
如第4D圖所示，移除該些阻層90及其下之種子層80， 使該些開口區900中之金屬材46作為線路部4c，以形成一覆晶封裝基板4，且該線路部4c係電性連接該導電部4b，其中，該核心層結構2”係具有分別對應該第一側40a與第二側40b之第一表面20a與第二表面20b。
於本實施例中，該導電部4b與該線路部4c係為同一製程一體成形者。
再者，該線路部4c係可為單層線路形式(如第4D或4D’圖所示)或增層形式(如第4E或4E’圖所示之線路部4c’)。
又，該線路部4c,4c’可直接電性連接該第一導電柱42或該第二導電柱44，如第4D或4E圖所示；或者，如第4D’或4E’圖所示，該線路部4c,4c’可藉由一體製作之導電墊部420,440間接電性連接該第一導電柱42或該第二導電柱44。
另外，如第4E或4E’圖所示，完成該覆晶封裝基板4,4’之製程後，接續之製程係如第2G或2G’圖所示之封裝作業以完成該電子封裝件4”之製作。
本發明復提供一種覆晶封裝基板3,3，,4,4，，係包括：複數導電部2b,4b、一絕緣部2a,2a’,4a以及一線路部2c,2c’,4c,4c’。
所述之導電部2b,4b係至少具有相互接觸疊置之第一與第二導電柱22,24，且該第一與第二導電柱22,24之寬度d1,d2係可相同或不相同，使該導電部2b之周面呈平直狀或具有凹凸狀S。
所述之絕緣部2a,2a’,4a係包覆該導電部2b,4b，以令該絕緣部2a,2a’,4a與該導電部2b,4b作為核心層結構2,2’,2”。
於一實施例中，形成該絕緣部2a,2a’,4a之材質係為介電材。例如，該介電材係為不包含玻纖之有機介電材(如防焊材)或不包含玻纖之無機介電材(如絕緣氧化物)。具體地，該有機介電材之種類更包含鑄模化合物、環氧模壓樹脂(EMC)或底層塗料。
所述之線路部2c,2c’,4c,4c’係設於該核心層結構2,2’,2”之第一表面20a及第二表面20b上並電性連接該導電部2b,4b，其可為單層線路形式(如該第一線路層250、第二線路層260、或如第4D及4D’圖所示之態樣)或增層形式(如該第一線路結構35、第二線路結構36、或如第4E及4E’圖所示之態樣)。
於一實施例中，該導電部2b,4b係直接(如第2F、2F-1、3G、4D及4E圖所示)或間接(如第2F’、2F-2、3G’、4D’及4E’圖所示)電性連接該線路部2c,2c’,4c,4c’。
依本發明製作之該核心層結構2,2’,2”，可以滿足提高單位面積內電性連接點的數量、更高密度電路佈線及細間距線路之需求，其具體優點如下：
第一、有效增加單位面積內之電性連接點的數量。具體地，茲因本發明中之核心層結構2,2’,2”之總厚度雖然增厚，但該絕緣部2a,2a’,4a之每一分層(如第一絕緣層21、第二絕緣層23或對應該導電柱之分段)的厚度依然可維持 薄型，所以每一分層的導電柱端面尺寸能維持細微化，因此本發明能使該核心層結構2,2’,2”之導電部2b,4b細間距化，進而有效增加單位面積內之電性連接點的數量。
第二、線路層之線路能細間距化及佈線高密度化。具體地，茲因本發明中之核心層結構2,2’,2”之總厚度雖然增厚，但該絕緣部2a,2a’,4a之每一分層(如第一絕緣層21、第二絕緣層23或對應該導電柱之分段)的厚度依然可維持薄型，所以每一分層的導電柱端面尺寸能維持細微化，因此本發明能使該核心層結構2,2’,2”之導電部2b,4b細間距化，據此能有效減少導電柱之端面佔用該絕緣部2a,2a’,4a表面之面積，因而能增加線路層的佈設面積，進而能降低線路層之線路佈線限制，且易於製作細間距線路及高密度佈線線路。
第三、層間的導電部2b,4b的製作成本低。具體地，茲因本發明中之核心層結構2,2”之總厚度雖然增厚，但該絕緣部2a,4a之每一分層(如第一絕緣層21、第二絕緣層23或對應該導電柱之分段)的厚度依然可維持薄型，所以每一分層之通孔(如第一通孔210,410與第二通孔230,430)的成型均能輕易、快速地完成，且通孔內不論是電鍍導電層或填入填充材，均能輕易的獲得良好品質與高良率，因而能有效降低製作成本。
第四、有效防止封裝製程的板翹問題。具體地，茲因本發明中之核心層結構2,2’,2”之總厚度增厚，故除了能獲得良好的剛性以因應高集積晶片的封裝需求而不會發生板 翹問題之外，還能獲得提高單位面積內之電性連接點的數量、線路細間距化及高密度佈線等優點特徵，因而能完全滿足高集積晶片的封裝需求、及後續穩定的效能表現需求。
綜上所述，本發明之覆晶封裝基板之製法及其結構中，係藉由特有的核心層結構之特點，促使該核心層結構即使總厚度變厚，仍能輕易依需求製作出所需之小端面尺寸導電部，故本發明之覆晶封裝基板不僅能達到避免其於半導體封裝製程時發生板翹之情況，且能進一步提供能有效增加單位面積內之電性連接點的數量、進行線路層線路細間距化、線路佈線高密度化、以及製作成本低廉等優點特徵，進而更能完全滿足高集積尺寸晶片(如AI晶片等)之高階晶片封裝及應用端之穩定效能之需求。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。

Claims (17)

  1. 一種覆晶封裝基板之製法，係包括：提供一承載板，且於該承載板上形成有一第一絕緣層；於該第一絕緣層中形成複數第一導電柱；於該第一絕緣層上形成至少一第二絕緣層，以令該第一與第二絕緣層作為絕緣部：於該第二絕緣層中形成複數第二導電柱，使該第一與第二導電柱相互接觸疊置以作為導電部，以令該絕緣部與該複數導電部作為核心層結構，且該核心層結構具有相對之第一表面與第二表面；移除該承載板；以及於該核心層結構之第一與第二表面上同時或分次形成線路部，且該線路部係電性連接該導電部。
  2. 一種覆晶封裝基板之製法，係包括：提供一承載板，且於該承載板上形成有相互接觸疊置之複數導電柱，以令該些導電柱作為導電部；形成一絕緣部於該承載板上以包覆該複數導電部，以令該絕緣部與該複數導電部作為核心層結構，且該核心層結構具有相對之第一表面與第二表面；移除該承載板；以及於該核心層結構之第一與第二表面上同時或分次形成線路部，且該線路部係電性連接該導電部。
  3. 如申請專利範圍第2項所述之覆晶封裝基板之製法， 其中，至少二搭疊之該導電柱之端面尺寸係相同或不相同。
  4. 如申請專利範圍第2項所述之覆晶封裝基板之製法，其中，該導電柱的製作方式係為電鍍或沉積製程。
  5. 一種覆晶封裝基板之製法，係包括：提供一絕緣部，其具有相對之第一側與第二側；於該絕緣部之第一側上形成複數第一通孔；於該絕緣部之第二側上形成對應該第一通孔的複數第二通孔，使相對應的該第一通孔與該第二通孔相連通；於該第一通孔中形成第一導電柱，且於該第二通孔中形成第二導電柱，使該第一與第二導電柱相互接觸疊置以作為導電部，以令該絕緣部與該複數導電部作為核心層結構，且該核心層結構具有相對之第一表面與第二表面；以及於該核心層結構之第一與第二表面上同時或分次形成線路部，且該線路部係電性連接該導電部。
  6. 如申請專利範圍第1或5項所述之覆晶封裝基板之製法，其中，該第一導電柱之端面尺寸與該第二導電柱之端面尺寸係相同或不相同。
  7. 如申請專利範圍第1或5項所述之覆晶封裝基板之製法，其中，該第一或第二導電柱的製作方式係為電鍍、沉積或填塞導電材製程。
  8. 如申請專利範圍第1、2或5項所述之其中一者之覆晶 封裝基板之製法，其中，形成該核心層結構之絕緣部的材質係為不包含玻纖之有機介電材或不包含玻纖之無機介電材。
  9. 如申請專利範圍第1、2或5項所述之其中一者之覆晶封裝基板之製法，其中，該線路部係為單層線路形式。
  10. 如申請專利範圍第1、2或5項所述之其中一者之覆晶封裝基板之製法，其中，該線路部係為增層形式。
  11. 如申請專利範圍第1、2或5項所述之其中一者之覆晶封裝基板之製法，其中，該導電部係直接或間接電性連接該線路部。
  12. 一種覆晶封裝基板，係包括：複數導電部，且每一導電部係由相互接觸疊置之複數導電柱構成；絕緣部，係包覆該複數導電部，以令該絕緣部與該些導電部作為核心層結構，且該核心層結構具有相對之第一表面與第二表面；以及線路部，係設於該核心層結構之第一表面及/或第二表面上並電性連接該導電部。
  13. 如申請專利範圍第12項所述之覆晶封裝基板，其中，至少二搭疊之該導電柱之寬度係相同或不相同。
  14. 如申請專利範圍第12項所述之覆晶封裝基板，其中，形成該絕緣部之材質係為不包含玻纖之有機介電材或不包含玻纖之無機介電材。
  15. 如申請專利範圍第12項所述之覆晶封裝基板，其中， 該線路部係為單層線路形式。
  16. 如申請專利範圍第12項所述之覆晶封裝基板，其中，該線路部係為增層形式。
  17. 如申請專利範圍第12項所述之覆晶封裝基板，其中，該導電部係直接或間接電性連接該線路部。
TW107115944A 2018-05-10 2018-05-10 覆晶封裝基板之製法及其結構 TWI713842B (zh)

Priority Applications (5)

Application Number Priority Date Filing Date Title
TW107115944A TWI713842B (zh) 2018-05-10 2018-05-10 覆晶封裝基板之製法及其結構
CN201810894212.7A CN110473788A (zh) 2018-05-10 2018-08-08 覆晶封装基板的制法及其结构
JP2018203464A JP2019197881A (ja) 2018-05-10 2018-10-30 フリップチップパッケージ基板の製造方法及びその構造
US16/404,856 US11476204B2 (en) 2018-05-10 2019-05-07 Flip-chip packaging substrate and method for fabricating the same
US17/891,184 US20220406734A1 (en) 2018-05-10 2022-08-19 Flip-chip packaging substrate and method for fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW107115944A TWI713842B (zh) 2018-05-10 2018-05-10 覆晶封裝基板之製法及其結構

Publications (2)

Publication Number Publication Date
TW201947678A true TW201947678A (zh) 2019-12-16
TWI713842B TWI713842B (zh) 2020-12-21

Family

ID=68464173

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107115944A TWI713842B (zh) 2018-05-10 2018-05-10 覆晶封裝基板之製法及其結構

Country Status (4)

Country Link
US (2) US11476204B2 (zh)
JP (1) JP2019197881A (zh)
CN (1) CN110473788A (zh)
TW (1) TWI713842B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI738325B (zh) * 2020-05-08 2021-09-01 大陸商上海兆芯集成電路有限公司 晶片封裝方法、晶片封裝體陣列及晶片封裝體
CN111741592B (zh) * 2020-06-17 2021-09-21 珠海越亚半导体股份有限公司 多层基板及其制作方法
KR20220070766A (ko) * 2020-11-23 2022-05-31 삼성전자주식회사 글래스 기판을 포함하는 이미지 센서 패키지
TWI759120B (zh) * 2021-03-04 2022-03-21 恆勁科技股份有限公司 中介基板及其製法
CN113130468A (zh) * 2021-04-15 2021-07-16 上海安略永信信息技术有限公司 一种倒装芯片半导体封装件及其制造方法
CN113823241B (zh) * 2021-09-30 2022-09-27 武汉华星光电技术有限公司 驱动芯片及显示面板
JP2024085489A (ja) * 2022-12-15 2024-06-27 Ｔｏｐｐａｎホールディングス株式会社 インターポーザ、半導体パッケージ及びそれらの製造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3838800B2 (ja) * 1998-12-15 2006-10-25 富士通株式会社 多層プリント配線板製造方法
JP2000323834A (ja) * 1999-05-11 2000-11-24 Shinko Electric Ind Co Ltd ビルドアップ基板形成用のコア基板の製造方法
US20040126547A1 (en) * 2002-12-31 2004-07-01 Coomer Boyd L. Methods for performing substrate imprinting using thermoset resin varnishes and products formed therefrom
WO2008053833A1 (fr) * 2006-11-03 2008-05-08 Ibiden Co., Ltd. Tableau de câblage imprimé multicouche
TWI373293B (en) * 2008-06-18 2012-09-21 Unimicron Technology Crop Printed circuit board and fabrication method thereof
JP4473935B1 (ja) * 2009-07-06 2010-06-02 新光電気工業株式会社 多層配線基板
US9420707B2 (en) * 2009-12-17 2016-08-16 Intel Corporation Substrate for integrated circuit devices including multi-layer glass core and methods of making the same
JP6081693B2 (ja) * 2011-09-12 2017-02-15 新光電気工業株式会社 配線基板及び配線基板の製造方法
US9161461B2 (en) * 2012-06-14 2015-10-13 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Multilayer electronic structure with stepped holes
CN105448883B (zh) * 2014-08-12 2017-11-24 碁鼎科技秦皇岛有限公司 芯片封装基板及、芯片封装结构及二者之制作方法
TWI556382B (zh) * 2014-08-26 2016-11-01 矽品精密工業股份有限公司 封裝基板及其製法
CN105590914B (zh) * 2014-10-24 2018-04-06 碁鼎科技秦皇岛有限公司 电子元件封装结构及制作方法
CN105720031A (zh) * 2014-12-03 2016-06-29 恒劲科技股份有限公司 中介基板及其制法
TWI634636B (zh) * 2016-09-09 2018-09-01 思鷺科技股份有限公司 半導體結構

Also Published As

Publication number Publication date
TWI713842B (zh) 2020-12-21
JP2019197881A (ja) 2019-11-14
CN110473788A (zh) 2019-11-19
US20190348375A1 (en) 2019-11-14
US20220406734A1 (en) 2022-12-22
US11476204B2 (en) 2022-10-18

Similar Documents

Publication Publication Date Title
TWI713842B (zh) 覆晶封裝基板之製法及其結構
TWI390692B (zh) 封裝基板與其製法暨基材
US8994193B2 (en) Semiconductor package including a metal plate, semiconductor chip, and wiring structure, semiconductor apparatus and method for manufacturing semiconductor package
TWI555166B (zh) 層疊式封裝件及其製法
JP4730426B2 (ja) 実装基板及び半導体モジュール
CN110858576B (zh) 覆晶封装基板及其制法
TWI746415B (zh) 覆晶封裝基板之核心結構及其製法
CN110459521B (zh) 覆晶封装基板和电子封装件
US20230199973A1 (en) Circuit board and semiconductor device including the same
US11948899B2 (en) Semiconductor substrate structure and manufacturing method thereof
US11658104B2 (en) Intermediate substrate and fabrication method thereof
TWI738069B (zh) 覆晶封裝基板及其製法
TWI723414B (zh) 電子封裝件及其製法
TWI739027B (zh) 覆晶封裝基板之核心結構及其製法
TWI788230B (zh) 電子封裝件及其製法
JP2017228692A (ja) 半導体パッケージ基板およびその製造方法
TWI392072B (zh) 封裝基板及其製作方法
TWI720735B (zh) 封裝結構及其製造方法
TWI808642B (zh) 印刷電路板及其製造方法
US12014934B2 (en) Semiconductor substrate structure and manufacturing method thereof
US20240203921A1 (en) Semiconductor substrate structure, semiconductor structure and manufacturing method thereof
US20220328391A1 (en) Semiconductor substrate and manufacturing method thereof and semiconductor package structure
US20240096838A1 (en) Component-embedded packaging structure
TW202327010A (zh) 半導體封裝載板及其製法
TW202414746A (zh) 封裝基板結構及其製造方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees