CN110473788A - 覆晶封装基板的制法及其结构 - Google Patents

覆晶封装基板的制法及其结构 Download PDF

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Publication number
CN110473788A
CN110473788A CN201810894212.7A CN201810894212A CN110473788A CN 110473788 A CN110473788 A CN 110473788A CN 201810894212 A CN201810894212 A CN 201810894212A CN 110473788 A CN110473788 A CN 110473788A
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China
Prior art keywords
crystal
conductive
substrate plate
core layer
packing substrate
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CN201810894212.7A
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English (en)
Inventor
周保宏
余俊贤
许诗滨
郭同尧
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Phoenix Pioneer Technology Co Ltd
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Phoenix Pioneer Technology Co Ltd
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Publication of CN110473788A publication Critical patent/CN110473788A/zh
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Abstract

一种覆晶封装基板的制法及其结构，该制法包括于将多个具有导电柱的绝缘层相互堆叠，使各该导电柱相互接触叠置，以令所述绝缘层与所述导电柱作为该覆晶封装基板的核心层结构，故通过本发明所制作的该核心层结构，能依需求而制作出小端面尺寸的导电柱，因此当该核心层结构的厚度增加时，不仅能增加该覆晶封装基板的刚性强度而避免发生板翘，且更保有能将导电柱的端面尺寸微小化设计的弹性，因而能于该核心层结构上制作高密度布设的电性连接点、细线路间距及高密度布线的线路层。

Description

覆晶封装基板的制法及其结构
技术领域
本发明有关一种覆晶封装基板技术，特别涉及一种半导体封装制程用的覆晶封装基板的制法及其结构。
背景技术
随着产业应用的发展，近年来逐渐朝向5G高频通信、AR、VR等发展，因此更需要研发高阶半导体的封装技术，以应用于诸如人工智能(AI)芯片、高阶芯片、多芯片等的半导体覆晶封装或多芯片封装，而在此封装需求之下，封装尺寸势必越来越大，叠层数也越来越高，导致线路设计更是朝高密度、细线路间距、高电性连接点数等方向设计，以满足上揭芯片的封装需求。
目前在高阶芯片封装及应用的缺点是现有的覆晶封装基板，因要配合高集成尺寸芯片(如AI芯片等)的封装，且为了满足更多的电性连接点数量、大量且复杂的线路需求、以及避免板翘现象的发生，所以势必要加厚其核心层尺寸，但也因而造成该核心层的通孔(Through hole)的断面尺寸随着核心层加厚而变大，致使其电性连接点的间距也随着变大，故导致在单位面积内的电性连接点的数量变少、线路密度变低、线路间距变大，而为了满足上揭需求，只好将覆晶封装基板的尺寸变得更大、更厚，因而造成封装作业变得更加困难。
因此，现有业界是使用大尺寸的覆晶封装基板，如45*45㎜2、70*70㎜2或80*80㎜2等大尺寸覆晶封装基板结构，以承载如人工智能(AI)芯片、高阶芯片或多芯片等高集成尺寸芯片来进行封装。如图1A所示，该电子装置1包括：一电路板18、一设于该电路板18上的大尺寸版面覆晶封装基板1a、以及一结合于该覆晶封装基板1a上的高集成尺寸半导体芯片19。具体地，如图1B所示，该覆晶封装基板1a包括一核心层10、设于该核心层10上、下两侧面上的增层(Build up)结构11、及设于该增层结构11上的防焊层12，其中，该核心层10具有导电通孔100以电性连接该增层结构11的线路层110，且该增层结构11还包含至少一包覆所述线路层110的介电层111，并令该防焊层12外露出该增层结构11最外侧的线路层110，从而供作为电性连接点112，以通过焊锡材料13结合该电路板18及该半导体芯片19。
昔知核心层10的制作中，为采用玻纤配合环氧树酯所组成的基材，如BT(Bismaleimide Triazine)或FR5等，再于其上进行导电通孔100制程，如机械钻孔、激光钻孔或双锥状盲孔(如图1C所示的导电通孔100’)等成孔步骤，再于孔中电镀导电层或再填入填充材(如图1B及图1C所示的全部导电通孔100，100’、或如图1D所示的导电材100a与绝缘材100b)。
然而，昔知应用于大尺寸的覆晶封装基板1a会产生明显缺点，例如：该核心层10为采用玻纤配合环氧树酯所组成的基材，因该覆晶封装基板1a于各层间材料的热膨胀系数(Coefficient of thermal expansion，简称CTE)不一致，因而于封装时易产生板翘，致使其与该半导体芯片19之间连接不良(如焊锡材料13’未接合或断裂)、或于焊接时，其与该电路板18之间会发生连接不良(如焊锡材料13”未接合或断裂)，更严重的是可能因为热应力关系，会造成该半导体芯片19本身的破裂、或该半导体芯片19电性失效。
因此，业界遂有将该核心层10的厚度h加厚，如厚度h从原本0.8毫米(㎜)(其搭配0.1㎜的孔径w)增加至1.2㎜(其需搭配0.2㎜以上的孔径w)，以增加该覆晶封装基板1a的刚性强度，以改善板翘问题，但却因而产生更多的缺点，如下：
第一、单位面积内的电性连接点的数量无法增加。具体地，加厚该核心层10的结果，造成在传统技术之下势必让所述导电通孔100，100’的端面尺寸变大(即该孔径w变大)，进而造成所述导电通孔100，100’的间距变大，故导致单位面积内电性连接点的数量变少。
第二、线路间距变大及线路密度变低。具体地，加厚该核心层10的结果，造成在传统技术的下势必让所述导电通孔100，100’的端面尺寸变大而占用布线面积，导致其上方线路层110的线路布线面积缩减，进而难以制作细线路间距或高密度线路的线路层110。
第三、该导电通孔100，100’内更难完成电镀及顺利填入填充材。具体地，加厚该核心层10的结果，将导致所述导电通孔100，100’变深，因而更难以在变深的导电通孔100，100’内完成电镀，甚至产生包孔现象，也难以将填充材100b顺利的填入变深的导电通孔100，100’内。
第四、该导电通孔100，100’的加工成本与难度随着该核心层10加厚而变高。具体地，兹因昔知核心层10是采用含玻纤的介电材来加厚该核心层10以改善板翘的问题，但是于该材质上以激光或机械钻孔进行较深的导电通孔100，100’加工时，不但难以制造出细小端面尺寸的导电通孔100，100’，更因而致使制作成本居高不下。
因此，如何克服昔知技术中的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述昔知技术的缺失，本发明提供一种覆晶封装基板的制法及其结构，能于该核心层结构上制作高密度布设的电性连接点、细线路间距及高密度布线的线路层。
本发明的覆晶封装基板的制法，包括：提供一承载板，且于该承载板上形成有一第一绝缘层；于该第一绝缘层中形成多个第一导电柱；于该第一绝缘层上形成至少一第二绝缘层，以令该第一与第二绝缘层作为绝缘部：于该第二绝缘层中形成多个第二导电柱，使该第一与第二导电柱相互接触叠置以作为导电部，以令该绝缘部与该多个导电部作为核心层结构，且该核心层结构具有相对的第一表面与第二表面；移除该承载板；以及于该核心层结构的第一与第二表面上同时或分次形成线路部，且该线路部电性连接该导电部。
本发明还提供一种覆晶封装基板的制法，包括：提供一承载板，且于该承载板上形成有相互接触叠置的多个导电柱，以令所述导电柱作为导电部；形成一绝缘部于该承载板上以包覆该导电部，以令该绝缘部与该导电部作为核心层结构，且该核心层结构具有相对的第一表面与第二表面；移除该承载板；以及于该核心层结构的第一与第二表面上同时或分次形成线路部，且该线路部电性连接该导电部。
本发明还提供一种覆晶封装基板的制法，包括：提供一绝缘部，其具有相对的第一侧与第二侧；于该绝缘部的第一侧上形成多个第一通孔；于该绝缘部的第二侧上形成对应该第一通孔的多个第二通孔，使相对应的该第一通孔与该第二通孔相连通；于该第一通孔中形成第一导电柱，且于该第二通孔中形成第二导电柱，使该第一与第二导电柱相互接触叠置以作为导电部，以令该绝缘部与该导电部作为核心层结构，且该核心层结构具有相对的第一表面与第二表面；以及于该核心层结构的第一与第二表面上同时或分次形成线路部，且该线路部电性连接该导电部。
前述的覆晶封装基板的制法中，该导电柱的制作方式为电镀、沉积或填塞导电材制程。
本发明又提供一种覆晶封装基板，包括：多个导电部，且每一导电部具有相互接触叠置的至少一第一导电柱与至少一第二导电柱；绝缘部，其包覆该多个导电部，以令该绝缘部与所述多个导电部作为核心层结构，且该核心层结构具有相对的第一表面与第二表面；以及线路部，其设于该核心层结构的第一表面及/或第二表面上并电性连接该导电部。
前述的覆晶封装基板的制法及其结构中，至少二搭叠的该导电柱的端面尺寸可相同或不相同。例如，第一导电柱的端面尺寸与第二导电柱的端面尺寸相同或不相同。
前述的覆晶封装基板的制法及其结构中，形成该绝缘部的材质可为不包含玻纤的有机介电材(如防焊材)或不包含玻纤的无机介电材(如绝缘氧化物)。具体地，该有机介电材的种类还包含铸模化合物、环氧模压树脂(EMC)或底层涂料。
前述的覆晶封装基板的制法及其结构中，该线路部为单层线路形式或增层形式。
前述的覆晶封装基板的制法及其结构中，该导电部直接或间接电性连接该线路部。
由上可知，本发明的覆晶封装基板的制法及其结构中，当为了增加该覆晶封装基板的刚性强度而增加该绝缘部的厚度时，该导电部的端面尺寸无需增大，甚至能缩小，故相较于昔知技术，本发明的覆晶封装基板不仅具有足够的刚性强度以避免封装件发生板翘，且该导电部的端面尺寸可依需求朝微小化设计，因而能增加单位面积内电性连接点的数量，以及制作出细线路间距的高密度线路层，进而能满足高集成芯片的封装需求者。
附图说明
图1A为昔知电子装置的剖视示意图；
图1B为昔知封装基板的剖视示意图；
图1C及图1D为各种昔知导电通孔的剖视示意图；
图2A至图2F为本发明的覆晶封装基板的制法的第一实施例的剖视示意图；图2B’为图2B的俯视图，图2C’为图2C的另一实施例，图2D’为图2D的俯视图，图2E’为图2E的局部立体图，图2F’为图2F的另一实施例；
图2F-1为图2F的再一实施例；
图2F-2为图2F’的另一实施例；
图2G为图2F-1的应用的剖视示意图；
图2G’为图2F-2的应用的剖视示意图；
图3A至图3G为本发明的覆晶封装基板的制法的第二实施例的剖视示意图；图3G’为图3G的另一实施例；
图3H为图3G的应用的剖视示意图；
图3H’为图3G’的应用的剖视示意图；
图4A至图4D为本发明的覆晶封装基板的制法的第三实施例的剖视示意图；图4D’为图4D的另一实施例；
图4E为图4D的应用的剖视示意图；
图4E’为图4D’的应用的剖视示意图；以及
图5A至图5E为本发明的覆晶封装基板的核心层结构的不同实施例的剖视示意图。
其中，附图标记说明如下：
1 电子装置
1a 覆晶封装基板
10 核心层
100，100’ 导电通孔
100a 导电材
100b 绝缘材
11 增层结构
110 线路层
111 介电层
112 接点
12 防焊层
13，13’，13” 焊锡材料
18 电路板
19 半导体芯片
2，2’，2” 核心层结构
2a，2a’，4a 绝缘部
2b，4b，5a，5b，5c 导电部
2c，2c’，4c，4c’ 线路部
20 承载板
20a 第一表面
20b 第二表面
21 第一绝缘层
21a 表面
210，410 第一通孔
22，42 第一导电柱
220，240，420，440 导电垫部
22a 端面
23 第二绝缘层
230，430 第二通孔
24，44 第二导电柱
250，350 第一线路层
260，360，56 第二线路层
3，3’，4，4’ 覆晶封装基板
3”，4” 电子封装件
30 电子元件
31 导电凸块
32 底胶
35 第一线路结构
351 第一介电层
352，362 电性接触垫
36 第二线路结构
361 第二介电层
37a，37b 绝缘保护层
38 焊锡凸块
39 导电元件
40a 第一侧
40b 第二侧
46 金属材
50 第三导电柱
80 种子层
90 阻层
900 开口区
91 第一阻层
910 第一开口区
92 第二阻层
920 第二开口区
S 凹凸状
H，h，L，t1，t2 厚度
a，d1，d2，t，t’，r，r’ 宽度
w 孔径。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，熟悉此技艺的人士可由本说明书所公开的内容轻易地了解本发明的其他优点及技术效果。
须知，本说明书附图所示出的结构、比例、大小等，均仅用以配合说明书所公开的内容，以供熟悉此技艺人士的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的技术效果及所能实现的目的下，均应仍落在本发明所公开的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”、“第三”及“一”等的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范围。
图2A至图2F为本发明的覆晶封装基板3，3’的制法的第一实施例的剖视示意图。
如图2A所示，先依封装需求决定核心层结构2(如图2E所示)的厚度尺寸，并据此决定该核心层结构2的分层层数(本实施例分为二层)；之后，再据以于一承载板20上形成一第一绝缘层21，且通过图案化制程，于该第一绝缘层21上形成多个第一通孔210。
于本实施例中，该第一绝缘层21以铸模方式、涂布方式或压合方式形成于该承载板20上，且形成该第一绝缘层21的材质为不包含玻纤的有机介电材(如防焊材)或不包含玻纤的无机介电材(如绝缘氧化物)。具体地，该有机介电材的种类还包含铸模化合物(Molding Compound)、环氧模压树脂(Epoxy Molding Compound，简称EMC)或底层涂料(Primer)。
此外，兹因该第一绝缘层21的厚度薄，因此通过激光方式即可轻易且快速地形成所需细小端面尺寸的第一通孔210。
如图2B所示，于该第一绝缘层21的第一通孔210中形成第一导电柱22。
于本实施例中，该第一导电柱22的周面未延伸有线路，如图2B’所示。
此外，该第一导电柱22的制作方式，除了电镀或沉积制程之外，也可采用直接在该第一通孔210中填塞导电材(如锡膏、导电胶等)的方式制作。
如图2C所示，于该第一绝缘层21上形成一第二绝缘层23，且通过图案化制程，于该第二绝缘层23上形成多个对应外露各该第一导电柱22的第二通孔230。
于本实施例中，该第二绝缘层23以铸模方式、涂布方式或压合方式形成于该第一绝缘层21上，且形成该第二绝缘层23的材质为不包含玻纤的有机介电材(如防焊材)或不包含玻纤的无机介电材(如绝缘氧化物)。具体地，该有机介电材的种类还包含铸模化合物、环氧模压树脂(EMC)或底层涂料。
此外，兹因该第二绝缘层23的厚度薄，所以通过激光方式即可轻易且快速地形成所需细小端面尺寸的第二通孔230。
又，该第二通孔230的宽度t可相同或相异于该第一通孔210的宽度r(本实施例为t<r)；或者，如图2C’所示的实施例，该第二通孔230的宽度t’也可大于该第一通孔210的宽度r’(本实施例为t’>r’)。
如图2D所示，继续图2C的制程，于该第二绝缘层23的第二通孔230中以电镀、沉积或填塞导电材等制程形成第二导电柱24，且该第二导电柱24接触堆叠于该第一导电柱22上，其中，该第一导电柱22的宽度d1(约为0.06㎜)与该第二导电柱24的宽度d2(约为0.04㎜)不相同，使该第一导电柱22与该第二导电柱24的端面交界处呈凹凸状S，如阶梯。
于本实施例中，该第二导电柱24的周面未延伸有线路，如图2D’所示。
如图2E所示，移除全部该承载板20，以外露出该第一导电柱22的端面22a与该第一绝缘层21的表面21a。
于本实施例中，该第一绝缘层21与该第二绝缘层23可视为绝缘部2a，且该第一导电柱22与该第二导电柱24可视为堆叠柱状导电部2b(如图2E’所示)，以令该绝缘部2a与该导电部2b作为该覆晶封装基板3的核心层结构2，其具有相对的第一表面20a与第二表面20b。
此外，利用堆叠方式制作该核心层结构2，不仅可制作总厚度够厚者，且可维持小孔径及细间距的设计。例如，以该核心层结构2所需的厚度L为1.2㎜为例，使用两层绝缘层的各层厚度t1，t2均为0.6㎜的两次叠加方式(如图2D所示)、或使用三层绝缘层的各层厚度均为0.4㎜的三次叠加方式(如图5A至图5D所示)，故各个绝缘层的厚度较薄，因而能制作出端面尺寸细小的导电柱，进而可有效增加单位面积内的电性连接点的数量、增加布线密度及缩减线路间距。
又，该绝缘部2a的铸模化合物或底层涂料的刚性佳而能抗板翘，因而该承载板20的移除，该核心层结构2不会发生板翘的情况，故可完全移除该承载板20。
如图2F所示，于该核心层结构2上形成线路部2c，其可为单层线路形式，如包含一形成于该第一表面20a上的第一线路层250，且该第一线路层250电性连接该第一导电柱22，也可包含一同时或分次形成于该核心层结构2的第二表面20b上的第二线路层260，且该第二线路层260电性连接该第二导电柱24，其中，该第一线路层250直接电性连接该第一导电柱22，且该第二线路层260直接电性连接该第二导电柱24。应可理解地，如图2F’所示，该第一线路层250可通过导电垫部220间接电性连接该第一导电柱22，且该第二线路层260也可通过导电垫部240间接电性连接该第二导电柱24。
于本实施例中，该线路部2c’也可为增层形式，即依需求设计布设线路的层数。具体地，如图2F-1所示的覆晶封装基板3’，该线路部2c’可包含一形成于该核心层结构2的第一表面20a上的第一线路结构35，其包括至少一第一介电层351及多个结合该第一介电层351的第一线路层350，其中，该第一线路层350可直接(不通过导电垫部220)电性连接该第一导电柱22或可通过该导电垫部220间接电性连接该第一导电柱22(如图2F-2所示)，且该第一线路结构35上可形成一绝缘保护层37a，以令该绝缘保护层37a外露出最外侧第一线路层350，从而供作为结合焊锡凸块(图略)的电性接触垫352。同理地，该线路部2c’也可包含一同时或分次形成于该核心层结构2的第二表面20b上的第二线路结构36，其包括至少一第二介电层361及多个结合该第二介电层361的第二线路层360，其中，该第二线路层360可直接(不通过导电垫部240)电性连接该第二导电柱24(如图2F-1所示)或可通过该导电垫部240间接电性连接该第二导电柱24(如图2F-2所示)，且该第二线路结构36上也可形成一绝缘保护层37b，以令该绝缘保护层37b外露出最外侧第二线路层360，从而供作为结合焊锡凸块38的电性接触垫362。
此外，该第一与第二介电层351，361可为环氧树脂(Epoxy)，如ABF、预浸材或环氧模压树脂(EMC)，且该绝缘保护层37a，37b可为防焊材，如感光型油墨、ABF或(非感光型介电材(如EMC))等。
又，该线路部2c，2c’通过该导电垫部220，240电性连接该第一或第二导电柱22，24，可获得额外的散热效益。
另外，于后续制程中，如图2G或图2G’所示的电子封装件3”的结构中，可于该覆晶封装基板3’的第二线路层260或该覆晶封装基板3’的电性接触垫362上以覆晶方式通过多个导电凸块31及/或所述焊锡凸块38设置电子元件30，再以底胶32包覆所述导电凸块31及/或所述焊锡凸块38、或以封装层(图略)包覆该电子元件30。另一方面，于该覆晶封装基板3的第一线路层250上或该覆晶封装基板3’的电性接触垫352上接置如焊球的导电元件39，从而供外接一电路板(图略)。
所述的电子元件30为主动元件、被动元件或其二者组合，其中，该主动元件例如为半导体芯片，而该被动元件例如为电阻、电容及电感。
所述的封装层可为压合制程用的薄膜、模压制程用的封装胶体或印刷制程用的胶材等，且形成该封装层的材质为聚酰亚胺(PI)、干膜(dry film)、环氧树脂(epoxy)或封装材，并无特别限制。
此外，当为了增加该覆晶封装基板3，3’的刚性强度而增加该核心层结构2(或该绝缘部2a)的厚度L(如由0.8㎜增至1.2㎜或1.6㎜)时，该导电部2b的端面(该第一导电柱22的宽度d1或该第二导电柱24的宽度d2)可设计为0.04㎜至0.06㎜，其远小于昔知钻孔制程的0.1㎜或0.2㎜以上的孔径，故相较于昔知技术，该导电部2b的端面可依需求朝微小化设计，因而能增加其上方线路层(该第一线路层250，350或第二线路层260，360)的线路布线密度，以及能增加单位面积内该电性接触垫352，362的数量。
又，该绝缘部2a可采用高刚性的材料以抗板翘，使该核心层结构2的厚度L无需进一步加厚(如维持0.8㎜，两层绝缘层的各层厚度t1，t2均为0.4㎜)，即可得到高刚性强度的覆晶封装基板3，3’，且该第一导电柱22的宽度d1或该第二导电柱24的宽度d2仍可为0.04㎜至0.06㎜。
另外，于该核心层结构2的其它实施例中，该导电部2b的导电柱的堆叠层数、各段导电柱的端面尺寸大小(可相同或相异)、或该线路层的布设方式等均可依需求设计。如图5A至图5C所示的三层堆叠结构，该导电部5a，5b，5c包含相互堆叠的第一导电柱22、第二导电柱24及第三导电柱50，且该三个导电柱的端面尺寸可相同或相异，如图5A所示呈现粗、中、细者，如图5B所示呈现粗、细、粗者，如图5C所示呈现细、粗、细者等实施例。再如图5D所示，该导电部5a上可不形成第二线路层260。如图5E所示，该第二线路层56的宽度a可小于该导电部2b的端面宽度(如该第二导电柱24的宽度d2)。
图3A至图3G为本发明的覆晶封装基板3，3’的制法的第二实施例的剖视示意图。本实施例与第一实施例的差异在于核心层结构的制程，其它制程大致相同，故以下不再赘述相同处。
如图3A所示，于一承载板20上形成一第一阻层91，且通过图案化制程，于该第一阻层91上形成多个第一开口区910。
于本实施例中，该第一阻层91为光刻胶，其利用影像转移方式(曝光及显像)形成图案化开口区。
如图3B所示，于该第一阻层91的第一开口区910中电镀或沉积形成第一导电柱22。
如图3C所示，于该第一阻层91上形成一第二阻层92，且通过图案化制程，于该第二阻层92上形成多个对应外露各该第一导电柱22的第二开口区920。
于本实施例中，该第二阻层92为光刻胶，其利用影像转移方式(曝光及显像)形成图案化开口区。
此外，该第二开口区920的宽度可相同或相异于该第一开口区910的宽度。
如图3D所示，于该第二阻层92的第二开口区920中电镀或沉积形成第二导电柱24，且该第二导电柱24接触堆叠于该第一导电柱22上。
如图3E所示，移除该第一与第二阻层91，92，以令该第一与第二导电柱22，24作为导电部2b。
如图3F所示，于该承载板20上形成一绝缘部2a’以包覆该导电部2b，以令该绝缘部2a’与该导电部2b作为核心层结构2’，其类似图2D所示的核心层结构2(两者差异在于该绝缘部2a，2a’)。
如图3G或图3G’所示，后续的制程如继续图2D的制程，如图2E至图2G所示的移除该承载板20、形成该线路部2c，2c’(可依需求形成该导电垫部220，240)及封装作业(如图3H或图3H’所示)等制程。
图4A至图4D为本发明的覆晶封装基板4，4’的制法的第三实施例的剖视示意图。本实施例与第一实施例的差异在于核心层结构的制程，其它制程大致相同，故以下不再赘述相同处。
如图4A所示，提供一绝缘部4a，其具有相对的第一侧40a与第二侧40b，且于该绝缘部4a的第一侧40a上形成多个第一通孔410，再于该绝缘部4a的第二侧40a上相对应的处形成多个第二通孔430，使该相对应的第一通孔410与该第二通孔430相连通。
如图4B所示，于该绝缘部4a的第一侧40a与第二侧40b上及第一与第二通孔410，430中形成种子层80。接着，分别形成一阻层90于该绝缘部4a的第一侧40a与第二侧40b上，且所述阻层90分别形成有多个开口区900，以连通该第一通孔410与第二通孔430及外露该绝缘部4a的第一侧40a与第二侧40b上的部分种子层80。
如图4C所示，于所述开口区900、该第一通孔410与第二通孔430中形成金属材46，且该第一通孔410中的金属材46作为第一导电柱42，该第二通孔430中的金属材46作为第二导电柱44，使该第一与第二导电柱42，44一体叠置成形以作为导电部4b，以令该绝缘部4a与该多个导电部4b作为核心层结构2”。
如图4D所示，移除所述阻层90及其下的种子层80，使所述开口区900中的金属材46作为线路部4c，以形成一覆晶封装基板4，且该线路部4c电性连接该导电部4b，其中，该核心层结构2”具有分别对应该第一侧40a与第二侧40b的第一表面20a与第二表面20b。
于本实施例中，该导电部4b与该线路部4c为同一制程一体成形者。
此外，该线路部4c可为单层线路形式(如图4D或图4D’所示)或增层形式(如图4E或图4E’所示的线路部4c’)。
又，该线路部4c，4c’可直接电性连接该第一导电柱42或该第二导电柱44，如图4D或图4E所示；或者，如图4D’或图4E’所示，该线路部4c，4c’可通过一体制作的导电垫部420，440间接电性连接该第一导电柱42或该第二导电柱44。
另外，如图4E或图4E’所示，完成该覆晶封装基板4，4’的制程后，继续的制程如图2G或图2G’所示的封装作业以完成该电子封装件4”的制作。
本发明还提供一种覆晶封装基板3，3’，4，4’，包括：多个导电部2b，4b、一绝缘部2a，2a’，4a以及一线路部2c，2c’，4c，4c’。
所述的导电部2b，4b至少具有相互接触叠置的第一与第二导电柱22，24，且该第一与第二导电柱22，24的宽度d1，d2可相同或不相同，使该导电部2b的周面呈平直状或具有凹凸状S。
所述的绝缘部2a，2a’，4a包覆该导电部2b，4b，以令该绝缘部2a，2a’，4a与该导电部2b，4b作为核心层结构2，2’，2”。
于一实施例中，形成该绝缘部2a，2a’，4a的材质为介电材。例如，该介电材为不包含玻纤的有机介电材(如防焊材)或不包含玻纤的无机介电材(如绝缘氧化物)。具体地，该有机介电材的种类还包含铸模化合物、环氧模压树脂(EMC)或底层涂料。
所述的线路部2c，2c’，4c，4c’设于该核心层结构2，2’，2”的第一表面20a及第二表面20b上并电性连接该导电部2b，4b，其可为单层线路形式(如该第一线路层250、第二线路层260、或如图4D及图4D’所示的实施例)或增层形式(如该第一线路结构35、第二线路结构36、或如图4E及图4E’所示的实施例)。
于一实施例中，该导电部2b，4b直接(如图2F、图2F-1、图3G、图4D及图4E所示)或间接(如图2F’、图2F-2、图3G’、图4D’及图4E’所示)电性连接该线路部2c，2c’，4c，4c’。
依本发明制作的该核心层结构2，2’，2”，可以满足提高单位面积内电性连接点的数量、更高密度电路布线及细间距线路的需求，其具体优点如下：
第一、有效增加单位面积内的电性连接点的数量。具体地，兹因本发明中的核心层结构2，2’，2”的总厚度虽然增厚，但该绝缘部2a，2a’，4a的每一分层(如第一绝缘层21、第二绝缘层23或对应该导电柱的分段)的厚度依然可维持超薄，所以每一分层的导电柱端面尺寸能维持细微化，因此本发明能使该核心层结构2，2’，2”的导电部2b，4b细间距化，进而有效增加单位面积内的电性连接点的数量。
第二、线路层的线路能细间距化及布线高密度化。具体地，兹因本发明中的核心层结构2，2’，2”的总厚度虽然增厚，但该绝缘部2a，2a’，4a的每一分层(如第一绝缘层21、第二绝缘层23或对应该导电柱的分段)的厚度依然可维持超薄，所以每一分层的导电柱端面尺寸能维持细微化，因此本发明能使该核心层结构2，2’，2”的导电部2b，4b细间距化，据此能有效减少导电柱的端面占用该绝缘部2a，2a’，4a表面的面积，因而能增加线路层的布设面积，进而能降低线路层的线路布线限制，且易于制作细间距线路及高密度布线线路。
第三、层间的导电部2b，4b的制作成本低。具体地，兹因本发明中的核心层结构2，2”的总厚度虽然增厚，但该绝缘部2a，4a的每一分层(如第一绝缘层21、第二绝缘层23或对应该导电柱的分段)的厚度依然可维持超薄，所以每一分层的通孔(如第一通孔210，410与第二通孔230，430)的成型均能轻易、快速地完成，且通孔内不论是电镀导电层或填入填充材，均能轻易的获得良好品质与高良率，因而能有效降低制作成本。
第四、有效防止封装制程的板翘问题。具体地，兹因本发明中的核心层结构2，2’，2”的总厚度增厚，故除了能获得良好的刚性以因应高集成芯片的封装需求而不会发生板翘问题之外，还能获得提高单位面积内的电性连接点的数量、线路细间距化及高密度布线等优点特征，因而能完全满足高集成芯片的封装需求、及后续稳定的效能表现需求。
综上所述，本发明的覆晶封装基板的制法及其结构中，通过特有的核心层结构的特点，促使该核心层结构即使总厚度变厚，仍能轻易依需求制作出所需的小端面尺寸导电部，故本发明的覆晶封装基板不仅能达到避免其于半导体封装制程时发生板翘的情况，且能进一步提供能有效增加单位面积内的电性连接点的数量、进行线路层线路细间距化、线路布线高密度化、以及制作成本低廉等优点特征，进而更能完全满足高集成尺寸芯片(如AI芯片等)的高阶芯片封装及应用端的稳定效能的需求。
上述实施例仅用以例示性说明本发明的原理及其技术效果，而非用于限制本发明。任何熟习此项技艺的人士均可在不违背本发明的构思及范围下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (17)

1.一种覆晶封装基板的制法，其特征在于，该制法包括：
提供一承载板，且于该承载板上形成有一第一绝缘层；
于该第一绝缘层中形成多个第一导电柱；
于该第一绝缘层上形成至少一第二绝缘层，以令该第一与第二绝缘层作为绝缘部：
于该第二绝缘层中形成多个第二导电柱，使该第一与第二导电柱相互接触叠置以作为导电部，以令该绝缘部与该多个导电部作为核心层结构，且该核心层结构具有相对的第一表面与第二表面；
移除该承载板；以及
于该核心层结构的第一与第二表面上同时或分次形成线路部，且该线路部电性连接该导电部。
2.一种覆晶封装基板的制法，其特征在于，该制法包括：
提供一承载板，且于该承载板上形成有相互接触叠置的多个导电柱，以令所述导电柱作为导电部；
形成一绝缘部于该承载板上以包覆该多个导电部，以令该绝缘部与该多个导电部作为核心层结构，且该核心层结构具有相对的第一表面与第二表面；
移除该承载板；以及
于该核心层结构的第一与第二表面上同时或分次形成线路部，且该线路部电性连接该导电部。
3.根据权利要求2所述的覆晶封装基板的制法，其特征在于，至少二搭叠的该导电柱的端面尺寸为相同或不相同。
4.根据权利要求2所述的覆晶封装基板的制法，其特征在于，该导电柱的制作方式为电镀或沉积制程。
5.一种覆晶封装基板的制法，其特征在于，该制法包括：
提供一绝缘部，其具有相对的第一侧与第二侧；
于该绝缘部的第一侧上形成多个第一通孔；
于该绝缘部的第二侧上形成对应该第一通孔的多个第二通孔，使相对应的该第一通孔与该第二通孔相连通；
于该第一通孔中形成第一导电柱，且于该第二通孔中形成第二导电柱，使该第一与第二导电柱相互接触叠置以作为导电部，以令该绝缘部与该多个导电部作为核心层结构，且该核心层结构具有相对的第一表面与第二表面；以及
于该核心层结构的第一与第二表面上同时或分次形成线路部，且该线路部电性连接该导电部。
6.根据权利要求1或5所述的覆晶封装基板的制法，其特征在于，该第一导电柱的端面尺寸与该第二导电柱的端面尺寸为相同或不相同。
7.根据权利要求1或5所述的覆晶封装基板的制法，其特征在于，该第一或第二导电柱的制作方式为电镀、沉积或填塞导电材制程。
8.根据权利要求1、2或5所述的其中一者的覆晶封装基板的制法，其特征在于，形成该核心层结构的绝缘部的材质为不包含玻纤的有机介电材或不包含玻纤的无机介电材。
9.根据权利要求1、2或5所述的其中一者的覆晶封装基板的制法，其特征在于，该线路部为单层线路形式。
10.根据权利要求1、2或5所述的其中一者的覆晶封装基板的制法，其特征在于，该线路部为增层形式。
11.根据权利要求1、2或5所述的其中一者的覆晶封装基板的制法，其特征在于，该导电部直接或间接电性连接该线路部。
12.一种覆晶封装基板，其特征在于，该覆晶封装基板包括：
多个导电部，且每一导电部由相互接触叠置的多个导电柱构成；
绝缘部，其包覆该多个导电部，以令该绝缘部与所述导电部作为核心层结构，且该核心层结构具有相对的第一表面与第二表面；以及
线路部，其设于该核心层结构的第一表面及/或第二表面上并电性连接该导电部。
13.根据权利要求12所述的覆晶封装基板，其特征在于，至少二搭叠的该导电柱的宽度为相同或不相同。
14.根据权利要求12所述的覆晶封装基板，其特征在于，形成该绝缘部的材质为不包含玻纤的有机介电材或不包含玻纤的无机介电材。
15.根据权利要求12所述的覆晶封装基板，其特征在于，该线路部为单层线路形式。
16.根据权利要求12所述的覆晶封装基板，其特征在于，该线路部为增层形式。
17.根据权利要求12所述的覆晶封装基板，其特征在于，该导电部直接或间接电性连接该线路部。
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