TW201937679A - 暫態電壓抑制器裝置、暫態電壓抑制器裝置組合以及形成方法 - Google Patents

暫態電壓抑制器裝置、暫態電壓抑制器裝置組合以及形成方法 Download PDF

Info

Publication number
TW201937679A
TW201937679A TW107140878A TW107140878A TW201937679A TW 201937679 A TW201937679 A TW 201937679A TW 107140878 A TW107140878 A TW 107140878A TW 107140878 A TW107140878 A TW 107140878A TW 201937679 A TW201937679 A TW 201937679A
Authority
TW
Taiwan
Prior art keywords
diode
substrate
tvs device
item
layer
Prior art date
Application number
TW107140878A
Other languages
English (en)
Other versions
TWI788462B (zh
Inventor
詹姆斯 艾倫 彼得
Original Assignee
美商力特福斯股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商力特福斯股份有限公司 filed Critical 美商力特福斯股份有限公司
Publication of TW201937679A publication Critical patent/TW201937679A/zh
Application granted granted Critical
Publication of TWI788462B publication Critical patent/TWI788462B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0814Diodes only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02293Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49548Cross section geometry
    • H01L23/49551Cross section geometry characterised by bent parts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49562Geometry of the lead-frame for devices being provided for in H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609Diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49548Cross section geometry
    • H01L23/49551Cross section geometry characterised by bent parts
    • H01L23/49555Cross section geometry characterised by bent parts the bent parts being the outer leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642Isolation within the component, i.e. internal isolation
    • H01L29/0649Dielectric regions, e.g. SiO2 regions, air gaps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609Diodes
    • H01L29/66098Breakdown diodes
    • H01L29/66113Avalanche diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609Diodes
    • H01L29/66136PN junction diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/8613Mesa PN junction diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Emergency Protection Circuit Devices (AREA)

Abstract

一種暫態電壓抑制(TVS)裝置,可包括:形成於一基板中之一基板基底,該基板基底包含一第一導電類型之一半導體;以及一磊晶層,該磊晶層安置於該基板基底上、在該基板之一第一側上,且包含一第二導電類型之一半導體。該磊晶層可包括:一第一部分,該第一部分具有一第一層厚度;以及一第二部分,該第二部分具有小於該第一層厚度之一第二層厚度,其中該第一部分及該第二部分安置於該基板之一第一側上,且其中該第一部分與該第二部分電隔離。

Description

非對稱瞬態電壓抑制裝置及其形成方法
各實施例係關於電路保護裝置的領域,該等電路保護裝置包括熔斷器裝置。
例如暫態電壓抑制器(TVS)裝置的半導體裝置可以製造成單向裝置或雙向裝置。在雙向裝置的情況下,第一裝置可以製造在半導體晶粒(晶片)之第一側上,而第二裝置可以製造在該半導體晶粒之第二側上。雙向裝置可包括:對稱裝置,其中第一裝置及第二裝置相同;以及不對稱裝置,其中第一裝置及第二裝置在多個性質方面不同。
儘管此類雙向裝置在設計半導體晶粒之不同側上的不同裝置之電性質方面提供一定靈活性,但此類裝置之封裝可能相對較複雜。
關於此等及其他考量,提供本發明。
例示性實施例係關於經改良之TVS裝置及用於形成TVS裝置之技術。
在一個實施例中,一種暫態電壓抑制(TVS)裝置可包括:形成於一基板中之一基板基底,該基板基底包含一第一導電類型之一半導體;以及一磊晶層,該磊晶層安置於該基板基底上、在該基板之一第一側上,且包含一第二導電類型之一半導體。該磊晶層可包括:一第一部分,該第一部分具有一第一層厚度;以及一第二部分,該第二部分具有小於該第一層厚度之一第二層厚度,其中該第一部分及該第二部分安置於該基板之一第一側上,且其中該第一部分與該第二部分電隔離。
在另一實施例中,一種暫態電壓抑制(TVS)裝置組合可包括:一TVS裝置,其中該TVS裝置包括形成於一基板中之一基板基底,該基板基底包含一第一導電類型之一半導體。該TVS裝置可包括一磊晶層,該磊晶層安置於該基板基底上、在該磊晶層之一第一側上、包含一第二導電類型之一半導體。該磊晶層可進一步包括:一第一部分,該第一部分具有一第一層厚度;以及一第二部分,該第二部分具有小於該第一層厚度之一第二層厚度,其中該第二部分包含一溝槽形狀,其中由該第一部分之一第一上表面界定的一平面在該第二部分之一第二上表面上方。該TVS裝置組合亦可進一步包括一引線框架,該引線框架耦合至該TVS裝置,該引線框架包含:一第一部件,該第一部件連接至該TVS裝置之該第一部分;以及一第二部件,該第二部件耦合至該TVS裝置之該第二部分。
在另一實施例中,一種方法可包括:提供一基板,該基板具有一第一導電類型之一基底層;在該基底層上形成一第二導電類型之一磊晶層,其中該磊晶層安置於該基板之一第一側上;在該磊晶層內形成一第一磊晶部分及一第二磊晶部分,其中該第一磊晶部分與該第二磊晶部分電隔離;在該第二磊晶部分內形成一凹部,其中該第一二極體及該第二二極體形成於該磊晶層內、在該基板之該第一側上。
現在將參考附圖在下文更全面地描述本發明實施例,附圖中展示了例示性實施例。該等實施例不應解釋為限於本文中所闡述的實施例。更確切地說,提供此等實施例,使得本發明將透徹且完整,且將其範疇全部傳遞給熟習此項技術者。在圖式中,相似數字始終指示相似元件。
在以下描述及/或技術方案中,術語「在……上」、「上覆於」、「安置於……上」以及「在……上方」可以在以下描述及申請專利範圍中使用。「在……上」、「上覆於」、「安置於……上」以及「在……上方」可以用於指示兩個或更多個元件彼此直接實體接觸。此外,術語「在……上」、「上覆於」、「安置於……上」以及「在……上方」可以意味兩個或更多個元件彼此不直接接觸。舉例而言,「在……上方」可意味一個元件在另一元件之上而彼此不接觸,且在該兩個元件之間可具有另一元件或多個元件。
在各種實施例中,提供新穎裝置結構及技術以用於形成雙向TVS裝置。
圖1圖示根據本發明之實施例的TVS裝置100。TVS裝置100可包括形成於基板101中之基板基底102。基板基底102可以由一第一導電類型之一半導體形成,第一導電類型之半導體諸如P型半導體。TVS裝置100可進一步包括磊晶層104,如所示,該磊晶層在基板101之第一側(圖1中的頂面)上安置於基板基底102上。磊晶層104可由一第二導電類型之一半導體形成。舉例而言,當基板基底102係P型矽時,磊晶層可為N型矽。舉例而言,當基板基底102係N型矽時,磊晶層可為P型矽。因而,P/N接面可在基板基底102與磊晶層104之間的界面處形成。磊晶層104可進一步包含第一部分106及第二部分108。第一部分106可具有一第一層厚度,而第二部分108可具有小於該第一層厚度之一第二層厚度。如所示,第一部分106及第二部分108安置於基板101之第一側上。借助隔離結構110,第一部分106與第二部分108電隔離。如所示,隔離結構110自基板101之第一側的表面延伸至基板基底102中。隔離結構110可用已知方式、例如使用溝槽絕緣體來形成。
因而,第一部分106連同基板基底102形成第一二極體118。第二部分108連同基板基底102形成第二二極體120。根據本發明之各種實施例,該第一二極體與該第二二極體在擊穿電壓、功率容量或擊穿電壓及功率容量上不同。舉例而言,由於磊晶層104之第二部分108與第一部分106相比具有相對較小的厚度,因此第二部分108之擊穿電壓與第一部分106之擊穿電壓相比可較小。舉例而言,第一部分106之第一層厚度在一些實施例中可在20 μm與80 μm之間,而針對第一部分106之給定第一層厚度,第二部分108之第二層厚度可小於該給定第一層厚度。
如圖1中進一步所示,形成於基板101內之第一二極體118及第二二極體120按陽極對陽極組態電氣串聯布置。第一二極體118及第二二極體120之相應陰極可經由分別形成於基板101之第一側上的觸點114及觸點116電接觸。因而,TVS裝置100可形成不對稱的單面雙向裝置。
第一二極體118與第二二極體120之間的電壓不對稱性的程度可以藉由調整第一部分106之第一層厚度相比於第二部分108之第二層厚度的相對厚度來布置。舉例而言,在各種實施例中,磊晶層104形成為基板基底102上之毯覆層(blanket layer),使得摻雜劑含量在磊晶層104上均勻。儘管第一部分106可保持不被更改,但在最初形成具有均勻厚度的磊晶層104之後,可以蝕刻第二部分108以減小第二部分108之層厚度。舉例而言,可以藉由在使第二部分108經受已知蝕刻劑的同時遮蔽第一部分106來選擇性地蝕刻第二部分108,從而形成凹部或溝槽形狀,如溝槽112所示。在圖1之實例中,由第一部分106之第一上表面124界定的平面122在第二部分108之第二上表面126上方。
可蝕刻第二部分108以在第二部分108之大部分區域上(在基板101的平面內)形成均勻的第二層厚度,諸如80%之區域、90%之區域、99%之區域等。以此方式,第二部分108可被蝕刻至目標平均層厚度,以將第二二極體120之擊穿電壓調整成不同於第一二極體118之擊穿電壓。由於第一部分106及第二部分108可具有相同的活性摻雜劑濃度,因此藉由蝕刻目標量之第二部分以達到目標厚度,待賦予第二二極體120之不同擊穿電壓可容易地調整至目標值。舉例而言,若第一二極體118形成具有60 μm之第一層厚度及600 V之擊穿電壓,則藉由蝕刻以得到30 μm的第二部分108之第二層厚度,從而得到遠小於600 V之擊穿電壓,可形成第二二極體120。
第一二極體118與第二二極體120之間的電壓不對稱的以上實例僅為例示性的,同時該等實施例在此背景下不受限制。在各種額外實施例中,第一二極體118可包含300 V或更高之一擊穿電壓,而第二二極體120包含100 V或更小之一擊穿電壓。此外,該等述實施例在此背景下不受限制。
在第一二極體118及第二二極體120展現功率容量上之不對稱性的其他實施例中,第一二極體118可包含700 W或更大之一功率容量,且該第二二極體可包含500 W或更小之一功率容量。第一二極體118及第二二極體120之功率容量可設定成彼此不同。功率容量可以藉由調整在基板101之平面(所示的笛卡爾坐標系之X-Y平面)內的第一部分106及第二部分108的區域來調整。根據領域中之已知技術,該等區域可以藉由形成不同大小之遮罩以界定第一部分106及第二部分108來調整。
針對不對稱裝置的圖1之設計之優點係引線框架可附接至基板101之僅一側,以便接觸不同二極體。圖2圖示TVS裝置組合150。TVS裝置組合150可包括TVS裝置100及引線框架160,其中引線框架160接觸TVS裝置100之第一表面,即圖1的上表面。在此實例中,引線框架160可包括第一部件162,其中第一部件162連接至TVS裝置100之第一部分106,而且可包括第二部件164,該第二部件耦合至TVS裝置100之第二部分108。在圖2之實例中,TVS組合包括外殼170,該外殼可為模製封裝。引線框架160可藉由焊接或其他接合方法便利地附接至TVS裝置100。
圖3繪示根據本發明之實施例的例示性程序流程300。在區塊302處,提供一基板,其中該基板包括一第一導電類型之一基底層。該基板可為例如p型矽基板,其中該基底層表示基板本身。在區塊304處,在該基底層上形成一第二導電類型之一磊晶層,其中該磊晶層安置於該基板之一第一側上。因而,當該基板基底係p型矽時,該磊晶層可為n型矽。可根據已知沈積方法來形成該磊晶層。該磊晶層中之摻雜劑濃度及該磊晶層之層厚度可根據待形成於基板中的二極體之電氣性質來設計。在各種實施例中,該磊晶層之層厚度可在20 μm至80 μm的範圍內。該等實施例在此背景下不受限制。
在區塊306處,在該磊晶層內形成一第一磊晶部分及一第二磊晶部分,其中該第一磊晶部分與該第二磊晶部分電隔離。可藉由根據已知技術產生隔離結構來形成該第一磊晶部分及該第二磊晶部分,其中該等隔離結構延伸遍及整個磊晶層。
在區塊308處,在該第二磊晶部分內形成一凹部,其中第一二極體及第二二極體形成於該磊晶層內、在該基板之該第一側上。因此,該第一二極體形成於該磊晶層之該第一部分中,該第一部分具有一第一層厚度,而該第二二極體形成於該磊晶層之該第二部分中,該第二部分具有一第二層厚度。因此,由於該第一部分與該第二部分之間的不同厚度,該第一二極體及該第二二極體在擊穿電壓方面可以彼此不同。以此方式,單面雙向不對稱裝置可便利地形成。
儘管已經參考特定實施例揭示了本發明實施例,但在不背離如隨附申請專利範圍中所界定的本發明之範圍及範疇的情況下,對所描述實施例之各種修改、變更及改變係可能的。因此,本發明實施例不限於所描述實施例,且可具有由以下技術方案及其等同物之語言界定的全範疇。
100‧‧‧暫態電壓抑制裝置
101‧‧‧基板
102‧‧‧基板基底
104‧‧‧磊晶層
106‧‧‧第一部分
108‧‧‧第二部分
110‧‧‧隔離結構
112‧‧‧溝槽
114、116‧‧‧觸點
118‧‧‧第一二極體
120‧‧‧第二二極體
122‧‧‧平面
124‧‧‧第一上表面
126‧‧‧第二上表面
160‧‧‧引線框架
162‧‧‧第一部件
164‧‧‧第二部件
300‧‧‧流程
302、304、306、308‧‧‧區塊
圖1圖示根據本發明之實施例的TVS裝置。
圖2圖示根據本發明之其他實施例的TVS裝置組合。
圖3繪示根據本發明之實施例的例示性程序流程。

Claims (18)

  1. 一種暫態電壓抑制(TVS)裝置,其包含: 形成於一基板中之一基板基底,該基板基底包含一第一導電類型之一半導體;以及 一磊晶層,該磊晶層安置於該基板基底上、在該基板之一第一側上,且包含一第二導電類型之一半導體,該磊晶層進一步包含: 一第一部分,該第一部分具有一第一層厚度;以及 一第二部分,該第二部分具有小於該第一層厚度之一第二層厚度,其中該第一部分及該第二部分安置於該基板之一第一側上,且其中該第一部分與該第二部分電隔離。
  2. 如申請專利範圍第1項所述的TVS裝置,其中該第一部分形成一第一二極體,其中該第二部分形成一第二二極體,且其中該第一二極體與該第二二極體在擊穿電壓、功率容量或擊穿電壓及功率容量上不同。
  3. 如申請專利範圍第2項所述的TVS裝置,其中該第一二極體及該第二二極體按陽極對陽極電氣串聯布置。
  4. 如申請專利範圍第1項所述的TVS裝置,其中該第一層厚度在20 μm至80 μm之間。
  5. 如申請專利範圍第1項所述的TVS裝置,其中該第二部分包含一溝槽形狀,其中由該第一部分之一第一上表面界定的一平面在該第二部分之一第二上表面上方。
  6. 如申請專利範圍第2項所述的TVS裝置,其中該第一二極體包含300 V或更高之一擊穿電壓,且其中該第二二極體包含100 V或更小之一擊穿電壓。
  7. 如申請專利範圍第2項所述的TVS裝置,其中該第一二極體包含700 W或更大之一功率容量,且其中該第二二極體包含500 W或更小之一功率容量。
  8. 一種暫態電壓抑制(TVS)裝置組合,其包含: 一TVS裝置,該TVS裝置包含: 形成於一基板中之一基板基底,該基板基底包含一第一導電類型之一半導體; 一磊晶層,該磊晶層安置於該基板基底上、在該磊晶層之一第一側上、包含一第二導電類型之一半導體,該磊晶層進一步包含: 一第一部分,該第一部分具有一第一層厚度;以及 一第二部分,該第二部分具有小於該第一層厚度之一第二層厚度,其中該第二部分包含一溝槽形狀,其中由該第一部分之一第一上表面界定的一平面在該第二部分之一第二上表面上方;以及 一引線框架,該引線框架耦合至該TVS裝置,該引線框架包含: 一第一部件,該第一部件連接至該TVS裝置之該第一部分;以及 一第二部件,該第二部件耦合至該TVS裝置之該第二部分。
  9. 如申請專利範圍第8項所述的TVS裝置組合,其中該引線框架安置於該TVS裝置之僅一側上。
  10. 如申請專利範圍第8項所述的TVS裝置組合,其中該第一部分及該第二部分安置於該基板之一第一側上,且其中該第一部分與該第二部分電隔離。
  11. 如申請專利範圍第8項所述的TVS裝置組合,其中該第一部分形成一第一二極體,其中該第二部分形成一第二二極體,且其中該第一二極體與該第二二極體在擊穿電壓、功率容量或擊穿電壓及功率容量上不同。
  12. 如申請專利範圍第11項所述的TVS裝置組合,其中該第一二極體及該第二二極體按陽極對陽極電氣串聯布置。
  13. 如申請專利範圍第11項所述的TVS裝置組合,其中該第一二極體包含300 V或更高之一擊穿電壓,且其中該第二二極體包含100 V或更小之一擊穿電壓。
  14. 如申請專利範圍第11項所述的TVS裝置組合,其中該第一二極體包含700 W或更大之一功率容量,且其中該第二二極體包含500 W或更小之一功率容量。
  15. 一種方法,其包含: 提供一基板,該基板具有一第一導電類型之一基底層; 在該基底層上形成一第二導電類型之一磊晶層,其中該磊晶層安置於該基板之一第一側上; 在該磊晶層內形成一第一磊晶部分及一第二磊晶部分,其中該第一磊晶部分與該第二磊晶部分電隔離;以及 在該第二磊晶部分內形成一凹部,其中一第一二極體及一第二二極體形成於該磊晶層內、在該基板之該第一側上。
  16. 如申請專利範圍第15項所述的方法,其中該第一部分形成一第一二極體,其中該第二部分形成一第二二極體,且其中該第一二極體與該第二二極體在擊穿電壓、功率容量或擊穿電壓及功率容量上不同。
  17. 如申請專利範圍第15項所述的方法,其中該第一部分包含一第一厚度,且其中該第二部分包含一第二厚度,該第二厚度小於該第一厚度。
  18. 如申請專利範圍第15項所述的方法,其進一步包含將一引線框架聯接至該基板,其中該引線框架僅安置於該基板之該第一側上。
TW107140878A 2017-11-17 2018-11-16 暫態電壓抑制器裝置、暫態電壓抑制器裝置組合以及形成方法 TWI788462B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/816,115 2017-11-17
US15/816,115 US10475787B2 (en) 2017-11-17 2017-11-17 Asymmetric transient voltage suppressor device and methods for formation

Publications (2)

Publication Number Publication Date
TW201937679A true TW201937679A (zh) 2019-09-16
TWI788462B TWI788462B (zh) 2023-01-01

Family

ID=66336309

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107140878A TWI788462B (zh) 2017-11-17 2018-11-16 暫態電壓抑制器裝置、暫態電壓抑制器裝置組合以及形成方法

Country Status (5)

Country Link
US (2) US10475787B2 (zh)
KR (1) KR102200785B1 (zh)
CN (1) CN109801910B (zh)
DE (1) DE102018009021A1 (zh)
TW (1) TWI788462B (zh)

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6867436B1 (en) * 2003-08-05 2005-03-15 Protek Devices, Lp Transient voltage suppression device
US7781826B2 (en) * 2006-11-16 2010-08-24 Alpha & Omega Semiconductor, Ltd. Circuit configuration and manufacturing processes for vertical transient voltage suppressor (TVS) and EMI filter
US20060216913A1 (en) * 2005-03-25 2006-09-28 Pu-Ju Kung Asymmetric bidirectional transient voltage suppressor and method of forming same
US9793256B2 (en) * 2006-11-30 2017-10-17 Alpha And Omega Semiconductor Incorporated Optimized configurations to integrate steering diodes in low capacitance transient voltage suppressor (TVS)
CN101527324B (zh) * 2008-12-08 2010-12-15 上海长园维安微电子有限公司 双向低压穿通瞬态电压抑制二极管及其制作方法
US8288839B2 (en) * 2009-04-30 2012-10-16 Alpha & Omega Semiconductor, Inc. Transient voltage suppressor having symmetrical breakdown voltages
US20110156682A1 (en) * 2009-12-30 2011-06-30 Dev Alok Girdhar Voltage converter with integrated schottky device and systems including same
KR101006768B1 (ko) * 2010-07-20 2011-01-10 주식회사 시지트로닉스 티브이에스 다이오드 어레이와 그 제조방법
US8835976B2 (en) * 2012-03-14 2014-09-16 General Electric Company Method and system for ultra miniaturized packages for transient voltage suppressors
US8835977B2 (en) * 2012-12-19 2014-09-16 Alpha And Omega Semiconductor Incorporated TVS with low capacitance and forward voltage drop with depleted SCR as steering diode
KR101649222B1 (ko) * 2014-10-17 2016-08-19 주식회사 시지트로닉스 비대칭 활성영역 조절에 의한 양방향 정전기, 전자기 간섭 및 서지 방호용 반도체 소자 및 그 제조 방법
CN205680681U (zh) * 2016-05-10 2016-11-09 北京燕东微电子有限公司 多通道瞬态电压抑制器
CN106129058B (zh) * 2016-08-27 2023-08-25 上海维安半导体有限公司 沟槽引出集成型低压双向瞬时电压抑制器及其制造方法

Also Published As

Publication number Publication date
CN109801910B (zh) 2024-08-13
KR102200785B1 (ko) 2021-01-12
US10957692B2 (en) 2021-03-23
US20190157265A1 (en) 2019-05-23
CN109801910A (zh) 2019-05-24
US20200035673A1 (en) 2020-01-30
US10475787B2 (en) 2019-11-12
DE102018009021A1 (de) 2019-05-23
TWI788462B (zh) 2023-01-01
KR20190056996A (ko) 2019-05-27

Similar Documents

Publication Publication Date Title
US20210119042A1 (en) Methods of Reducing the Electrical and Thermal Resistance of SIC Substrates and Device Made Thereby
US9035320B2 (en) Semiconductor device
JP2013140868A (ja) 半導体装置
TWI772556B (zh) 暫態電壓抑制裝置、暫態電壓抑制裝置總成及其形成方法
TWI582986B (zh) 矽控整流器
TW201937679A (zh) 暫態電壓抑制器裝置、暫態電壓抑制器裝置組合以及形成方法
US9453977B2 (en) Assembly of integrated circuit chips having an overvoltage protection component
TWI690083B (zh) 功率金氧半導體場效電晶體及其製作方法
US20120061719A1 (en) Shockley diode having a low turn-on voltage
JP2017041491A (ja) 半導体装置
US8963235B1 (en) Trench power device and semiconductor structure thereof
US9013027B2 (en) Semiconductor device, a semiconductor wafer structure, and a method for forming a semiconductor wafer structure
TWI708364B (zh) 半導體元件及其製造方法
TWI655746B (zh) 二極體與二極體串電路
JP2007227711A (ja) 半導体バルク抵抗素子
JP6294511B2 (ja) 半導体装置の製造方法及び半導体装置
JP2015177041A (ja) 半導体装置
KR100617866B1 (ko) 제너 다이오드 제조 및 패키징 방법
JP2008243863A (ja) Pinダイオードとその製造方法