CN109801910B - 不对称的瞬态电压抑制器装置以及形成方法 - Google Patents
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Abstract
一种瞬态电压抑制(TVS)装置,可以包括:形成于衬底中的衬底基底,所述衬底基底包括第一导电类型的半导体;以及外延层,所述外延层在所述衬底的第一侧上设置在所述衬底基底上并且包括第二导电类型的半导体。所述外延层可以包括:第一部分,所述第一部分具有第一层厚度;以及第二部分,所述第二部分具有小于所述第一层厚度的第二层厚度,其中所述第一部分和所述第二部分设置在所述衬底的第一侧上,并且其中所述第一部分与所述第二部分电隔离。
Description
技术领域
实施方案涉及电路保护装置的领域,所述电路保护装置包括熔断器装置。
背景技术
例如瞬态电压抑制器(TVS)装置的半导体装置可以制造成单向装置或双向装置。在双向装置的情况下,第一装置可以制造在半导体裸片(芯片)的第一侧上,而第二装置可以制造在所述半导体裸片的第二侧上。双向装置可以包括:对称装置,其中第一装置和第二装置相同;以及不对称装置,其中第一装置和第二装置在多个性质方面不同。
尽管此类双向装置在设计半导体裸片的不同侧上的不同装置的电性质方面提供一定灵活性,此类装置的封装可能相对较复杂。
关于这些和其他考量,提供本发明公开。
发明内容
示例性实施方案涉及改进的TVS装置和用于形成TVS装置的技术。
在一个实施方案中,一种瞬态电压抑制(TVS)装置可以包括:形成于衬底中的衬底基底,所述衬底基底包括第一导电类型的半导体;以及外延层,所述外延层在所述衬底的第一侧上设置在所述衬底基底上并且包括第二导电类型的半导体。所述外延层可以包括:第一部分,所述第一部分具有第一层厚度;以及第二部分,所述第二部分具有小于所述第一层厚度的第二层厚度,其中所述第一部分和所述第二部分设置在所述衬底的第一侧上,并且其中所述第一部分与所述第二部分电隔离。
在另一实施方案中,一种瞬态电压抑制(TVS)装置组合件可以包括:TVS装置,其中所述TVS装置包括形成于衬底中的衬底基底,所述衬底基底包括第一导电类型的半导体。所述TVS装置可以包括外延层,所述外延层在所述外延层的第一侧上设置在所述衬底基底上、包括第二导电类型的半导体。所述外延层还可以包括:第一部分,所述第一部分具有第一层厚度;以及第二部分,所述第二部分具有小于所述第一层厚度的第二层厚度,其中所述第二部分包括沟槽形状,其中由所述第一部分的第一上表面限定的平面在所述第二部分的第二上表面上方。所述TVS装置组合件还可以包括引线框,所述引线框耦合到所述TVS装置,所述引线框包括:第一部件,所述第一部件连接到所述TVS装置的所述第一部分;以及第二部件,所述第二部件耦合到所述TVS装置的所述第二部分。
在另一实施方案中,一种方法可以包括:提供衬底,所述衬底具有第一导电类型的基底层;在所述基底层上形成第二导电类型的外延层,其中所述外延层设置在所述衬底的第一侧上;在所述外延层内形成第一外延部分和第二外延部分,其中所述第一外延部分与所述第二外延部分电隔离;在所述第二外延部分内形成凹部,其中所述第一二极管和所述第二二极管形成于在所述衬底的所述第一侧上的所述外延层内。
附图说明
图1图示了根据本公开的实施方案的TVS装置;
图2图示了根据本公开的其他实施方案的TVS装置组合件;
图3描绘了根据本公开的实施方案的示例性工艺流程。
具体实施方式
现在将参考附图在下文更全面地描述本发明实施方案,附图中示出了示例性实施方案。所述实施方案不应解释为限于本文中所阐述的实施方案。更确切地说,提供这些实施方案,使得本公开将透彻且完整,并且将其范围全部传递给本领域技术人员。在图式中,相似数字始终指示相似元件。
在以下描述和/或权利要求中,术语“在......上”、“上覆于”、“设置在......上”以及“在......上方”可以在以下描述和权利要求中使用。“在......上”、“上覆于”、“设置在......上”以及“在......上方”可以用于指示两个或更多个元件彼此直接物理接触。此外,术语“在......上”、“上覆于”、“设置在......上”以及“在......上方”可以意味两个或更多个元件彼此不直接接触。举例来说,“在......上方”可意味一个元件在另一元件之上而彼此不接触,并且在所述两个元件之间可具有另一元件或多个元件。
在各种实施方案中,提供新颖装置结构和技术以用于形成双向TVS装置。
图1图示了根据本公开的实施方案的TVS装置100。TVS装置100可以包括形成于衬底101中的衬底基底102。衬底基座102可以由第一导电类型的半导体形成,第一导电类型的半导体例如P型半导体。TVS装置100还可以包括外延层104,如所示,所述外延层在衬底101的第一侧(图1中的顶面)上设置在衬底基座102上。外延层104可以由第二导电类型的半导体形成。举例来说,当衬底基座102是P型硅时,外延层可以是N型硅。举例来说,当衬底基座102是N型硅时,外延层可以是P型硅。因而,P/N结可以在衬底基座102与外延层104之间的界面处形成。外延层104还可以包括第一部分106和第二部分108。第一部分106可以具有第一层厚度,而第二部分108可以具有小于所述第一层厚度的第二层厚度。如所示,第一部分106和第二部分108设置在衬底101的第一侧上。借助隔离结构110,第一部分106与第二部分108电隔离。如所示,隔离结构110从衬底101的第一侧的表面延伸到衬底基座102中。隔离结构110可以用已知方式、例如使用沟槽绝缘体来形成。
因而,第一部分106连同衬底基座102形成第一二极管118。第二部分108连同衬底基座102形成第二二极管120。根据本公开的各种实施方案,所述第一二极管与所述第二二极管在击穿电压、功率容量或击穿电压和功率容量上不同。举例来说,由于外延层104的第二部分108与第一部分106相比具有相对较小的厚度,因此第二部分108的击穿电压与第一部分106的击穿电压相比可以较小。举例来说,第一部分106的第一层厚度在一些实施方案中可以在20μm与80μm之间,而针对第一部分106的给定第一层厚度,第二部分108的第二层厚度可小于所述给定第一层厚度。
如图1中进一步所示,形成于衬底101内的第一二极管118和第二二极管120按阳极对阳极配置的电气串联来布置。第一二极管118和第二二极管120的相应阴极可以通过分别形成于衬底101的第一侧上的触点114和触点116电接触。因而,TVS装置100可以形成不对称的单面双向装置。
第一二极管118与第二二极管120之间的电压不对称性的程度可以通过调整第一部分106的第一层厚度相比于第二部分108的第二层厚度的相对厚度来布置。举例来说,在各种实施方案中,外延层104形成为衬底基座102上的覆盖层(blanket layer),使得掺杂剂含量在外延层104上均匀。尽管第一部分106可以保持不被更改,但是在最初形成具有均匀厚度的外延层104之后,可以蚀刻第二部分108以减小第二部分108的层厚度。举例来说,可以通过在使第二部分108经受已知蚀刻剂的同时掩蔽第一部分106来选择性地蚀刻第二部分108,从而形成凹部或沟槽形状,如沟槽112所述。在图1的实例中,由第一部分106的第一上表面124限定的平面122在第二部分108的第二上表面126上方。
可以蚀刻第二部分108以在第二部分108的大部分区域上(在衬底101的平面内)形成均匀的第二层厚度,例如80%的区域、90%的区域、99%的区域等。这样,第二部分108可以被蚀刻到目标平均层厚度,以将第二二极管120的击穿电压调整成不同于第一二极管118的击穿电压。因为第一部分106和第二部分108可以具有相同的活性掺杂剂浓度,所以通过蚀刻目标量的第二部分以达到目标厚度,待赋予第二二极管120的不同击穿电压可以容易地调整到目标值。举例来说,如果第一二极管118形成具有60μm的第一层厚度和600V的击穿电压,则通过蚀刻以得到30μm的第二部分108的第二层厚度,从而得到远小于600V的击穿电压,可以形成第二二极管120。
第一二极管118与第二二极管120之间的电压不对称的以上实例仅为示例性的,同时所述实施方案在这个背景下不受限制。在各种额外实施方案中,第一二极管118可以包括300V或更高的击穿电压,而第二二极管120包括100V或更小的击穿电压。此外,所述实施方案在这个背景下不受限制。
在第一二极管118和第二二极管120展现功率容量上的不对称性的其他实施方案中,第一二极管118可以包括700W或更大的功率容量,并且所述第二二极管可以包括500W或更小的功率容量。第一二极管118和第二二极管120的功率容量可以设定成彼此不同。功率容量可以通过调整在衬底101的平面(所示的笛卡尔坐标系的X-Y平面)内的第一部分106和第二部分108的区域来调整。根据领域中的已知技术,所述区域可以通过形成不同大小的掩模以限定第一部分106和第二部分108来调整。
针对不对称装置的图1的设计的优点是引线框可以附接到衬底101的仅一侧,以便接触不同二极管。图2图示了TVS装置组合件150。TVS装置组合件150可以包括TVS装置100和引线框160,其中引线框160接触TVS装置100的第一表面,即图1的上表面。在这个实例中,引线框160可以包括第一部件162,其中第一部件162连接到TVS装置100的第一部分106,而且可以包括第二部件164,所述第二部件耦合到TVS装置100的第二部分108。在图2的实例中,所述TVS组合件包括外壳170,所述外壳可以是模制封装。引线框160可以通过焊接或其他联结方法便利地附接到TVS装置100。
图3描绘了根据本公开的实施方案的示例性工艺流程300。在块302,提供衬底,其中所述衬底包括第一导电类型的基底层。所述衬底可以是例如p型硅衬底,其中所述基底层表示衬底本身。在块304,在所述基底层上形成第二导电类型的外延层,其中所述外延层设置在所述衬底的第一侧上。因而,当所述衬底基底是p型硅时,所述外延层可以是n型硅。可以根据已知沉积方法来形成所述外延层。所述外延层中的掺杂剂浓度和所述外延层的层厚度可以根据待形成于衬底中的二极管的电气性质来设计。在各种实施方案中,所述外延层的层厚度可以在20μm到80μm的范围内。所述实施方案在这个背景下不受限制。
在块306,在所述外延层内形成第一外延部分和第二外延部分,其中所述第一外延部分与所述第二外延部分电隔离。可以通过根据已知技术产生隔离结构来形成所述第一外延部分和所述第二外延部分,其中所述隔离结构延伸遍及整个外延层。
在块308,在所述第二外延部分内形成凹部,其中第一二极管和第二二极管形成于在所述衬底的所述第一侧上的所述外延层内。因此,所述第一二极管形成于所述外延层的所述第一部分中,所述第一部分具有第一层厚度,而所述第二二极管形成于所述外延层的所述第二部分中,所述第二部分具有第二层厚度。因此,由于所述第一部分与所述第二部分之间的不同厚度,所述第一二极管和所述第二二极管在击穿电压方面可以彼此不同。这样,单面双向不对称装置可以便利地形成。
尽管已经参考特定实施方案公开了本发明实施方案,但是在不背离如随附权利要求中所限定的本公开的范围和范畴的情况下,对所描述实施方案的各种修改、变更和改变是可能的。因此,本发明实施方案不限于所描述实施方案,并且可以具有由上述权利要求以及其等同物的语言限定的全范围。
Claims (18)
1.一种瞬态电压抑制TVS装置,所述TVS装置包括:
形成于衬底中的衬底基底,所述衬底基底包括第一导电类型的半导体;以及
外延层,所述外延层在所述衬底的第一侧上直接设置在所述衬底基底上,并且包括第二导电类型的半导体,并且不包括所述第一导电类型的半导体,所述外延层还包括:
第一部分,形成第一二极管,并且从所述衬底基座与所述第一部分之间的界面延伸,直到所述衬底的上表面为止,所述第一部分具有第一层厚度;以及
第二部分,形成第二二极管,并且从所述衬底基座与所述第二部分之间的界面延伸,直到所述衬底的上表面为止,所述第二部分具有小于所述第一层厚度的第二层厚度,其中所述第一部分和所述第二部分设置在所述衬底的所述第一侧上,并且其中所述第一部分与所述第二部分电隔离。
2.如权利要求1所述的TVS装置,其中所述第一二极管与所述第二二极管在击穿电压上不同,在功率容量上不同,或者在击穿电压和功率容量上不同。
3.如权利要求2所述的TVS装置,其中所述第一二极管和所述第二二极管按阳极对阳极的电气串联来布置。
4.如权利要求1所述的TVS装置,其中所述第一层厚度在20 μm到80 μm之间。
5.如权利要求1所述的TVS装置,其中所述第二部分包括沟槽形状,其中由所述第一部分的第一上表面限定的平面在所述第二部分的第二上表面上方。
6.如权利要求2所述的TVS装置,其中所述第一二极管包括300 V或更高的击穿电压,并且其中所述第二二极管包括100 V或更小的击穿电压。
7.如权利要求2所述的TVS装置,其中所述第一二极管包括700 W或更大的功率容量,并且其中所述第二二极管包括500 W或更小的功率容量。
8.一种瞬态电压抑制TVS装置组合件,所述TVS装置组合件包括:
TVS装置,所述TVS装置包括:
形成于衬底中的衬底基底,所述衬底基底包括第一导电类型的半导体;
外延层,所述外延层在所述外延层的第一侧上直接设置在所述衬底基底上、包括第二导电类型的半导体,并且不包括所述第一导电类型的半导体,所述外延层还包括:
第一部分,形成第一二极管,并且从所述衬底基底与所述第一部分之间的界面延伸,直到所述衬底的上表面为止,所述第一部分具有第一层厚度;以及
第二部分,形成第二二极管,并且从所述衬底基底与所述第二部分之间的界面延伸,直到所述衬底的上表面为止,所述第二部分具有小于所述第一层厚度的第二层厚度,其中所述第二部分包括沟槽形状,其中由所述第一部分的第一上表面限定的平面在所述第二部分的第二上表面上方;以及
引线框,所述引线框耦合到所述TVS装置,所述引线框包括:
第一部件,所述第一部件连接到所述TVS装置的所述第一部分;以及
第二部件,所述第二部件耦合到所述TVS装置的所述第二部分。
9.如权利要求8所述的TVS装置组合件,其中所述引线框设置在所述TVS装置的仅一侧上。
10.如权利要求8所述的TVS装置组合件,其中所述第一部分和所述第二部分设置在所述衬底的第一侧上,并且其中所述第一部分与所述第二部分电隔离。
11.如权利要求8所述的TVS装置组合件,其中所述第一二极管与所述第二二极管在击穿电压上不同,在功率容量上不同,或者在击穿电压和功率容量上不同。
12.如权利要求11所述的TVS装置组合件,其中所述第一二极管和所述第二二极管按阳极对阳极的电气串联来布置。
13.如权利要求11所述的TVS装置组合件,其中所述第一二极管包括300 V或更高的击穿电压,并且其中所述第二二极管包括100 V或更小的击穿电压。
14.如权利要求11所述的TVS装置组合件,其中所述第一二极管包括700 W或更大的功率容量,并且其中所述第二二极管包括500 W或更小的功率容量。
15.一种用于制造瞬态电压抑制TVS装置的方法,所述方法包括:
提供衬底,所述衬底具有第一导电类型的衬底基底;
直接在所述衬底基底上形成第二导电类型的外延层,其中所述外延层设置在所述衬底的第一侧上;
在所述外延层内形成第一外延部分和第二外延部分,其中所述第一外延部分与所述第二外延部分电隔离,所述第一外延部分从所述衬底基底与所述第一外延部分之间的界面延伸,直到所述衬底的上表面为止,并且所述第二外延部分从所述衬底基底与所述第二外延部分之间的界面延伸,直到所述衬底的上表面为止,其中所述第一外延部分形成第一二极管,其中所述第二外延部分形成第二二极管;以及
在所述第二外延部分内形成凹部,
其中,在形成所述凹部之后,所述外延层不包括所述第一导电类型的半导体。
16.如权利要求15所述的方法,其中所述第一二极管与所述第二二极管在击穿电压上不同,在功率容量上不同,或者在击穿电压和功率容量上不同。
17.如权利要求15所述的方法,其中所述第一外延部分包括第一厚度,并且其中所述第二外延部分包括第二厚度,所述第二厚度小于所述第一厚度。
18.如权利要求15所述的方法,所述方法还包括将引线框结合到所述衬底,其中所述引线框仅设置在所述衬底的所述第一侧上。
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