TW201935656A - 靜電放電保護元件 - Google Patents

靜電放電保護元件 Download PDF

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TW201935656A
TW201935656A TW107105108A TW107105108A TW201935656A TW 201935656 A TW201935656 A TW 201935656A TW 107105108 A TW107105108 A TW 107105108A TW 107105108 A TW107105108 A TW 107105108A TW 201935656 A TW201935656 A TW 201935656A
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doped region
type doped
electrostatic discharge
discharge protection
protection element
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TW107105108A
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TWI661530B (zh
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徐睿翔
羅文駒
林志鋒
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力晶積成電子製造股份有限公司
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Priority to TW107105108A priority Critical patent/TWI661530B/zh
Priority to CN201810181933.3A priority patent/CN110164848B/zh
Priority to US15/975,791 priority patent/US10361187B1/en
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Abstract

一種靜電放電保護元件，包括沿著第一方向排列的矽控整流器與二極體串。矽控整流器包括彼此分離設置的陽極與陰極。陽極與陰極分別包括多個摻雜區。陽極中的摻雜區沿著第二方向排列。陰極中的摻雜區沿著第二方向排列。第一方向與第二方向相交。

Description

靜電放電保護元件
本發明是有關於一種半導體結構，且特別是有關於一種靜電放電保護元件。
靜電放電（electrostatic discharge，ESD）是電荷在非導體或未接地的導體上累積後，經由放電路徑，在短時間內快速移動放電的現象。靜電放電會造成積體電路中的電路損害，故通常會在半導體元件內設置靜電放電保護元件，以防止靜電放電所造成的損害。
然而，現有的靜電放電保護元件的佈局面積較大，因此如何有效地降低靜電放電保護元件的佈局面積為目前亟待解決的問題。
本發明提供一種靜電放電保護元件，其面積可大幅地降低。
本發明提出一種靜電放電保護元件，包括沿著第一方向排列的矽控整流器與二極體串。矽控整流器包括彼此分離設置的陽極與陰極。陽極與陰極分別包括多個摻雜區。陽極中的摻雜區沿著第二方向排列。陰極中的摻雜區沿著第二方向排列。第一方向與第二方向相交。
依照本發明的一實施例所述，在上述靜電放電保護元件中，陽極可位於陰極與二極體串之間。
依照本發明的一實施例所述，在上述靜電放電保護元件中，陽極中的摻雜區可彼此分離設置，且陰極中的摻雜區可彼此分離設置。
依照本發明的一實施例所述，在上述靜電放電保護元件中，陽極中的摻雜區可包括至少一個第一N型摻雜區與至少一個第一P型摻雜區。陰極中的摻雜區可包括至少一個第二N型摻雜區與至少一個第二P型摻雜區。
依照本發明的一實施例所述，在上述靜電放電保護元件中，第一N型摻雜區與第一P型摻雜區可彼此耦接。第二N型摻雜區與第二P型摻雜區可彼此耦接。
依照本發明的一實施例所述，在上述靜電放電保護元件中，在陽極中，第一P型摻雜區的總面積可大於第一N型摻雜區的總面積。
依照本發明的一實施例所述，在上述靜電放電保護元件中，在陽極中，第一P型摻雜區的總面積佔第一N型摻雜區與第一P型摻雜區的總面積的比例可為大於50%且小於等於70%。
依照本發明的一實施例所述，在上述靜電放電保護元件中，在陰極中，第二N型摻雜區的總面積可大於第二P型摻雜區的總面積。
依照本發明的一實施例所述，在上述靜電放電保護元件中，在陰極中，第二N型摻雜區的總面積佔第二N型摻雜區與第二P型摻雜區的總面積的比例可為大於50%且小於等於70%。
依照本發明的一實施例所述，在上述靜電放電保護元件中，矽控整流器更可包括N型井區與P型井區。陽極中的摻雜區位於N型井區中。陰極中的摻雜區位於P型井區中。
依照本發明的一實施例所述，在上述靜電放電保護元件中，二極體串可包括串接的多個二極體。二極體沿著第二方向排列。
依照本發明的一實施例所述，在上述靜電放電保護元件中，二極體分別可包括N型摻雜區與P型摻雜區。
依照本發明的一實施例所述，在上述靜電放電保護元件中，N型摻雜區與P型摻雜區可彼此分離設置。
依照本發明的一實施例所述，在上述靜電放電保護元件中，二極體串更可包括多個N型井區。二極體分別可位於N型井區中。
依照本發明的一實施例所述，在上述靜電放電保護元件中，矽控整流器可與二極體串耦接。
依照本發明的一實施例所述，在上述靜電放電保護元件中，矽控整流器的陽極可耦接於二極體串的輸入端。矽控整流器的陰極可耦接於二極體串的輸出端。
本發明提出另一種靜電放電保護元件，包括沿著第一方向排列的矽控整流器與二極體串。二極體串包括串接的多個二極體。二極體沿著第二方向排列。第一方向與第二方向相交。
依照本發明的另一實施例所述，在上述靜電放電保護元件中，二極體分別可包括N型摻雜區與P型摻雜區。
依照本發明的另一實施例所述，在上述靜電放電保護元件中，二極體串更可包括多個N型井區。二極體分別位於N型井區中。
依照本發明的另一實施例所述，在上述靜電放電保護元件中，矽控整流器可與二極體串耦接。
基於上述，在本發明一實施例所提出的靜電放電保護元件中，矽控整流器與二極體串沿著第一方向排列。在矽控整流器中，陽極中的摻雜區沿著第二方向排列，陰極中的摻雜區沿著第二方向排列，且第一方向與第二方向相交。藉此，靜電放電保護元件的佈局面積可大幅地降低，進而可具有較佳的靜電放電保護效能。
此外，在本發明另一實施例所提出的靜電放電保護元件中，矽控整流器與二極體串沿著第一方向排列。二極體串中的二極體沿著第二方向排列，且第一方向與第二方向相交。藉此，靜電放電保護元件的佈局面積可大幅地降低，進而可具有較佳的靜電放電保護效能。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1為本發明一實施例的靜電放電保護元件的上視圖。在圖1中，為了清楚地說明構件之間的關係，因而未繪示出隔離結構與內連線結構。圖2為沿著圖1中的I-I’剖面線的靜電放電保護元件的剖面圖。
請參照圖1與圖2，靜電放電保護元件100，包括沿著第一方向D1排列的矽控整流器200與二極體串300。第一方向D1與第二方向D2相交。矽控整流器200與二極體串300可藉由隔離結構102而彼此分離設置。隔離結構102例如是淺溝渠隔離結構(shallow trench isolation，STI)。
矽控整流器200包括彼此分離設置的陽極202與陰極204，且更可包括N型井區206與P型井區208。陽極202可位於陰極204與二極體串300之間，但本發明並不以此為限。舉例來說，陽極202與陰極204可藉由隔離結構210而彼此分離設置。隔離結構210例如是淺溝渠隔離結構。
陽極202包括多個摻雜區(如，N型摻雜區202N與P型摻雜區202P)。陽極202中的摻雜區沿著第二方向D2排列，藉此可大幅地降低佈局面積。陽極202中的摻雜區可彼此分離設置。陽極202中的摻雜區可位於N型井區206中。舉例來說，陽極202中的摻雜區可包括至少一個N型摻雜區202N與至少一個P型摻雜區202P。在此實施例中，陽極202中的摻雜區是以包括一個N型摻雜區202N與一個P型摻雜區202P為例來進行說明，但本發明並不以此為限。在其他實施例中，所屬技術領域具有通常知識者可依照產品需求調整N型摻雜區202N與P型摻雜區202P的數量。
N型摻雜區202N與P型摻雜區202P沿著第二方向D2排列。N型摻雜區202N與P型摻雜區202P可位於N型井區206中。202PN型摻雜區202N與P型摻雜區202P可藉由隔離結構212而彼此分離設置。隔離結構212例如是淺溝渠隔離結構。此外，N型摻雜區202N與P型摻雜區202P可藉由內連線結構214而彼此耦接。內連線結構214可為導線、接觸窗(contact)、介層窗(via)或其組合。
在陽極202中，P型摻雜區202P的總面積可大於N型摻雜區202N的總面積。舉例來說，P型摻雜區202P的總面積佔N型摻雜區202N與P型摻雜區202P的總面積的比例可為大於50%且小於等於70%，例如是60%。
陰極204包括多個摻雜區(如，N型摻雜區204N與P型摻雜區204P)。陰極204中的摻雜區沿著第二方向D2排列，藉此可大幅地降低佈局面積。陰極204中的摻雜區可彼此分離設置。陰極204中的摻雜區可位於P型井區208中。舉例來說，陰極204中的摻雜區可包括至少一個N型摻雜區204N與至少一個P型摻雜區204P。在此實施例中，陰極204中的摻雜區是以包括一個N型摻雜區204N與兩個P型摻雜區204P為例來進行說明，但本發明並不以此為限。在其他實施例中，所屬技術領域具有通常知識者可依照產品需求調整N型摻雜區204N與P型摻雜區204P的數量。
N型摻雜區204N與P型摻雜區204P沿著第二方向D2排列。N型摻雜區204N與P型摻雜區204P可位於P型井區208中。N型摻雜區204N與P型摻雜區204P可藉由隔離結構216而彼此分離設置。隔離結構216例如是淺溝渠隔離結構。此外，N型摻雜區204N與P型摻雜區204P可藉由內連線結構218而彼此耦接。內連線結構218可為導線、接觸窗、介層窗或其組合。
在陰極204中，N型摻雜區204N的總面積可大於P型摻雜區204P的總面積。舉例來說，N型摻雜區204N的總面積佔N型摻雜區204N與P型摻雜區204P的總面積的比例可為大於50%且小於等於70%，例如是60%。
二極體串300可包括串接的二極體302a~302e，且更可包括多個N型井區304。二極體302a~302e分別可位於N型井區304中。二極體302a~302e沿著第二方向D2排列。二極體302a~302e可藉由隔離結構306而彼此隔離設置。隔離結構306例如是淺溝渠隔離結構。在此實施例中，二極體串300中的二極體數量是以五個為例來進行說明，但本發明並不以此為限。只要二極體串300包括多個串接的二極體即屬於本發明所主張的範圍。
二極體302a~302e分別可包括N型摻雜區308N與P型摻雜區308P。在二極體串300的二極體302a~302e中，位於二極體串300的輸出端的二極體302e可具有最大的面積。N型摻雜區308N與P型摻雜區308P分別可位於N型井區304中。二極體302a~302e的串接方法例如是藉由內連線結構310而彼此耦接。舉例來說，可藉由內連線結構310將二極體302a中的摻雜區308N與二極體302b中的摻雜區308P進行耦接，而使得二極體302a與二極體302b彼此串接。內連線結構310可為導線、接觸窗、介層窗或其組合。N型摻雜區308N與P型摻雜區308P可藉由隔離結構312而彼此分離設置。隔離結構312例如是淺溝渠隔離結構。
矽控整流器200可與二極體串300耦接。矽控整流器200的陽極202可耦接於二極體串300的輸入端(如，二極體302a的P型摻雜區308P)。矽控整流器200的陰極204可耦接於二極體串300的輸出端(如，二極體302e的N型摻雜區308N)。舉例來說，矽控整流器200的陽極202可藉由內連線結構104耦接於二極體302a的P型摻雜區308P(二極體串300的輸入端)，且矽控整流器200的陰極204可藉由內連線結構106耦接於二極體302e的N型摻雜區308N(二極體串300的輸出端)。內連線結構104、106分別可為導線、接觸窗、介層窗或其組合。
在此實施例中，靜電放電保護元件100是以同時採用上述矽控整流器200的佈局方式與上述二極體串300的佈局方式為例來進行說明，然而本發明並不以此為限。在其他實施例中，只要靜電放電保護元件採用上述矽控整流器200的佈局方式與上述二極體串300的佈局方式中的至少一者，即可達成降低佈局面積的目的，且屬於本發明所主張的範圍。
基於上述實施例可知，在本發明一實施例所提出的靜電放電保護元件100中，矽控整流器200與二極體串300沿著第一方向D1排列。在矽控整流器200中，陽極202中的摻雜區沿著第二方向D2排列，陰極204中的摻雜區沿著第二方向D2排列，且第一方向D1與第二方向D2相交。藉此，靜電放電保護元件100的佈局面積可大幅地降低，進而可具有較佳的靜電放電保護效能。
此外，在本發明另一實施例所提出的靜電放電保護元件100中，矽控整流器200與二極體串300沿著第一方向D1排列。二極體串300中的二極體沿著第二方向D2排列，且第一方向D1與第二方向D2相交。藉此，靜電放電保護元件100的佈局面積可大幅地降低，進而可具有較佳的靜電放電保護效能。
另外，在本發明另一實施例所提出的靜電放電保護元件100中，亦可同時採用上述矽控整流器200的佈局方式與上述二極體串300的佈局方式，藉此可更進一步地降低靜電放電保護元件100的佈局面積，且可進一步地提升靜電放電保護效能。
綜上所述，上述實施例的靜電放電保護元件可藉由特定的佈局方式來降低佈局面積，進而可提升靜電放電保護效能。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100‧‧‧靜電放電保護元件
102、210、212、216、306、312‧‧‧隔離結構
104、106、214、218、310‧‧‧內連線結構
200‧‧‧矽控整流器
202‧‧‧陽極
202N、204N、308N‧‧‧N型摻雜區
202P、204P、308P‧‧‧P型摻雜區
204‧‧‧陰極
206、304‧‧‧N型井區
208‧‧‧P型井區
300‧‧‧二極體串
302a~302e‧‧‧二極體
圖1為本發明一實施例的靜電放電保護元件的上視圖。 圖2為沿著圖1中的I-I’剖面線的靜電放電保護元件的剖面圖。

Claims (20)

  1. 一種靜電放電保護元件，包括沿著第一方向排列的矽控整流器與二極體串，其中 所述矽控整流器包括彼此分離設置的陽極與陰極， 所述陽極與所述陰極分別包括多個摻雜區， 所述陽極中的所述多個摻雜區沿著第二方向排列， 所述陰極中的所述多個摻雜區沿著所述第二方向排列，且 所述第一方向與所述第二方向相交。
  2. 如申請專利範圍第1項所述的靜電放電保護元件，其中所述陽極位於所述陰極與所述二極體串之間。
  3. 如申請專利範圍第1項所述的靜電放電保護元件，其中所述陽極中的所述多個摻雜區彼此分離設置，且所述陰極中的所述多個摻雜區彼此分離設置。
  4. 如申請專利範圍第1項所述的靜電放電保護元件，其中 所述陽極中的所述多個摻雜區包括至少一個第一N型摻雜區與至少一個第一P型摻雜區，且 所述陰極中的所述多個摻雜區包括至少一個第二N型摻雜區與至少一個第二P型摻雜區。
  5. 如申請專利範圍第4項所述的靜電放電保護元件，其中所述至少一個第一N型摻雜區與所述至少一個第一P型摻雜區彼此耦接，且所述至少一個第二N型摻雜區與所述至少一個第二P型摻雜區彼此耦接。
  6. 如申請專利範圍第4項所述的靜電放電保護元件，其中在所述陽極中，所述至少一個第一P型摻雜區的總面積大於所述至少一個第一N型摻雜區的總面積。
  7. 如申請專利範圍第6項所述的靜電放電保護元件，其中在所述陽極中，所述至少一個第一P型摻雜區的總面積佔所述至少一個第一N型摻雜區與所述至少一個第一P型摻雜區的總面積的比例為大於50%且小於等於70%。
  8. 如申請專利範圍第4項所述的靜電放電保護元件，其中在所述陰極中，所述至少一個第二N型摻雜區的總面積大於所述至少一個第二P型摻雜區的總面積。
  9. 如申請專利範圍第8項所述的靜電放電保護元件，其中在所述陰極中，所述至少一個第二N型摻雜區的總面積佔所述至少一個第二N型摻雜區與所述至少一個第二P型摻雜區的總面積的比例為大於50%且小於等於70%。
  10. 如申請專利範圍第1項所述的靜電放電保護元件，其中所述矽控整流器更包括： N型井區，其中所述陽極中的所述多個摻雜區位於所述N型井區中；以及 P型井區，其中所述陰極中的所述多個摻雜區位於所述P型井區中。
  11. 如申請專利範圍第1項所述的靜電放電保護元件，其中所述二極體串包括串接的多個二極體，其中所述多個二極體沿著第二方向排列。
  12. 如申請專利範圍第11項所述的靜電放電保護元件，其中所述多個二極體分別包括N型摻雜區與P型摻雜區。
  13. 如申請專利範圍第12項所述的靜電放電保護元件，其中所述N型摻雜區與P型摻雜區彼此分離設置。
  14. 如申請專利範圍第11項所述的靜電放電保護元件，其中所述二極體串更包括多個N型井區，其中所述多個二極體分別位於所述多個N型井區中。
  15. 如申請專利範圍第1項所述的靜電放電保護元件，其中所述矽控整流器與所述二極體串耦接。
  16. 如申請專利範圍第15項所述的靜電放電保護元件，其中所述矽控整流器的所述陽極耦接於所述二極體串的輸入端，且所述矽控整流器的所述陰極耦接於所述二極體串的輸出端。
  17. 一種靜電放電保護元件，包括沿著第一方向排列的矽控整流器與二極體串，其中 所述二極體串包括串接的多個二極體， 所述多個二極體沿著第二方向排列，且 所述第一方向與所述第二方向相交。
  18. 如申請專利範圍第17項所述的靜電放電保護元件，其中所述多個二極體分別包括N型摻雜區與P型摻雜區。
  19. 如申請專利範圍第17項所述的靜電放電保護元件，其中所述二極體串更包括多個N型井區，其中所述多個二極體分別位於所述多個N型井區中。
  20. 如申請專利範圍第17項所述的靜電放電保護元件，其中所述矽控整流器與所述二極體串耦接。
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US10361187B1 (en) 2019-07-23

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