TW201920735A - 用於銅互連件之晶種層 - Google Patents
用於銅互連件之晶種層 Download PDFInfo
- Publication number
- TW201920735A TW201920735A TW107129279A TW107129279A TW201920735A TW 201920735 A TW201920735 A TW 201920735A TW 107129279 A TW107129279 A TW 107129279A TW 107129279 A TW107129279 A TW 107129279A TW 201920735 A TW201920735 A TW 201920735A
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- copper
- ruthenium
- substrate
- copper layer
- Prior art date
Links
- 239000010949 copper Substances 0.000 title claims abstract description 164
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 161
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 159
- 238000000034 method Methods 0.000 claims abstract description 76
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims abstract description 59
- 229910052707 ruthenium Inorganic materials 0.000 claims abstract description 59
- 239000000758 substrate Substances 0.000 claims description 45
- 230000008569 process Effects 0.000 claims description 32
- 239000000463 material Substances 0.000 claims description 31
- 238000000151 deposition Methods 0.000 claims description 30
- 230000004888 barrier function Effects 0.000 claims description 21
- 239000012713 reactive precursor Substances 0.000 claims description 20
- 239000001257 hydrogen Substances 0.000 claims description 12
- 229910052739 hydrogen Inorganic materials 0.000 claims description 12
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 11
- 239000002243 precursor Substances 0.000 claims description 10
- 229910052721 tungsten Inorganic materials 0.000 claims description 8
- 239000010937 tungsten Substances 0.000 claims description 8
- -1 tungsten nitride Chemical class 0.000 claims description 7
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 4
- IUYOGGFTLHZHEG-UHFFFAOYSA-N copper titanium Chemical compound [Ti].[Cu] IUYOGGFTLHZHEG-UHFFFAOYSA-N 0.000 claims description 4
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 239000012691 Cu precursor Substances 0.000 claims 2
- 239000003989 dielectric material Substances 0.000 claims 1
- 238000013508 migration Methods 0.000 abstract description 3
- 230000005012 migration Effects 0.000 abstract description 2
- 238000005240 physical vapour deposition Methods 0.000 description 15
- 238000000231 atomic layer deposition Methods 0.000 description 13
- 238000005229 chemical vapour deposition Methods 0.000 description 13
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 8
- 230000008021 deposition Effects 0.000 description 6
- 230000009471 action Effects 0.000 description 5
- 238000005054 agglomeration Methods 0.000 description 5
- 230000002776 aggregation Effects 0.000 description 5
- 229910052786 argon Inorganic materials 0.000 description 4
- 239000011261 inert gas Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000011148 porous material Substances 0.000 description 4
- 238000004070 electrodeposition Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- KAKZBPTYRLMSJV-UHFFFAOYSA-N Butadiene Chemical compound C=CC=C KAKZBPTYRLMSJV-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005429 filling process Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 230000002401 inhibitory effect Effects 0.000 description 2
- 238000010926 purge Methods 0.000 description 2
- PIZHFBODNLEQBL-UHFFFAOYSA-N 2,2-diethoxy-1-phenylethanone Chemical compound CCOC(OCC)C(=O)C1=CC=CC=C1 PIZHFBODNLEQBL-UHFFFAOYSA-N 0.000 description 1
- VZEZONWRBFJJMZ-UHFFFAOYSA-N 3-allyl-2-[2-(diethylamino)ethoxy]benzaldehyde Chemical compound CCN(CC)CCOC1=C(CC=C)C=CC=C1C=O VZEZONWRBFJJMZ-UHFFFAOYSA-N 0.000 description 1
- STHPMJODTLZBKU-UHFFFAOYSA-N C(C)C(C(C)O[Cu]OC(C)C(CC)NC)NC Chemical compound C(C)C(C(C)O[Cu]OC(C)C(CC)NC)NC STHPMJODTLZBKU-UHFFFAOYSA-N 0.000 description 1
- HVHUYKPEEWRAAQ-UHFFFAOYSA-N C(C)C(CC(C)O[Cu]OC(C)CC(CC)NC)NC Chemical compound C(C)C(CC(C)O[Cu]OC(C)CC(CC)NC)NC HVHUYKPEEWRAAQ-UHFFFAOYSA-N 0.000 description 1
- CJBVLDGFTXMPNM-UHFFFAOYSA-N C(C)N(CC)C([O-])C.[Cu+2].C(C)N(CC)C([O-])C Chemical compound C(C)N(CC)C([O-])C.[Cu+2].C(C)N(CC)C([O-])C CJBVLDGFTXMPNM-UHFFFAOYSA-N 0.000 description 1
- BLTHGIYPBPNNDK-UHFFFAOYSA-N C(C)N(CC)CCC(C)O[Cu]OC(C)CCN(CC)CC Chemical compound C(C)N(CC)CCC(C)O[Cu]OC(C)CCN(CC)CC BLTHGIYPBPNNDK-UHFFFAOYSA-N 0.000 description 1
- PFORRKRPODKAAY-UHFFFAOYSA-N CN(C)CC(C)(C)O[Cu]OC(C)(C)CN(C)C Chemical compound CN(C)CC(C)(C)O[Cu]OC(C)(C)CN(C)C PFORRKRPODKAAY-UHFFFAOYSA-N 0.000 description 1
- RBHOTLNMLNPNKT-UHFFFAOYSA-N CN(C)CCC(C)O[Cu]OC(C)CCN(C)C Chemical compound CN(C)CCC(C)O[Cu]OC(C)CCN(C)C RBHOTLNMLNPNKT-UHFFFAOYSA-N 0.000 description 1
- MFKNGWLTPFGBBK-UHFFFAOYSA-N COC(C)(C)O[Cu]OC(C)(C)OC Chemical compound COC(C)(C)O[Cu]OC(C)(C)OC MFKNGWLTPFGBBK-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910017566 Cu-Mn Inorganic materials 0.000 description 1
- 229910017767 Cu—Al Inorganic materials 0.000 description 1
- 229910017871 Cu—Mn Inorganic materials 0.000 description 1
- 102100027094 Echinoderm microtubule-associated protein-like 1 Human genes 0.000 description 1
- 101001057941 Homo sapiens Echinoderm microtubule-associated protein-like 1 Proteins 0.000 description 1
- 101000653787 Mus musculus Protein S100-A11 Proteins 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- WYEMLYFITZORAB-UHFFFAOYSA-N boscalid Chemical compound C1=CC(Cl)=CC=C1C1=CC=CC=C1NC(=O)C1=CC=CN=C1Cl WYEMLYFITZORAB-UHFFFAOYSA-N 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- JYVFVHINVDAPJO-UHFFFAOYSA-N copper;1-(dimethylamino)propan-2-olate Chemical compound [Cu+2].CC([O-])CN(C)C.CC([O-])CN(C)C JYVFVHINVDAPJO-UHFFFAOYSA-N 0.000 description 1
- LJNKLCWPWAPYME-UHFFFAOYSA-N copper;2,2,6,6-tetramethylheptane-3,5-dione Chemical compound [Cu].CC(C)(C)C(=O)CC(=O)C(C)(C)C.CC(C)(C)C(=O)CC(=O)C(C)(C)C LJNKLCWPWAPYME-UHFFFAOYSA-N 0.000 description 1
- AOPSBLDLHFNEAG-UHFFFAOYSA-N copper;2-methoxyethanolate Chemical compound [Cu+2].COCC[O-].COCC[O-] AOPSBLDLHFNEAG-UHFFFAOYSA-N 0.000 description 1
- 150000004985 diamines Chemical class 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 239000011572 manganese Substances 0.000 description 1
- WPBNNNQJVZRUHP-UHFFFAOYSA-L manganese(2+);methyl n-[[2-(methoxycarbonylcarbamothioylamino)phenyl]carbamothioyl]carbamate;n-[2-(sulfidocarbothioylamino)ethyl]carbamodithioate Chemical compound [Mn+2].[S-]C(=S)NCCNC([S-])=S.COC(=O)NC(=S)NC1=CC=CC=C1NC(=S)NC(=O)OC WPBNNNQJVZRUHP-UHFFFAOYSA-L 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 150000002902 organometallic compounds Chemical class 0.000 description 1
- 125000002524 organometallic group Chemical group 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
- H01L21/28562—Selective deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
- H01L2221/1073—Barrier, adhesion or liner layers
- H01L2221/1084—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L2221/1089—Stacks of seed layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01044—Ruthenium [Ru]
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Electroplating Methods And Accessories (AREA)
Abstract
本文描述用於形成具有改進的抗遷移性質的銅晶種層的方法。在一個實施方式中,方法包括以下步驟:在特徵中形成第一銅層;在特徵中的第一銅層上形成釕層,和在特徵中的釕層上形成第二銅層。釕層實質上將在其下方的銅層鎖定在特徵中的適當位置中,從而防止其大量的實體遷移。
Description
本文所述的實施方式總體涉及半導體裝置製造的領域,並且更特別地涉及形成用於銅互連件的晶種層的方法。
隨著下一代裝置的電路密度增大且電晶體尺寸繼續縮小,接線互連件的電阻和導電性開始在大部分裝置效能指標,包括功耗、電阻-電容(RC)延遲和可靠性中主導裝置效能。銅是用於先進USLI和VSLI技術中的接線互連件的一種材料,因為銅一般呈現相對低電阻率和高導電性。通常,在將塊體銅電鍍到銅晶種層上之前或在塊體銅回流到銅晶種層中之前,通過將銅晶種層沉積到形成在基板的材料表面中的開口中來形成銅互連件。
典型地,銅晶種層攜帶所需電流用於後續的電鍍製程或用作潤濕層以促進銅回流到形成在基板的材料表面中的開口中。銅晶種層在開口的壁或基部上的覆蓋物中的間隙將導致互連結構的塊體銅材料中的不期望的孔隙。塊體銅材料中的孔隙或覆蓋間隙造成銅結構的電遷移失敗,這可能會使得所得裝置無用或能力降低。銅晶種層覆蓋間隙的起因包括銅附聚或不連續的沉積中的一者或兩者。銅附聚在沉積的銅通過將銅從周圍區域拉走而在一些區域中聚結成更厚的覆蓋物時發生。在開口的壁上的不連續的沉積典型地是由於針對一些開口幾何形狀的銅種晶物理氣相沉積(PVD)製程所固有的陰影效應。
沉積在銅晶種層上的導電襯裡,諸如金屬襯裡,填充開口的壁或基部上的晶種層的覆蓋物中的間隙,這減少了在後續的電鍍製程期間的塊體銅材料中的孔隙。然而,設置在銅晶種層與塊體銅層之間的導電襯裡非期望地在銅晶種層和塊體銅層之間形成介面襯裡/銅層。此介面層非期望地降低總銅線寬度,並且因此非期望地增大後續形成的銅互連件的線電阻率。
因此,本領域中需要的是改進的銅晶種層和形成改進的銅晶種層的方法。
本公開內容大體上描述了形成釕摻雜的銅晶種層的方法。
在一個實施方式中,提供形成互連結構的方法。方法包括以下步驟:將圖案化基板定位在第一處理腔室中,圖案化基板具有形成在其材料層中的開口;以及在開口的壁上形成晶種層。在開口的壁上形成晶種層之步驟包括:形成第一銅層;在第一銅層上形成釕層;以及在釕層上形成第二銅層。
在另一實施方式中,形成裝置的方法包括以下步驟:在圖案化基板上沉積第一銅層,圖案化基板包括其中形成有開口的材料層和設置在材料層上的阻擋層;在第一銅層上沉積釕層;以及在釕層上沉積第二銅層。在一些實施方式中,方法進一步包括使用電沉積製程、回流間隙填充製程或以上項的組合來將銅層沉積到開口中之步驟。
在另一實施方式中,形成銅互連件的方法包括以下步驟:將圖案化基板定位在處理腔室中,圖案化基板具有形成在其材料層中的開口;以及在開口的壁上形成晶種層。在開口的壁上形成晶種層之步驟包括:在圖案化基板上沉積第一銅層;在第一銅層上沉積釕層;以及在釕層上沉積第二銅層。沉積第一銅層之步驟包括將圖案化基板順序地暴露於包含含銅有機金屬的第一反應性前驅物和包含氫的第二反應性前驅物。沉積釕層包括將第一銅層順序地暴露於包含含釕有機金屬的第三反應性前驅物和包含氫的第四反應性前驅物。沉積第二銅層之步驟包括將釕層順序地暴露於第一反應性前驅物和第二反應性前驅物。
在一些實施方式中,本文所述的方法進一步包括使用電沉積製程、回流間隙填充製程或以上項的組合來將銅層沉積到開口中之步驟。
在另一實施方式中,裝置包括:基板,特徵為圖案化表面,圖案化表面具有形成在其材料層中的多個開口;和晶種層,設置在開口的壁上。在此,晶種層包括:第一銅層;釕層,設置在第一銅層上;和第二銅層,設置在釕層上。
本公開內容的實施方式總體描述形成銅互連結構、特別地形成釕摻雜的銅晶種層的方法,釕摻雜的銅晶種層包括多個銅層和設置在銅層之間的至少一個釕層。本文所述的方法可在物理氣相沉積(PVD)處理腔室、化學氣相沉積(CVD)處理腔室、原子層沉積(ALD)處理腔室或以上項的組合中執行。在一個實施方式中,PVD、CVD和ALD處理腔室分別是ENDURA® PVD處理腔室、PRODUCER® CVD處理腔室和OLYMPIA® ALD處理腔室,它們均可得自加利福尼亞州聖克拉拉市的應用材料公司(Applied Materials, Inc., Santa Clara, California)。
根據本文所述的方法形成的釕摻雜的晶種層使得能夠在互連開口的壁上覆蓋連續的晶種層並促進減小襯裡厚度。在本文中,釕摻雜的晶種層包括沉積在第一銅層與第二銅層之間的至少一個釕層。典型地,使用PVD製程、CVD製程或ALD製程來沉積第一銅層和第二銅層,並且使用CVD製程或ALD製程來沉積釕層。銅和釕一般彼此不可混溶,因此釕層有效地將第一層和第二層的銅釘紮在其間形成的晶界處,並如期望地將銅鎖定在特徵中的適當位置處。將銅釘紮在形成在銅層與釕層之間的晶界處防止銅層中的銅移動以形成非期望的銅附聚體。此外,使用本文所述的方法防止銅電遷移允許通過防止與其相關的裝置故障來增大電路密度且提高可靠性。
使用本文提供的實施方式抑制銅附聚的益處進一步包括使得能夠減小設置在具有其中形成有開口的介電層上的襯裡層的厚度。襯裡層的厚度減小增大了後續形成的互連件的塊體銅體積。塊體銅體積的這種增加有利地降低了開口中的線電阻。釘紮銅層有利地減弱了互連特徵開口的壁上的覆蓋間隙。減弱由銅遷移引起的覆蓋間隙有利地減弱了或減少了在後續的電沉積或回流/間隙填充製程期間在銅互連件的塊體銅材料中形成的孔隙。有益地,釕比其他摻雜劑(諸如鈷或錳)更慢地擴散到銅中,使得通過在晶種層中使用釕,塊體銅層的線電阻不會被不利地影響。此外,根據所述實施方式形成的釕摻雜的晶種層提供相對薄且連續的表面,以促進後續的銅回流/間隙填充製程。
第1圖是根據一個實施方式的闡述形成釕參雜的銅晶種層的方法的流程圖。第2A-2E圖示出了第1圖中闡述的方法的元件。
在動作110處,方法100包括將圖案化基板定位在處理腔室中之步驟。第2A圖中示出了圖案化基板200,圖案化基板包括基板201、形成在基板201上的材料層209、形成在材料層209中的一個或多個開口205,以及設置在材料層209的開口205上並襯於其中的阻擋層206。在本文中,材料層209包括一個或多個介電層,諸如第一介電層202和第二介電層204。典型地,一個或多個介電層202、204由選自由以下組成的群組中的材料形成:氧化矽、SiN、SiOC、SIC、低介電常數聚合物(諸如聚醯胺)和以上項的組合。
在一些實施方式中,材料層209進一步包括設置在第一介電層202與第二介電層204之間的蝕刻停止層203。設置在材料層209上的阻擋層206防止銅原子從後續沉積的銅層擴散到周圍的介電層202、204中。典型地,阻擋層206包括金屬、金屬氮化物、金屬合金或以上項的組合中的一種或多種。在一些實施方式中,阻擋層206選自由以下組成的群組:鉭、氮化鉭、鎢、鈦、鈦鎢、氮化鈦、氮化鎢、鈦銅和以上項的組合。在一些實施方式中,阻擋層包括氮化鉭。阻擋層206使用任何合適的方法沉積,諸如化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或以上項的組合。
在動作120處,方法100包括在阻擋層206上形成晶種層207之步驟。第2B圖示出了沉積在圖案化基板200的阻擋層206上的晶種層207。第2E圖是第2B圖的一部分的近視圖。
在動作130處,方法100包括在圖案化基板200的阻擋層206上沉積第一銅層207a之步驟。使用原子層沉積(ALD)製程沉積在此處的第一銅層207a之步驟,包括將圖案化基板200順序地暴露於包含含銅有機金屬的第一反應性前驅物和包含含氫氣體的第二反應性前驅物以形成銅膜。含銅有機金屬氣體的示例包括雙(二乙基氨基-2-正丁氧基)銅(Cu(DEAB)2)、雙(乙基甲基氨基-2-正丁氧基)銅、雙(二甲基氨基-2-丙氧基)銅(Cu) (DMAP)2)、雙(二甲基氨基-2-正丁氧基)銅(Cu(DMAB)2)、雙(二甲基氨基-2-乙氧基)銅、雙(乙基甲基氨基-2-丙氧基)銅(Cu(EMAP)2)、雙(二乙基氨基-2-乙氧基)銅、雙(乙基甲基氨基-2-甲基-2-正丁氧基)銅、雙(二甲基氨基-2-甲基-2-丙氧基)銅、雙(二乙基氨基-2-丙氧基)銅( Cu(DEAP)2)、雙(2-甲氧基乙氧基)銅、雙(2,2,6,6-四甲基-3,5-庚二酮)銅、雙(2,2,6,6-四甲基-3,5-庚烷酮亞胺)銅、雙(2-甲氧基-2-丙氧基)銅和2,2,6,6-四甲基-3,5-庚二酮銅(TMVS),以及以上項的組合。含氫前驅物的示例包括H2、NH3和以上項的組合。在一些實施方式中,使用惰性氣體,諸如氬,在第一前驅物和第二前驅物的交替暴露之間淨化處理空間。
在一些實施方式中,在第一銅層207a的沉積期間,處理腔室維持在約1托至約30托的壓力下,並且圖案化基板維持在約50℃至約400℃的溫度下。第一反應性前驅物和第二反應性前驅物的流率對於經配置以處理300 mm直徑基板的處理腔室來說典型地是在約3000 sccm與約9000 sccm之間,並且針對不同大小的基板而適當地縮放。在一些實施方式中,處理腔室是電漿增強處理腔室,其中設置在處理腔室中的電極耦合到電漿電源。電漿電源提供約100 W至1000 W之間,諸如在13.56 MHz的頻率下約400 W,以將前驅物點燃並維持為處理電漿。在一些實施方式中,第一銅層207a具有大於約99%的銅純度。在其他實施方式中,使用物理氣相沉積(PVD)或化學氣相沉積(CVD)製程來沉積第一銅層。例如,在一個實施方式中,使用PVD製程沉積第一銅層207a,其中靶是純銅靶或銅合金靶,諸如包含在約0.1%與約3% Al之間的Cu-Al靶或包含約0.1%至約3%Mn的Cu-Mn靶。在該實施方式中,靶耦合到在約20 kW與約40 kW之間的DC功率,並且基板耦合到在約50 W與約1500 W之間的AC偏置功率。在另一實施方式中,使用CVD或PVD製程沉積第一銅層207a。
在動作140處,方法100包括在第一銅層207a上沉積釕層207b之步驟。在此,在與用於沉積第一銅層207a相同的處理腔室中沉積釕層207b。典型地,在沉積第一銅層207a和沉積釕層之間,使用惰性氣體(諸如氬)淨化處理腔室。在一些實施方式中,使用ALD製程沉積釕層207b之步驟,包括交替地將其上沉積有第一銅層207a的圖案化基板200順序地暴露於包含含釕有機金屬的第三反應性前驅物,並然後是包含氫(諸如氫氣)的第四反應性前驅物。含釕有機金屬化合物的示例包括甲基-環己二釕三羰基環己二胺、三羰基釕、丁二烯三羰基釕、二甲基丁二烯三羰基釕、具有Ru(CO)3的改性二胺和以上項的組合。
典型地,在釕層207b的沉積期間,處理腔室維持在約1托至約50托的壓力下,並且圖案化基板維持在約100℃至約400℃的溫度下。第三反應性前驅物和第四反應性前驅物的流率對於經配置以處理300 mm直徑基板的ALD處理腔室來說在約3000 sccm與約9000 sccm之間,並且針對不同大小的基板而適當地縮放。在一些實施方式中,設置在處理腔室中的電極耦合到電漿電源,電漿電源提供約100 W和1000 W之間,例如在13.56MHz的頻率下約400 W,其點燃並維持設置在其中的前驅物氣體的處理電漿。在一些實施方式中,使用惰性氣體,諸如氬,在第三前驅物和第四前驅物的交替暴露之間淨化處理空間。在其他實施方式中,使用CVD製程沉積和/或在與用於形成第一銅層207a的處理腔室不同的處理腔室中沉積釕層207b。在其他實施方式中,使用PVD製程沉積釕層207b。
在動作150處,方法100包括在釕層207b上沉積第二銅層207c之步驟。在一些實施方式中,將第二銅層207c沉積在一處理腔室中,所述處理腔室與用於在動作130處形成第一銅層207a並且在動作140處形成釕層207b的處理腔室相同。在一些實施方式中,使用與用於在動作130處形成第一銅層207a相同的製程沉積第二銅層207c。典型地,在沉積釕層207b與第二銅層207c之間,用惰性氣體(諸如氬)來淨化ALD處理腔室。在其他實施方式中,使用PVD製程或CVD製程在與用於形成第一銅層207a和/或釕層207b的腔室不同的腔室中沉積第二銅層207c。在一些實施方式中,用於形成阻擋層206、銅層207a、207c和/或釕層207b的處理腔室通過維持在次大氣壓下的傳送腔室在真空或受控環境下連接在一起以防止沉積層在其上形成後續層之前表面氧化。
在本文中,阻擋層206具有第一厚度T(1),第一厚度T(1)在約0.5 nm與約20 nm之間,諸如在約1 nm與約5 nm之間,例如約2 nm。第一銅層207a具有第二厚度T(2),第二厚度T(2)在約0.5 nm與約20nm之間,諸如在約0.5 nm與約10 nm之間,諸如在約0.5 nm與約5 nm之間,例如約4 nm。釕層207b具有第三厚度T(3),第三厚度T(3)在約1埃(Å)與約20 Å之間,諸如在約1 Å與約15 Å之間,諸如在約1 Å與約10 Å之間。第二銅層207c具有第四厚度T(4),第四厚度T(4)在約0.5 nm與約200 nm之間,諸如在約1 nm與約20 nm之間,或在約1 nm與約5 nm之間,例如約2 nm。典型地,晶種層207中的銅與釕的比率在約99.9:1與約4:1之間,其中相應的銅層和釕層207a、207b和207c的厚度T(2)、T(3)和T(4)經調整以增大或減小晶種層中的釕的濃度。
在一些實施方式中,形成晶種層207之步驟包括在沉積第二且最終的銅層207c之前順序地沉積多個第一銅層207a和釕層207b。
第2D和2E圖進一步示出了銅互連件的形成。第2D圖示出了使用電鍍製程或銅回流/間隙填充製程(例如,熱輔助的回流製程)沉積在晶種層上的塊體銅層208。然後,使用塊體膜去除製程(諸如化學機械平坦化(CMP))從基板的表面去除塊體銅層208,以形成銅互連結構,諸如第2D圖中所示的互連結構。
本文所述的方法的益處包括在晶種層的形成期間抑制銅附聚,減少其連續的覆蓋所需的最小晶種層厚度,改進較薄的晶種層的回流填充,以及改進在其上形成的銅互連件的線和/或通孔電阻。此外,除了抑制銅附聚之外,本文的實施方式的益處包括抑制銅電遷移,其通過防止與之相關的裝置故障而允許增大電路密度和改進可靠性和/或使用壽命。
儘管前述內容涉及本公開內容的實施方式,但是也可在不脫離本公開內容的基本範圍的情況下設計本公開內容的其他和進一步實施方式,並且本公開內容的範圍是由隨附的申請專利範圍確定。
100‧‧‧方法
110‧‧‧動作
120‧‧‧動作
130‧‧‧動作
140‧‧‧動作
150‧‧‧動作
200‧‧‧圖案化基板
201‧‧‧基板
202‧‧‧第一介電層
203‧‧‧蝕刻停止層
204‧‧‧第二介電層
205‧‧‧開口
206‧‧‧阻擋層
207‧‧‧晶種層
207a‧‧‧第一銅層
207b‧‧‧釕層
207c‧‧‧第二銅層
208‧‧‧塊體銅層
209‧‧‧材料層
為了可詳細地理解本公開內容的上述特徵所用方式,上文簡要地概述的本公開內容的更特定的描述可以參考實施方式進行,實施方式中的一些示出在隨附附圖中。然而,將注意,隨附圖式僅示出了本公開內容的典型實施方式,並且因此不應視為限制本公開內容的範圍,因為本公開內容可允許其他等效實施方式。
第1圖是根據一個實施方式的闡述形成釕摻雜的銅晶種層的方法的流程圖。
第2A-2E圖示出了根據一個實施方式的第1圖中闡述的方法的元件。
為了促進理解,已經儘可能地使用相同的附圖標記標示各圖共有的相同元件。將構想,一個實施方式的元件和特徵可有益地併入在其他實施方式中,不再贅述。
國內寄存資訊 (請依寄存機構、日期、號碼順序註記) 無
國外寄存資訊 (請依寄存國家、機構、日期、號碼順序註記) 無
Claims (20)
- 一種形成一互連結構的方法,包含以下步驟: 將一基板定位在一第一處理腔室中,該基板包含一圖案化表面,該圖案化表面具有形成在其一材料層中的開口;以及 在該等開口的壁上形成一晶種層,包含以下步驟: 在該等開口的該等壁上形成一第一銅層; 在該第一銅層上形成一釕層;以及 在該釕層上形成一第二銅層。
- 如請求項1所述的方法,其中形成該釕層之步驟包含順序地重複將該基板暴露於一釕前驅物及將該基板暴露於一含氫前驅物。
- 如請求項1所述的方法,其中使用一PVD製程、一CVD製程、一ALD製程或彼等的一組合之至少一者來沉積該第一銅層和該第二銅層。
- 如請求項1所述的方法,其中在一第二處理腔室中形成該釕層,該第二處理腔室不同於用於形成該第一銅層的該第一處理腔室。
- 如請求項1所述的方法,其中在該第一處理腔室中形成該第一銅層、該釕層和該第二銅層,而不從該第一處理腔室中移除該基板。
- 如請求項1所述的方法,其中該晶種層中的銅與釕的比率在約99.9:1與約4:1之間。
- 如請求項1所述的方法,其中該釕層的一厚度在約1埃與約20埃之間。
- 如請求項1所述的方法,其中該圖案化表面進一步包含設置在該材料層上的一阻擋層,該阻擋層包含選自由以下組成的群組中的一材料:鉭、氮化鉭、鎢、鈦、鈦鎢、氮化鈦、氮化鎢、鈦銅和彼等的一組合,並且其中該第一銅層形成在該阻擋層上。
- 如請求項8所述的方法,其中在一第二處理腔室中沉積該阻擋層,並且其中該第一處理腔室和該第二處理腔室由一傳送腔室連接在一起。
- 如請求項1所述的方法,其中形成該第一銅層之步驟包含順序地重複將該基板暴露於一銅前驅物及將該基板暴露於一氫前驅物。
- 如請求項10所述的方法,其中沉積該第二銅層之步驟包含順序地重複將該基板暴露於該銅前驅物及將該基板暴露於該氫前驅物。
- 一種形成一裝置的方法,包含以下步驟: 在一圖案化基板上沉積一第一銅層,該圖案化基板包含其中形成有開口的一材料層和設置在該材料層上的一阻擋層; 在該第一銅層上沉積一釕層;以及 在該釕層上沉積一第二銅層。
- 如請求項12所述的方法,其中該材料層包含一介電層。
- 如請求項13所述的方法,其中該阻擋層包括選自由以下組成的群組中的一材料:鉭、氮化鉭、鎢、鈦、鈦鎢、氮化鈦、氮化鎢、鈦銅和彼等的一組合。
- 如請求項14所述的方法,其中沉積該第一銅層和該第二銅層之步驟包含將該圖案化基板順序地暴露於包含一含銅有機金屬的一第一反應性前驅物和包含氫的一第二反應性前驅物。
- 如請求項15所述的方法,其中沉積該釕層之步驟包含將該圖案化基板和沉積在其上的該第一銅層順序地暴露於包含一含釕有機金屬的一第三反應性前驅物和包含氫的一第四反應性前驅物。
- 如請求項12所述的方法,其中沉積該第一銅層和該第二銅層之步驟包含一PVD製程,並且其中沉積該釕層之步驟包含將該圖案化基板順序地暴露於包含一含釕有機金屬的一第一反應性前驅物和包含氫的一第二反應性前驅物。
- 一種裝置,包括: 一基板,包含一圖案化表面,該圖案化表面具有形成在其一材料層中的複數個開口;和 一晶種層,設置在該等開口的壁上,該晶種層包含: 一第一銅層; 一釕層,設置在該第一銅層上;和 一第二銅層,設置在該釕層上。
- 如請求項18所述的裝置,其中該釕層的一厚度在約1埃與約20埃之間。
- 如請求項18所述的裝置,其中該材料層包含一介電材料,並且該裝置進一步包含插入在該晶種層與該等開口的該等壁之間的一阻擋層,並且其中該阻擋層包含選自由以下組成的群組中的一材料:鉭、氮化鉭、鎢、鈦、鈦鎢、氮化鈦、氮化鎢、鈦銅和彼等的一組合。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201762548604P | 2017-08-22 | 2017-08-22 | |
US62/548,604 | 2017-08-22 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201920735A true TW201920735A (zh) | 2019-06-01 |
TWI803510B TWI803510B (zh) | 2023-06-01 |
Family
ID=63350353
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW107129279A TWI803510B (zh) | 2017-08-22 | 2018-08-22 | 用於銅互連件之晶種層 |
Country Status (6)
Country | Link |
---|---|
US (1) | US10847463B2 (zh) |
EP (1) | EP3447793B1 (zh) |
JP (2) | JP2019062190A (zh) |
KR (1) | KR20190021184A (zh) |
CN (1) | CN109461698B (zh) |
TW (1) | TWI803510B (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113471070B (zh) * | 2020-05-22 | 2022-04-12 | 北京屹唐半导体科技股份有限公司 | 使用臭氧气体和氢自由基的工件加工 |
US11410881B2 (en) | 2020-06-28 | 2022-08-09 | Applied Materials, Inc. | Impurity removal in doped ALD tantalum nitride |
Family Cites Families (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7910165B2 (en) * | 2002-06-04 | 2011-03-22 | Applied Materials, Inc. | Ruthenium layer formation for copper film deposition |
US7101790B2 (en) | 2003-03-28 | 2006-09-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming a robust copper interconnect by dilute metal doping |
JP2006097044A (ja) * | 2004-09-28 | 2006-04-13 | L'air Liquide Sa Pour L'etude & L'exploitation Des Procede S Georges Claude | 成膜用前駆体、ルテニウム含有膜の成膜方法、ルテニウム膜の成膜方法、ルテニウム酸化物膜の成膜方法およびルテニウム酸塩膜の成膜方法 |
US7265048B2 (en) * | 2005-03-01 | 2007-09-04 | Applied Materials, Inc. | Reduction of copper dewetting by transition metal deposition |
US20060246699A1 (en) * | 2005-03-18 | 2006-11-02 | Weidman Timothy W | Process for electroless copper deposition on a ruthenium seed |
JP2008098449A (ja) * | 2006-10-12 | 2008-04-24 | Ebara Corp | 基板処理装置及び基板処理方法 |
US20080164613A1 (en) | 2007-01-10 | 2008-07-10 | International Business Machines Corporation | ULTRA-THIN Cu ALLOY SEED FOR INTERCONNECT APPLICATION |
US20080223287A1 (en) * | 2007-03-15 | 2008-09-18 | Lavoie Adrien R | Plasma enhanced ALD process for copper alloy seed layers |
US20100200991A1 (en) * | 2007-03-15 | 2010-08-12 | Rohan Akolkar | Dopant Enhanced Interconnect |
US7659204B2 (en) * | 2007-03-26 | 2010-02-09 | Applied Materials, Inc. | Oxidized barrier layer |
US7737028B2 (en) | 2007-09-28 | 2010-06-15 | Applied Materials, Inc. | Selective ruthenium deposition on copper materials |
JP2009116952A (ja) * | 2007-11-06 | 2009-05-28 | Hitachi Global Storage Technologies Netherlands Bv | 垂直磁気記録媒体およびこれを用いた磁気記憶装置 |
TW200951241A (en) | 2008-05-30 | 2009-12-16 | Sigma Aldrich Co | Methods of forming ruthenium-containing films by atomic layer deposition |
US7964497B2 (en) * | 2008-06-27 | 2011-06-21 | International Business Machines Corporation | Structure to facilitate plating into high aspect ratio vias |
US20090321935A1 (en) | 2008-06-30 | 2009-12-31 | O'brien Kevin | Methods of forming improved electromigration resistant copper films and structures formed thereby |
US8084104B2 (en) | 2008-08-29 | 2011-12-27 | Asm Japan K.K. | Atomic composition controlled ruthenium alloy film formed by plasma-enhanced atomic layer deposition |
JP2010215982A (ja) * | 2009-03-18 | 2010-09-30 | Tosoh Corp | ルテニウム錯体有機溶媒溶液を用いたルテニウム含有膜製造方法、及びルテニウム含有膜 |
JP2012074608A (ja) * | 2010-09-29 | 2012-04-12 | Tokyo Electron Ltd | 配線形成方法 |
CN102332426A (zh) * | 2011-09-23 | 2012-01-25 | 复旦大学 | 一种用于纳米集成电路的铜扩散阻挡层的制备方法 |
US9076661B2 (en) * | 2012-04-13 | 2015-07-07 | Applied Materials, Inc. | Methods for manganese nitride integration |
US9142509B2 (en) * | 2012-04-13 | 2015-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Copper interconnect structure and method for forming the same |
CN102903699A (zh) * | 2012-10-15 | 2013-01-30 | 复旦大学 | 一种铜互连结构及其制备方法 |
US20140134351A1 (en) * | 2012-11-09 | 2014-05-15 | Applied Materials, Inc. | Method to deposit cvd ruthenium |
CN103266304B (zh) | 2013-05-31 | 2015-12-23 | 江苏科技大学 | 一种高热稳定性无扩散阻挡层Cu(Ru)合金材料的制备方法 |
US9984975B2 (en) * | 2014-03-14 | 2018-05-29 | Taiwan Semiconductor Manufacturing Company | Barrier structure for copper interconnect |
JP6278827B2 (ja) * | 2014-05-14 | 2018-02-14 | 株式会社Adeka | 銅化合物、薄膜形成用原料及び薄膜の製造方法 |
US20160032455A1 (en) | 2014-07-31 | 2016-02-04 | Applied Materials, Inc. | High through-put and low temperature ald copper deposition and integration |
US9768060B2 (en) * | 2014-10-29 | 2017-09-19 | Applied Materials, Inc. | Systems and methods for electrochemical deposition on a workpiece including removing contamination from seed layer surface prior to ECD |
US10002834B2 (en) * | 2015-03-11 | 2018-06-19 | Applied Materials, Inc. | Method and apparatus for protecting metal interconnect from halogen based precursors |
KR20160123793A (ko) * | 2015-04-17 | 2016-10-26 | 포항공과대학교 산학협력단 | 이중층 구조를 가지는 저항변화메모리 및 이중층 구조를 가지는 저항변화메모리의 제조방법 |
CN105355620B (zh) * | 2015-12-17 | 2018-06-22 | 上海集成电路研发中心有限公司 | 一种铜互连结构及其制造方法 |
-
2018
- 2018-08-13 US US16/102,533 patent/US10847463B2/en active Active
- 2018-08-17 EP EP18189568.1A patent/EP3447793B1/en active Active
- 2018-08-21 JP JP2018154364A patent/JP2019062190A/ja active Pending
- 2018-08-22 TW TW107129279A patent/TWI803510B/zh active
- 2018-08-22 KR KR1020180097909A patent/KR20190021184A/ko not_active Application Discontinuation
- 2018-08-22 CN CN201810960756.9A patent/CN109461698B/zh active Active
-
2023
- 2023-09-25 JP JP2023159999A patent/JP2023182638A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
US10847463B2 (en) | 2020-11-24 |
EP3447793A1 (en) | 2019-02-27 |
JP2023182638A (ja) | 2023-12-26 |
CN109461698B (zh) | 2024-04-12 |
TWI803510B (zh) | 2023-06-01 |
US20190067201A1 (en) | 2019-02-28 |
KR20190021184A (ko) | 2019-03-05 |
EP3447793B1 (en) | 2021-01-06 |
CN109461698A (zh) | 2019-03-12 |
JP2019062190A (ja) | 2019-04-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR102189781B1 (ko) | 망간 및 망간 니트라이드들의 증착 방법들 | |
KR20190050869A (ko) | 루테늄 라이너로 구리 전자 이동을 개선하기 위한 도핑된 선택적 금속 캡 | |
KR102036245B1 (ko) | 구리 배리어 적용들을 위한 도핑된 탄탈룸 질화물 | |
JP2020506540A (ja) | ルテニウムドーピングにより強化される耐コバルト凝集性及び間隙充填作用 | |
US9343402B2 (en) | Semiconductor device having Ti- and N-containing layer, and manufacturing method of same | |
US20080242088A1 (en) | Method of forming low resistivity copper film structures | |
US20100151676A1 (en) | Densification process for titanium nitride layer for submicron applications | |
US20090087982A1 (en) | Selective ruthenium deposition on copper materials | |
TW201709293A (zh) | 用於內連線的釕金屬特徵部填補 | |
TWI559402B (zh) | 含銅種晶層之原子層沉積技術 | |
US8058164B2 (en) | Methods of fabricating electronic devices using direct copper plating | |
TWI694501B (zh) | 防止銅擴散的介電/金屬阻障集成 | |
JP2009231497A (ja) | 半導体装置及び半導体装置の製造方法 | |
JP2023182638A (ja) | 銅配線のためのシード層 | |
KR102279757B1 (ko) | 확산 방지막의 형성 방법, 상기 확산 방지막을 포함하는 반도체 소자의 금속 배선 및 이의 제조 방법 | |
JP2005203569A (ja) | 半導体装置の製造方法及び半導体装置 | |
JP2006024668A (ja) | 半導体装置の製造方法 | |
KR100622639B1 (ko) | 반도체 소자의 제조 방법 | |
KR100503965B1 (ko) | 반도체 소자의 확산 방지막 형성 방법 | |
TW202315118A (zh) | 經摻雜之含鉭阻障膜 | |
JP2006147895A (ja) | 半導体装置の製造方法 |