TW201911427A - 半導體模組之製造方法及半導體模組 - Google Patents
半導體模組之製造方法及半導體模組 Download PDFInfo
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- TW201911427A TW201911427A TW107101523A TW107101523A TW201911427A TW 201911427 A TW201911427 A TW 201911427A TW 107101523 A TW107101523 A TW 107101523A TW 107101523 A TW107101523 A TW 107101523A TW 201911427 A TW201911427 A TW 201911427A
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Abstract
本發明之課題在於提高半導體模組之可靠性。 於半導體模組SA之組裝之樹脂塑模步驟中,將IGBT晶片10、二極體晶片、控制晶片、及晶片搭載部TAB1~4各者之一部分,以自密封體MR之背面BS6露出晶片搭載部TAB1~4各者之背面之方式進行樹脂塑模。於上述樹脂塑模後,以覆蓋晶片搭載部TAB1~4各者之背面(露出部)之方式,於密封體MR之背面BS6貼附絕緣層70,其後,將TIM層80貼附於絕緣層70。此處,於俯視下之TIM層80之區域包含於絕緣層70之區域內。
Description
本發明係例如關於一種功率半導體模組(IPM(Intelligent Power Module:智慧型功率模組)、電子裝置等)之製造方法及其構造。
於日本特開2012-195492號公報(專利文獻1),記載一種關於具有MOSFET(Metal Oxide Semiconductor Field Effect Transistor,金屬氧化物半導體場效電晶體)之功率半導體模組與其安裝構造之技術。該功率半導體模組具備搭載功率半導體元件之第1金屬基板、與未搭載功率半導體元件之第2金屬基板,成為於上述第1金屬基板之與功率半導體元件搭載面相反側之背面露出於樹脂封裝外且形成散熱面之構造。 於日本特開2005-109100號公報(專利文獻2)中,記載具備功率晶片之半導體裝置及其製造技術。具體而言,於記載於上述專利文獻2之半導體裝置之組裝中,揭示一種將已安裝金屬箔之樹脂薄片配置於樹脂密封用模具之內部底面且進行樹脂塑模之技術。 [先前技術文獻] [專利文獻] [專利文獻1]日本特開2012-195492號公報 [專利文獻2]日本特開2005-109100號公報
[發明所欲解決之問題] 於功率系統之半導體模組中,於搭載半導體晶片之晶片搭載部不自密封體露出之全模塑模類型之構造中,自晶片搭載部向密封體外部之散熱性較差。因此,本發明人針對具備分別搭載複數個半導體晶片之複數個晶片搭載部之半導體模組,檢討使複數個晶片搭載部之一部分露出於密封體外部之構造。 經本發明人研究,發現於使複數個晶片搭載部之一部分露出於密封體外部之構造之半導體模組中,若將該半導體模組安裝於散熱板,則有複數個晶片搭載部之一部分經由散熱板而短路之可能性,於考慮半導體模組之可靠性之情形時,有應改善之事項。 其他課題與新穎之特徵應可自本說明書之記述及附加圖式明瞭。 [解決問題之技術手段] 一實施形態之半導體模組之製造方法係將第1半導體晶片、第2半導體晶片、第1晶片搭載部之一部分及第2晶片搭載部之一部分,以上述第1晶片搭載部之第2面與上述第2晶片搭載部之第2面各者自密封體之第2面露出之方式加以密封。於上述密封後,以覆蓋上述第1晶片搭載部之上述第2面與上述第2晶片搭載部之上述第2面之方式,於上述密封體之上述第2面貼附絕緣層,其後,於上述絕緣層貼附熱傳導材料層。此處,於俯視下,上述熱傳導材料層之區域包含於上述絕緣層之區域內。 又,一實施形態之其他半導體模組之製造方法係將第1半導體晶片、第2半導體晶片、第1晶片搭載部之一部分及第2晶片搭載部之一部分,以上述第1晶片搭載部之第2面與上述第2晶片搭載部之第2面各者自密封體之第2面露出之方式加以密封。於上述密封後,以接合絕緣層與熱傳導材料層而形成之薄片構造體之上述絕緣層覆蓋上述第1晶片搭載部之上述第2面與上述第2晶片搭載部之上述第2面之方式,將上述薄片構造體貼附於上述密封體之上述第2面。此處,於俯視下,上述薄片構造體中之上述熱傳導材料層之區域包含於上述絕緣層之區域內。 又,一實施形態之半導體模組具有密封體,該密封體具有第1面與第2面,且將第1半導體晶片、第2半導體晶片、第1晶片搭載部之一部分及第2晶片搭載部之一部分,以上述第1晶片搭載部之第2面與上述第2晶片搭載部之第2面各者自上述第2面露出之方式加以密封。進而,於上述密封體之上述第2面具有以覆蓋上述第1晶體搭載部之上述第2面與上述第2晶體搭載部之上述第2面之方式接合之絕緣層,及與上述絕緣層積層並接合之熱傳導材料層。且,於俯視下,上述熱傳導材料層之區域包含於上述絕緣層之區域內。 [發明之效果] 根據上述一實施形態,可提高半導體模組之可靠性。
於以下之實施形態中,除特別需要時以外,原則上不重複同一或相同部分之說明。 又,以下之實施形態中,為方便起見於有必要時,對複數之部份或實施形態進行分割說明,但,除了特別明示之情形以外,該等部份並非相互間無關係者,而係一者為另一者之一部分或全部之變形例、細節、補充說明等之關係。 又,以下之實施形態,提及要件之數目等(包含個數、數值、量及範圍等)之情形,除了特別明示之情形及原理上明確限定為特定數目之情形等以外,並不限定於其特定之數目,亦可取特定之數目以上或以下者。 又,於以下實施形態中,其構成要素(亦包含要素步驟等)除了特別明示之情形及原理上可認為明顯必須之情形等以外,當然未必一定為必須者。 又,以下之實施形態,關於構成要件等,提及「具有A」及「包含A」時,除了特別明示僅為該要件之情形等以外,當然並非排除其以外之要件。同樣,於以下實施形態中,言及構成要素等之形狀、位置關係等時,除特別明示之情形及認為原理上明確否定之情形等外,設為實質上包含與其形狀等近似或類似者等者。此情況對於上述數值及範圍亦相同。 以下,根據圖式詳細說明本發明之實施形態。另,於用以說明實施形態之全部圖中,對具有相同功能之構件標註相同符號,且省略其重複之說明。另,存在為使圖式易懂而即使為俯視圖仍標註陰影線之情形。 <用語之說明> 於本說明書中,「半導體模組」意指半導體零件(半導體晶片)與電性連接該半導體零件之外部連接端子之構造體,且意指半導體零件以密封體覆蓋之構造體。尤其,「半導體模組」係構成為可藉由外部連接端子與外部裝置電性連接。 又,於本說明書中,「功率電晶體」意指藉由排列連接複數個單位電晶體(胞電晶體)(例如排列連接數千個至數萬個單位電晶體),即使於較單位電晶體之容許電流更大之電流中,亦可實現單位電晶體功能之單位電晶體之集合體。例如,於單位電晶體作為開關元件發揮功能之情形時,「功率電晶體」成為亦可應用於較單位電晶體之容許電流更大電流之開關元件。作為構成開關元件之「功率電晶體」,可例示IGBT(Insulated Gate Bipolar Transistor:絕緣閘極型雙極電晶體)與功率MOSFET。於本說明書中,「功率電晶體」等用語係例如作為顯示包含「功率MOSFET」與「IGBT」之兩者之上位概念之語句而使用。 (實施形態1) <半導體模組之構造> 圖1係顯示實施形態1之半導體模組之構造之俯視圖,圖2係顯示圖1之半導體模組之構造之背面圖,圖3係顯示沿圖2之A-A線切斷之構造之剖視圖,圖4係顯示沿圖2之B-B線切斷之構造之剖視圖,圖5係顯示圖1之半導體模組之內部構造之透射俯視圖。 圖1~圖5所示之本實施形態1之半導體模組係例如使用於在空調等所使用之3相感應馬達之驅動電路者。具體而言,於該驅動電路,包含反相器電路,該反相器電路係具有將直流電力轉換為交流電力之功能之電路。 於本實施形態1中,係說明於內置於半導體模組之功率電晶體為IGBT之情形,且將複數個IGBT晶片組入半導體模組之情形。另,於無需區別形成有構成3相反相器電路之IGBT的複數個半導體晶片時,於本說明書中,僅稱為「IGBT晶片10」,同樣地,於無需區別形成有構成3相反相器電路之二極體的複數個半導體晶片時,於本說明書中,僅稱為「二極體晶片20」。 若對本實施形態1之半導體模組SA之概略構成進行說明,則如圖3~圖5所示,組入各內置功率電晶體之複數個IGBT晶片10、各具有二極體之複數個二極體晶片20及控制複數個IGBT晶片10各者之動作之控制晶片30。且,包含第1半導體晶片及第2半導體晶片之複數個IGBT晶片10與複數個二極體晶片20係分別經由導電性之接合材60而搭載於晶片搭載部TAB1~4之任一者,另一方面,控制晶片30係經由非導電性之接合材65搭載於晶片搭載部TAB5。 又,如圖5所示,控制晶片30與IGBT晶片10係藉由金導線40電性連接,IGBT晶片10與二極體晶片20係藉由較金導線40線徑更大之鋁導線50而電性連接。此處,金導線40係以金(Au)為主成分之導電性構件,另一方面,鋁導線50係以鋁(Al)為主成分之導電性構件。 又,於晶片搭載部TAB1~TAB5之周圍,設置有複數根導線LD1及導線LD2。複數根導線LD1係配置於晶片搭載部TAB5之周圍,另一方面,複數根導線LD2係配置於晶片搭載部TAB1~4之周圍。且,控制晶片30與複數根導線LD1係分別藉由金導線40電性連接,另一方面,二極體晶片20與複數根導線LD2係分別藉由鋁導線50電性連接。另,於複數根導線LD2,存在有與晶體搭載部TAB2一體地連接者,及與晶片搭載部TAB分開之引線單獨者。具體而言,搭載於晶片搭載部TAB1之IGBT晶片10經由二極體晶片20及鋁導線50而與任意晶片搭載部TAB電性連接。另一方面,搭載於晶片搭載部TAB2~4各者之IGBT晶片10係經由二極體晶片20及鋁導線50而與任一單獨引線LD2電性連接。 又,複數個IGBT晶片10、複數個二極體晶片20、控制晶片30、晶片搭載部TAB1~4各者之一部分、晶片搭載部TAB5、複數根金導線40、複數根鋁導線50、複數根引線LD1之一部分(內部)及複數根引線LD2之一部分(內部)係藉由包含樹脂之密封體MR而密封。另,密封體MR具有表面(第3主面)FS6、表面FS6相反側之背面(第3背面)BS6、及位於表面FS6與背面BS6之間之如圖4所示之側面SS1。 且,如圖1、圖2、圖4及圖5所示,作為複數根引線LD1之外部的外引線1a係自靠近密封體MR之晶片搭載部TAB5側之側面SS1分別露出。另一方面,作為複數根引線LD2之外部的外部引線2a自靠近密封體MR之晶片搭載部TAB1~4之側之側面SS1分別露出。又,如圖4所示,複數根外部引線1a、2a分別向密封體MR之表面FS6之方向彎曲。 又,於密封體MR中,自其背面BS6,露出晶片搭載部TAB1~4各者之背面。但,晶片搭載部TAB5之背面BS5不自密封體MR之背面BS6露出。即,僅晶片搭載部TAB5埋入密封體MR之內部。 於本實施形態1之半導體模組SA中,如圖2~圖4所示,絕緣層70接合(貼附)於密封體MR之背面BS6。詳細而言,於密封體MR之背面BS6,以覆蓋於該背面BS6露出之晶片搭載部TAB1~4各者之背面(露出部)之方式接合(貼附)絕緣層70。進而,具有與絕緣層70積層而接合(貼附)之薄膜狀之TIM(Thermal Interface Material、熱傳導材料、熱介面材料)層80。 且,如圖2所示,於半導體模組SA之俯視(背面視)下,TIM層80之區域包含於絕緣層70之區域。即,成為於俯視下之大小為絕緣層70較TIM層80大、且於四邊形之TIM層80之4邊各者,絕緣層70向外推出之構造。絕緣層70與TIM層80之大小・位置之關雖並未圖示,但亦存在TIM層80之區域邊緣連接於絕緣層70之區域邊緣之情形,關於確保於後說明之圖50所示之沿面距離L2之方面,較佳為圖2所示之絕緣層70與TIM層80之大小及位置關係。具體而言,於俯視下,絕緣層70具有於第1方向(x方向)延伸之第1邊71、第1邊71相反側之第2邊72、於與第1方向(x方向)交叉之第2方向(y方向)延伸之第3邊73及第3邊73相反側之第4邊74。又,TIM層80具有沿第1方向(x方向)延伸之第5邊81、第5邊81相反側之第6邊82、於第2方向(y方向)延伸之第7邊83及第7邊83相反側之第8邊84。且,於俯視下,TIM層80之第5邊81位於絕緣層70之第1邊71與絕緣層70之第2邊72之間,TIM層80之第6邊82位於絕緣層70之第2邊72與TIM層80之第5邊81之間。進而,TIM層80之第7邊83位於絕緣層70之第3邊73與絕緣層70之第4邊74之間,TIM層80之第8邊84位於絕緣層70之第4邊74與TIM層80之第7邊83之間,絕緣層70與TIM層80較佳為上述之大小及位置關係。 另,本實施形態1之半導體模組SA係於其組裝中,於藉由樹脂塑模形成密封體MR後,貼附絕緣層70與TIM層80者。 此處,對於TIM層80、絕緣層70及引線框架(參照後述之圖19)90進行說明。首先,TIM層80係具有熱傳導功能之薄膜層。且,經由TIM層80藉由配置於其上下之構件之線膨脹係數差而緩和產生之應力。換言之,TIM層80係柔軟地追隨配置於其上下之構件之熱變形者。進而,亦具備吸收配置於上述上下之構件之接合面之凹凸之功能。TIM層80係例如含有碳粒子之樹脂薄片材料、金屬或含有陶瓷之矽樹脂層或散熱性油脂層等。又,TIM層80之厚度為例如約0.15~0.5 mm。進而,TIM層80之熱傳導率為例如40~90 W/mk。 又,絕緣層70係例如包含陶瓷或絕緣性之樹脂材料之絕緣性樹脂薄片,其厚度為例如85 μm或210 μm。於絕緣層70之厚度為85 μm之情形時,其熱傳導率為例如 3W/mk。進而,於絕緣層70之厚度為210 μm之情形時,其熱傳導率為例如 11W/mk。 又,引線框架90係例如包含銅系合金或鐵系合金等之板材,其厚度為例如0.5 mm。於該情形時,包含晶片搭載部(第1晶片搭載部)TAB1及晶片搭載部(第2晶片搭載部)TAB2之晶片搭載部TAB1~5及引線LD1、LD2之厚度亦為0.5 mm。因此,晶片搭載部TAB1~5各者之厚度為絕緣層70或TIM層80各者之厚度以上。 其次,使用圖5,對於透過本實施形態1之半導體模組SA之密封體MR觀察到之構造進行說明。此處,對於實現3相反相器電路之半導體模組SA之透射構造進行說明。 半導體模組SA係以於x方向並列之方式,排列晶片搭載部TAB1~TAB4,且於該等晶片搭載部TAB1~TAB4之上側(y方向側)配置有晶片搭載部TAB5。且,於晶片搭載部TAB1,搭載形成有對應於U相之高側IGBT之半導體晶片CHP1(IGBT晶片10、HU)、形成有對應於V相之高側IGBT之半導體晶片CHP1(IGBT晶片10、HV)、及形成有對應於W相之高側IGBT之半導體晶片CHP1(IGBT晶片10、HW)。又,於晶片搭載部TAB1,亦搭載分別形成有二極體之半導體晶片CHP2(二極體晶片20、HU)、CHP2(二極體晶片20、HV)、CHP2(二極體晶片20、HW)。 同樣地,於晶片搭載部TAB2,搭載形成有對應於U相之低側IGBT之半導體晶片CHP1(IGBT晶片10、LU)、及形成有二極體之半導體晶片CHP1(二極體晶片20、LU)。又,於晶片搭載部TAB3,搭載形成有對應於V相之低側IGBT之半導體晶片CHP1(IGBT晶片10、LV)、及形成有二極體之半導體晶片CHP2(二極體晶片20、LV)。進而,於晶片搭載部TAB4,搭載形成有對應於W相之低側IGBT之半導體晶片CHP1(IGBT晶片10、LW)、及形成有二極體之半導體晶片CHP2(二極體晶片20、LW)。 另一方面,於連接於導電構件(懸吊引線)HL之晶片搭載部TAB5,搭載由3相反相器電路之閘極控制電路彙集形成之半導體晶片CHP3(控制晶片30)。 於該情形時,半導體晶片CHP3(控制晶片30)與6個IGBT晶片10分別以導線W(金導線40)而電性連接。此時,半導體晶片CHP3配置於6個IGBT晶片10所排列之x方向之中心。換言之,沿密封體MR之長邊(沿如圖5所示之x方向延伸之邊)配置之6個IGBT晶片10中,於沿通過配置於朝向左起第3個之IGBT晶片10與配置於朝向左起第4個IGBT晶片10之間之y方向之假想線(未圖示)上,配置半導體晶片CHP3(控制晶片30)。其結果,以排列於x方向之方式配置之6個IGBT晶片10各者,與配置於x方向之中央部之1個半導體晶片CHP3(控制晶片30)經由金導線40而分別電性連接。藉由如此配置,可將控制晶片30至各IGBT晶片10之閘極配線長設為大致相等距離,而實現提高半導體模組100之可靠性。 又,半導體晶片CHP3(控制晶片30)經由各金導線W(金導線40)與配置於密封體MR之一側面SS1之複數根引線LD1電性連接。又,6個IGBT晶片10各者與6個二極體晶片20各者經由線徑較金導線40更大之鋁導線50而電性連接。進而,6個二極體晶片20各者與配置於密封體MR之另一側面SS1之複數根引線LD2經由鋁導線50而電性連接。 另,搭載半導體晶片CHP3(控制晶片30)之晶片搭載部TAB5係藉由2根懸吊引線HL支持。 其次,使用圖6~圖9,選取本發明人進行比較研究之半導體模組針對本發明之課題之細節進行說明。圖6係顯示本發明人比較研究之半導體模組之構造之俯視圖,圖7係顯示圖6之半導體模組之構造之背面圖,圖8係顯示沿圖6之A-A線切斷之構造之剖視圖,圖9係顯示沿圖6之B-B線切斷之構造之剖視圖。 本發明人對圖6~圖9所示之全模塑模類型之半導體模組100進行研究。全模塑模類型之半導體模組100係所組裝之半導體晶片或晶片搭載部及複數根導線,進而引線之外部以外之部分(內部)由密封體MR覆蓋之構造者。即,係晶片搭載部TAB周圍全部被樹脂覆蓋之構造之半導體模組100。 於上述半導體模組100中,若組裝內置有IGBT或MOSFET等功率系統之電晶體之半導體晶片(IGBT晶片10),則該等半導體晶片成為發熱源。此時,於如圖6~圖9所示之全模塑模類型之半導體模組100中,搭載半導體晶片之晶片搭載部TAB因以不自密封體MR露出之方式由樹脂覆蓋,故自晶片搭載部TAB向封裝(密封體MR)外部之散熱性較差。 於此種構造中,雖認為藉由增大晶片搭載部TAB之熱容量,可改善散熱性,但若是向封裝(密封體MR)外部之散熱性差,則不得不增大半導體晶片。其結果,無法使半導體模組100小型化,無法低成本化。 因此,本發明人為了提高散熱性,而研究使分別供搭載複數個半導體晶片之複數個晶片搭載部TAB各者之背面朝封裝(密封體MR)外部露出之構造。 然而,將使晶片搭載部TAB之背面露出於密封體MR之背面之半導體模組安裝於散熱板(散熱片)之情形,成為將密封體MR之背面側安裝於散熱板之安裝構造。因此,經由本發明人之研究得知,於密封體MR背面露出之複數個晶片搭載部TAB各者之一部分有互相經由散熱板而短路之可能性,或有無法確保露出之晶片搭載部TAB之一部分與散熱板之絕緣耐壓距離之可能性。 其次,就本實施形態1之半導體模組SA之細節進行說明。 首先,對本實施形態1之半導體模組SA中之3相反相器電路之構成例進行說明。圖10係顯示包含圖1之半導體模組中之反相器電路及3相感應馬達之馬達電路之構成之電路圖。 於圖10中,馬達電路具有3相感應馬達MT及反相器電路INV。3相感應馬達MT係構成為藉由相位不同之3相電壓驅動。具體而言,於3相感應馬達MT中,使用相位偏移120度之所謂U相、V相、及W相之3相交流而使導體即轉子RT之周圍產生旋轉磁場。於該情形時,磁場於轉子RT之周圍旋轉。這意味著橫貫導體即轉子RT之磁通產生變化。其結果,會於導體即轉子RT產生電磁感應,且於轉子RT流通感應電流。且,於旋轉磁場中感應電流流通之情形意味著藉由弗萊明之左手定律,對轉子RT施加力,藉由該力而轉子RT旋轉。如此可知,於3相感應馬達MT中,藉由使用3相交流,可使轉子RT旋轉。即,於3相感應馬達MT中,需要3相交流。因此,於馬達電路中,藉由使用從直流產生交流之反相器電路INV,將交流電力供給於感應馬達。且,於本實施形態1中,於1個反相器電路INV產生3種類(U相、V相、W相)之交流電力,供給至3相感應馬達。 以下,對該反相器電路INV之構成例進行說明。如圖10所示,例如,於本實施形態1之反相器電路INV中,對應於3相而設置有IGBTQ1與二極體FWD。即,於本實施形態1之反相器電路INV中,例如,藉由反並聯連接如圖10所示之IGBTQ1與二極體FWD之構成,實現成為反相器電路INV之構成要素之開關元件。 具體而言,第1接腳LG1之上臂及下臂、第2接腳LG2之上臂及下臂、第3接腳LG3之上臂及下臂各者係由反並聯連接IGBTQ1與二極體FWD之構成要素而構成。 換言之,於本實施形態1之反相器電路INV中,IGBTQ1與二極體FWD反並聯連接於正電位端子PT與3相感應馬達MT之各相(U相、V相、W相)之間,且,IGBTQ1與二極體FWD亦反並聯連接於3相感應馬達MT之各相與負電位端子NT之間。即,於每個單相設置有2個IGBTQ1與2個二極體FWD。其結果,於本實施形態1之反相器電路INV,具有合計6個IGBTQ1與6個二極體FWD。且,於每個IGBTQ1之閘極電極,連接有閘極控制電路GCC,藉由該閘極控制電路GCC,控制IGBTQ1之開關動作。於如此構成之反相器電路INV中,藉由以閘極控制電路GCC控制IGBTQ1之開關動作,將直流電力轉換為3相交流電力,且將該3相交流電力供給至3相感應馬達MT。 其次,對二極體之必要性進行說明。 如上所述,於本實施形態1之反相器電路INV,作為開關元件係使用IGBTQ1,但以與該IGBTQ1反並聯連接之方式設置有二極體FWD。僅基於藉由開關元件實現開關功能之觀點,作為開關元件之IGBTQ1雖為必要,但認為並無設置二極體FWD之必要性。關於該點,於連接於反相器電路INV之負荷包含電感之情形時,有必要設置二極體FWD。以下,就該理由進行說明。 於負荷為不包含電感之純電阻之情形時,由於無回流之能量故不需要二極體FWD。但,於連接有於負荷包含如馬達之電感之電路之情形時,經導通之開關處於負荷電流逆向流動之模式。即,於負荷包含電感之情形時,有能源自負荷之電感返回反相器電路INV之情形(有電流逆流之情形)。 此時,由於在IGBTQ1單體中,不具有可流動該回流電流之功能,故必須與IGBTQ1反並聯地連接二極體FWD。即,於反相器電路INV中,如馬達控制般於負荷包含電感之情形時,於已關閉IGBTQ1時,必須釋放出電感所蓄積之能量(1/2LI2
)。然而,於IGBTQ1單體中,無法流通用於釋放電感所蓄積之能量之回流電流。因此,為了回流該電感所蓄積之電能,故與IGBTQ1反並聯地連接二極體FWD。即,二極體FWD具有流通用於釋放電感所蓄積之電能之回流電流之功能。基於以上可知,於連接於包含電感之負荷之反相器電路中,有必要與開關元件即IGBTQ1反並聯地設置二極體FWD。該二極體FWD稱為續流二極體(free wheel diode)。 其次,針對IGBT之構造進行說明。 圖11係顯示於圖1之半導體模組SA中形成IGBT之半導體晶片之外形形狀之俯視圖。 對於構成本實施形態1之反相器電路INV之IGBTQ1與二極體FWD之構造,一邊參照圖式一邊進行說明。於本實施形態1之反相器電路INV,包含有IGBTQ1且包含有二極體FWD。 於圖11中,顯示半導體晶片CHP1之主表面(表面)。如圖11所示,本實施形態1之半導體晶片CHP1之俯視形狀為例如正方形形狀。且,於呈正方形形狀之半導體晶片CHP1之表面,形成射極電極墊EP與閘極電極墊GP。另一方面,雖於圖11並未圖示,但於與半導體晶片CHP1之表面相反側之背面,形成集極電極。 其次,對IGBT之器件構造進行說明。 圖12係顯示圖11之IGBT之器件構造之剖視圖。 於圖12中,IGBTQ1具有形成於半導體晶片背面之集極電極CE,且於該集極電極CE上形成p+
型半導體區域PR1。於p+
型半導體區域PR1上形成n+
型半導體區域NR1,於該n+
型半導體區域NR1上形成n-
型半導體區域NR2。且,於n-
型半導體區域NR2上形成p型半導體區域PR2,且形成貫通該p型半導體區域PR2到達至n-
型半導體區域NR2之溝槽TR。進而,與溝槽TR整合,形成成為射極區域之n+
型半導體區域ER。於該溝槽TR之內部,例如形成有包含氧化矽膜之閘極絕緣膜GOX,經由該閘極絕緣膜GOX形成閘極電極GE。該閘極電極GE係例如由多晶矽膜形成,以嵌埋溝TR之方式形成。又,於圖12中,雖顯示溝槽閘極構造,但並未限定於其,例如,雖未圖示,但亦可為使用形成於矽基板上之平面閘極構造之IGBT。 於如此構成之IGBTQ1中,閘極電極GE係經由圖11所示之閘極電極墊GP與閘極端子GT連接。同樣地,成為射極區域之n+
型半導體區域ER經由射極電極EE(射極電極墊EP),與射極端子ET電性連接。成為集極區域之p+
型半導體區域PR1係與形成於半導體晶片背面之集極電極CE電性連接。 如此構成之IGBTQ1兼備功率MOSFET之高速開關特性及電壓驅動特性與雙極電晶體之低導通電壓特性。 另,n+
型半導體區域NR1被稱為緩衝層。該n+
型半導體區域NR1係用於防止於IGBTQ1關閉時,自p型半導體區域PR2成長於n-
型半導體區域NR2內之耗盡層與形成於n-
型半導體區域NR2之下層之p+
型半導體區域PR1接觸之穿通現象而設置。又,為了限制自p+
型半導體區域PR1向n-
型半導體區域NR2之電洞注入量等之目的,設置有n+
型半導體區域NR1。 其次,對IGBT之動作進行說明。 首先,針對IGBTQ1打開之動作進行說明。於圖12中,藉由於閘極電極GE、成為射極區域之n+
型半導體區域ER之間施加充分之正電壓,而打開呈溝槽閘極構造之MOSFET。於該情形時,構成集極區域之p+
型半導體區域PR1與n-
型半導體區域NR2之間進行順偏壓,且引起自p+
型半導體區域PR1向n-
型半導體區域NR2之電洞注入。接著,僅有與注入之電洞之正電荷相同之電子集中於n-
型半導體區域NR2。藉此,引起n-
型半導體區域NR2之電阻降低(傳導度調變)、IGBTQ1成為打開狀態。 對導通電壓,雖施加p+
型半導體區域PR1與n-
型半導體區域NR2之接合電壓,但由於n-
型半導體區域NR2之電阻值藉由傳導度調變而下降1位數以上,故於如佔導通電阻之大半之高耐壓中,IGBTQ1較功率MOSFET更成為低導通電壓。因此,可知IGBTQ1為對高耐壓化有效之器件。即,於功率MOSFET中,為了謀求高耐壓化而必須增厚成為漂移層之磊晶層之厚度,但於該情形時,導通電阻亦上升。相對於此,於IGBTQ1中,為了謀求高耐壓化,即使增厚n-
型半導體區域NR2之厚度,於IGBTQ1之導通動作時亦會產生傳導度調變。因此,可較功率MOSFET更降低導通電阻。即,根據IGBTQ1,與功率MOSFET比較,即使於謀求高耐壓化之情形時,亦可實現低導通電阻之器件。 接著,對IGBTQ1關閉之動作進行說明。若使閘極電極GE、與成為射極區域之n+
型半導體區域ER之間之電壓下降,則呈溝槽閘極構造之MOSFET關閉。於該情形時,自p+
型半導體區域PR1向n-
型半導體區域NR2之電洞注入停止,已經注入之電洞壽命亦隨之減少。剩餘之電洞向射極電極EE側直接流出(拖尾電流),於流出完成之時點,IGBTQ1為斷開狀態。如此,可使IGBTQ1進行導通/斷開動作。 其次,對二極體之構造進行說明。 圖13係顯示於圖1之半導體模組中形成二極體之半導體晶片之外形形狀之俯視圖。 於圖13中,顯示半導體晶片CHP2之主表面(表面)。如圖13所示,本實施形態1之半導體晶片CHP2之俯視形狀為正方形形狀。且,於呈正方形形狀之半導體晶片CHP2之表面形成有陽極電極墊ADP。另一方面,雖未圖示,但遍及半導體晶片CHP2之與表面相反側之背面整體,形成陰極電極墊。 接著,對二極體FWD之器件構造進行說明。圖14係顯示圖13之二極體FWD之器件構造之剖視圖。於圖14中,於半導體晶片之背面,形成陰極電極CDE,於該陰極電極CDE上形成n+
型半導體區域NR3。且,於n+
型半導體區域NR3上形成n-
型半導體區域NR4,於n-
型半導體區域NR4上,形成p型半導體區域PR3。於p型半導體區域PR3與p-
型半導體區域PR4上,形成陽極電極ADE(陽極電極墊ADP)。陽極電極ADE例如由鋁-矽構成。 其次,對二極體之動作進行說明。 根據如此構成之二極體FWD,若對陽極電極ADE施加正電壓,對陰極電極CDE施加負電壓,則n-
型半導體區域NR4與p型半導體區域PR3之間之pn接合進行順偏壓,電流流動。另一方面,對陽極電極ADE施加負電壓,對陰極電極CDE施加負電壓,則n-
型半導體區域NR4與p型半導體區域PR3之間之pn接合進行逆偏壓,未流動電流。如此,可使具有整流功能之二極體FWD動作。 其次,對閘極控制電路之構成進行說明。 圖15係顯示圖1之半導體模組中之閘極控制電路之電路方塊構成之圖。於圖15中,舉出驅動3相感應馬達MT之反相器電路INV之3相中之1相為例,對控制該1相之閘極控制電路GCC之構成進行說明。於圖15中,於與高壓電源(600V)電性連接之端子VCC及與接地電性連接之端子COM之間,例如,構成反相器電路INV之1相量之高側IGBT(HQ1)與低側IGBT(LQ1)串聯連接。且,高側IGBT(HQ1)與低側IGBT(LQ1)之間之中間節點經由端子VS與3相感應馬達MT電性連接。 此處,閘極控制電路GCC構成為控制高側IGBT(HQ1)之導通/斷開動作與低側IGBT(LQ1)之導通/斷開動作。例如,閘極控制電路GCC藉由控制施加於高側IGBT(HQ1)之閘極電極之閘極電壓,實現高側IGBT(HQ1)之導通/斷開動作,且藉由控制施加於低側IGBT(LQ1)之閘極電極,實現低側IGBT(LQ1)之導通/斷開動作。 具體而言,閘極控制電路GCC和與低壓電源電性連接之端子VDD及與接地電性連接之端子Vss連接。且,閘極控制電路GCC具有將自反相器電路INV之端子HIN及端子LIN輸入之輸入信號予以處理之輸入信號處理電路ISC、位準移位電路LSC、低側驅動電路LDC及高側驅動電路HDC。 且,低側驅動電路LDC基於自輸入信號處理電路ISC輸出之處理信號,控制施加於對低側IGBT(LQ1)之閘極電極之閘極電壓。例如,低側驅動電路LDC自端子Vss輸入GND電位(接地電位),將以該GND電位為基準產生之閘極電壓供給至低側IGBT(LQ1)之閘極電極。此處,於供給至閘極電極之閘極電壓相對於GND電位為臨界值電壓以上之情形時,低側IGBT(LQ1)導通,另一方面,於供給至閘極電極之閘極電壓相對於GND電位未達到臨界值電壓之情形時,低側IGBT(LQ1)斷開。如此,低側IGBT(LQ1)之導通/斷開動作藉由低側驅動電路LDC控制。 另一方面,高側驅 動電路HDC於將輸入信號處理電路ISC之處理信號輸入至位準移位電路LSC後,基於自該位準移位電路LSC之輸入信號,控制施加於高側IGBT(HQ1)之閘極電極之閘極電壓。例如,高側驅動電路HDC自端子Vs輸入成為基準之基準電位。即,即使為高側驅動電路HDC,亦必須產生施加於高側IGBT(HQ1)之閘極電極的閘極電壓,但於產生該閘極電壓時,基準電位成為必要。關於該點,例如,考慮將自於低側驅動電路LDC中使用之端子Vss輸入之GND電位於高側驅動電路HDC中使用,但於高側驅動電路HDC中,無法將自端子Vss輸入之GND電位作為基準電位而使用。即,於圖15中,低側IGBT(LQ1)藉由對低側IGBT(LQ1)之射極電位,施加臨界值以上之閘極電壓,可使低側IGBT(LQ1)導通。因此,低側IGBT(LQ1)之閘極電壓係以低側IGBT(LQ1)之射極電位為基準而產生。此時,低側IGBT(LQ1)之射極電位由於與GND電位為相同電位,故低側IGBT(LQ1)之閘極電壓可將自端子Vss輸入之GND電位作為基準電壓而產生。 相對於此,如圖15所示,即使為高側IGBT(HQ1),亦將高側IGBT(HQ1)之射極電位使用為基準電位,但該高側IGBT(HQ1)之射極電位係自GND電位至電源電位之間變動。即,於低側IGBT(LQ1)導通之情形時,高側IGBT(HQ1)之射極電位與GND電位成為相同電位。相對於此,於高側IGBT(HQ1)導通之情形時,高側IGBT(HQ1)之射極電位與電源電位成為相同電位。於此種情形時,意味著為了使高側IGBT(HQ1)導通,必須以電源電位為基準產生閘極電壓,因此,以自端子Vss輸入之GND電位為基準,無法產生施加於高側IGBT(HQ1)之閘極電極之閘極電壓。 由此,於高側驅動電路HDC中,自端子Vs輸入高側IGBT(HQ1)之射極電位,以自該端子Vs輸入之電位為基準,產生施加於高側IGBT(HQ1)之閘極電極之閘極電壓。因此,自端子Vs輸入之電位由於變動至電源電位,故以自該端子Vs輸入之電位為基準產生之高側IGBT(HQ1)之閘極電壓必須設成較電源電位更高之電位。由此,於高側驅動電路HDC中,例如,將端子VB與位於反相器電路INV外部之低壓電源LPS(15V)連接,藉由使用自該端子VB輸入之電位與自上述之端子Vs輸入之電位,產生較電源電位更高之閘極電壓。該閘極電壓係自高側驅動電路HDC供給至高側IGBT(HQ1)之閘極電極。如以上,於供給至閘極電極之閘極電壓相對於基準電位為臨界值以上之情形時,高側IGBT(HQ1)導通,另一方面,於供給至閘極電極之閘極電壓相對於基準電位未達臨界值之情形時,高側IGBT(HQ1)斷開。如此,高側IGBT(HQ1)之導通/斷開動作藉由高側驅動電路HDC控制。 其次,對具體化閘極控制電路之半導體晶片之構成進行說明。 上述之閘極控制電路GCC例如可藉由已形成積體電路之半導體晶片實現,但於已具體化閘極控制電路GCC之半導體晶片,有如以下所示之特徵點。即,閘極控制電路GCC之構成要素即輸入信號處理電路ISC或位準移位電路LSC或低側驅動電路LDC因以自端子Vss供給之GND電位為基準而設計電路,故可內置於半導體基板。相對於此,高側驅動電路HDC由於以變動至自端子Vs供給之電源電位的電位為基準而設計電路,故必須與半導體基板(端子Vss)分離而形成。具體而言,高側驅動電路HDC採用高耐壓之浮動構造,使用與低側驅動電路LDC獨立之「浮島構造」。而且,該「浮島構造」於與低側驅動電路LDC之信號交換上有限制,只能通過位準移位電路LSC交接脈衝信號。由此,高側驅動電路HDC所必需之墊必須形成「浮島構造」。如以上,於形成閘極控制電路GCC之半導體晶片,形成「浮島構造」。 其次,對本實施形態1之半導體模組SA之電路方塊構成進行說明。圖16係顯示圖1之半導體模組中之電路方塊構成之圖,且係實現圖10所示之反相器電路INV之電路方塊構成。於圖16中,本實施形態1中之半導體模組SA具有6個IGBT、6個二極體及閘極控制電路GCC,且具備25個外部端子。編號1與編號13~17與編號25之端子為非連接之端子NC。又,編號2~4之端子為與閘極控制電路GCC連接之端子VB1~VB3,編號5~7之端子為將輸入信號輸入至閘極控制電路GCC之端子HIN1~HIN3。進而,編號8之端子為將低壓電源供給至閘極控制電路GCC之端子VDD,編號9之端子為將接地電位供給至閘極控制電路GCC之端子Vss。又,編號10~12之端子為將輸入信號輸入至閘極控制電路GCC之端子LIN1~LIN3。另一方面,編號18之端子係與接地電位連接之端子NW(端子COM),編號19之端子亦為與接地電位連接之端子NV(端子COM),編號20之端子亦為與接地電位連接之端子NU(端子COM)。又,編號21之端子係與3相馬達之W相連接之端子W(端子Vs3),編號22之端子係與3相馬達之V相連接之端子V(端子Vs2),編號23之端子係與3相馬達之U相連接之端子U(端子Vs1)。進而,編號24之端子係與高壓電源連接之端子P(端子VCC)。 圖17係顯示圖16所示之閘極控制電路GCC之內部方塊構成之圖。如圖17所示,閘極控制電路GCC係圖15所示之單位方塊構成與U相、V相、及W相之各相對應而設置。此時,於圖17中,對如圖15所示之單位方塊構成所示之符號之末尾標註「1」者與U相對應,對圖15所示之單位方塊構成所示之符號之末尾標註「2」者與V相對應,對圖15所示之單位方塊構成所示之符號之末尾標註「3」者與W相對應。 其次,對具體化本實施形態1之半導體模組SA之閘極控制電路之半導體晶片之構成進行說明。 圖18係顯示具體化圖17所示之閘極控制電路GCC之半導體晶片CHP3之構成的模式圖。如圖18所示,於半導體晶片CHP3,形成:形成有對應於U相之高側驅動電路HDC1之「浮島構造」,形成有對應於V相之高側驅動電路HDC2之「浮島構造」,與形成有對應於W相之高側驅動電路HDC2之「浮島構造」。此時,於本實施形態1之半導體晶片CHP3中,3個「浮島構造」係以於y方向排列之方式佈局配置。且,於「浮島構造」以外之區域,形成低側驅動電路LDC1~3、位準移位電路LSC1~3、輸入信號處理電路ISC1~3。 根據如此構成之本實施形態1之半導體晶片CHP3,由於可將構成3相反相器電路之閘極控制電路GCC彙集於1個半導體晶片CHP3上,故可獲得能夠減少構成3相反相器電路之半導體模組SA之製造成本之優點。進而,由於無需考慮晶片間之性能偏差,故藉由使用本實施形態1之半導體晶片CHP3,可謀求閘極控制電路GCC之IGBT之控制性提高。 <半導體模組之製造方法> 1.引線框架準備 圖19係顯示圖1所示之半導體模組之組裝所用之引線框架之構造的俯視圖,圖20係顯示沿圖19之A-A線切斷之構造之剖視圖,圖21係顯示沿著圖19之B-B線切斷之構造之剖視圖。 首先,準備如圖19所示之引線框架90。於引線框架整體,雖形成複數個可形成圖1所示之1個半導體模組SA之製品形成區域90a,但於本實施形態1中,僅選取1個製品形成區域90a作為代表進行說明。於該製品形成區域90a,設置有晶片搭載部TAB1~5、配置於晶片搭載部TAB5周圍之複數根引線LD1、配置於晶片搭載部TAB1~4附近之複數根引線LD2,及支持晶片搭載部TAB5之2根懸吊引線HL。且,複數根引線LD1、LD2及2根懸吊引線HL與框部90b相連。 另,晶片搭載部TAB1~4係如圖20所示,分別具有供搭載半導體晶片之面即表面(第1主表面)FS3或FS4,及該等之相反側之面即背面(第2主表面)BS3或BS4等。又,晶片搭載部TAB1~4係分別為相同高度。另一方面,如圖21所示,晶片搭載部TAB5具有供搭載半導體晶片之面即表面(第3主表面)FS5及其相反側之面即背面(第4主表面)BS5。另,如圖20、圖21所示,晶片搭載部TAB5與晶片搭載部TAB1~4為不同高度。具體而言,晶片搭載部TAB5係配置於較晶片搭載部TAB1~4更高之位置。 此處,引線框架90係例如由以銅(Cu)為主成分之基材形成,圖19所示之引線圖形係藉由蝕刻加工或壓製加工等而形成者。 2.晶片接合 圖22係顯示於圖1所示之半導體模組之組裝中IGBT晶片與二極體晶片之晶片接合完成時之構造之俯視圖;圖23係顯示沿圖22之A-A線切斷之構造之剖視圖;圖24係顯示沿圖22之B-B線切斷之構造之剖視圖,圖25係顯示於圖1所示之半導體模組之組裝中控制晶片之晶片接合完成時之構造之俯視圖。 首先,準備如圖11所示之IGBT晶片10、如圖13所示之二極體晶片20、如圖18所示之控制晶片30。另,例如,搭載於晶片搭載部TAB1上之第1半導體晶片為IGBT晶片10。且,該IGBT晶片10內置功率電晶體,且於圖3所示之表面(第1面)FS1形成與功率電晶體之射極電極(第1電極)電性連接之射極端子(第1端子)EP。進而,於表面FS1,形成與功率電晶體之閘極電極電性連接之閘極端子GP。另一方面,雖未圖示,但於位於表面FS1之相反側的背面(第2面)BS1,形成集極端子(第2端子)。集極端子電性連接於功率電晶體之集極電極(第2電極)。 又,例如,搭載於晶片搭載部TAB2上之第2半導體晶片亦同樣為IGBT晶片10。且,該IGBT晶片(第2半導體晶片)10亦內置功率電晶體,於表面(第1面)FS2形成與功率電晶體之射極電極(第3電極)電性連接之射極端子(第3端子)EP。進而,於表面FS2,形成與功率電晶體之閘極電極電性連接之閘極端子GP。另一方面,同樣地,雖未圖示,但於位於表面FS2之相反側的背面(第2面)BS2,形成集極端子(第4端子)。集極端子電性連接於功率電晶體之集極電極(第4電極)。 又,二極體晶片20係如圖13所示,於其表面形成陽極端子ADP。另一方面,雖未圖示,但於位於表面之相反側的背面,形成陰極端子。 且,於準備好圖22所示之引線框架90之後,進行晶片接合。於本實施形態1中,作為固黏各半導體晶片之晶片接合材料(如圖3所示之導電性接合材60),例如使用銀漿等。 首先,如圖22~圖24所示,於引線框架90之晶片搭載部TAB1經由上述導電性之接合材60搭載3個IGBT晶片10,進而,於晶片搭載部TAB2~4各者,同樣地,分別經由導電性接合材60逐個搭載IGBT晶片10。 其次,同樣地,於晶片搭載部TAB1經由導電性接合材60搭載3個二極體晶片20,進而,於晶片搭載部TAB2~4各者,分別經由導電性接合材60逐個搭載二極體晶片20。 於搭載IGBT晶片10及二極體晶片20之後,如圖25所示,於引線框架90之晶片搭載部TAB5搭載控制晶片30。另,控制晶片30經由圖4所示之非導電性接合材65而搭載於晶片搭載部TAB5。 又,IGBT晶片10、二極體晶片20及控制晶片30係例如分別施加熱與荷重而晶片接合。 3.導線接合 圖26係顯示於圖1所示之半導體模組之組裝中鋁導線之導線接合完成時之構造之俯視圖,圖27係顯示於圖1所示之半導體模組之組裝中金導線之導線接合完成時之構造之俯視圖。 於晶片接合後,如圖26及圖27所示,進行導線接合。首先,如圖26所示,使用鋁導線50電性連接IGBT晶片10與二極體晶片20,進而經由鋁導線50與相連於晶片搭載部之引線LD2(圖26中、配置於下邊側之引線LD2之內部)電性連接。或者,使用鋁導線50電性連接IGBT晶片10與二極體晶片20,進而經由鋁導線50而與未與晶片搭載部相連之單獨之引線LD2之內部電性連接。另,鋁導線50係以鋁(Al)為主成分之導電性構件。 完成使用鋁導線50之IGBT晶片10與二極體晶片20與引線LD2之接合之後,如圖27所示,進行使用較鋁導線50線徑更小(更細)之金導線40之導線接合。首先,使用金導線40,電性連接IGBT晶片10各者與控制電極30。進而,使用相同之金導線40,電性連接控制晶片30與引線LD1(圖27中,配置於上邊側之引線LD1之內部)。另,金導線40係以金(Au)為主成分之導電性構件。 4.密封樹脂(樹脂塑模) 圖28係顯示於圖1所示之半導體模組之組裝中,將導線接合完成之引線框架配置於塑模模具之模腔內之構造沿圖22之A-A線切斷之構造之剖視圖。又,圖29係顯示於圖1所示之半導體模組之組裝中,將導線接合完成之引線框架配置於塑模模具之模腔內之構造沿圖22之B-B線切斷之構造之剖視圖,圖30係顯示於圖28所示之構造中將樹脂開始注入於模腔內之狀態之剖視圖。進而,圖31係顯示於圖29所示之構造中將樹脂開始注入模腔內之狀態之剖視圖,圖32係顯示於圖28所示之構造中完成向模腔內注入樹脂之狀態之剖視圖,圖33係顯示於圖29所示之構造中完成向模腔內注入樹脂之狀態之剖視圖。又,圖34係顯示將完成塑模之引線框架自塑模模具中取出之構造的俯視圖,圖35係顯示沿圖34之A-A線切斷之構造之剖視圖,圖36係顯示沿圖34之B-B線切斷之構造之剖視圖。 導線接合後,進行樹脂密封。此處,藉由密封體MR覆蓋複數個IGBT晶片10、複數個二極體晶片20、控制晶片30、複數個晶片搭載部TAB1~4之一部分、晶片搭載部TAB5、複數根金導線40、複數根鋁導線50、複數根引線LD1之內部、及複數根引線LD2之內部。此時,以自具有表面(第1面)FS6及其相反側之背面(第2面)BS6之密封體MR之背面BS6露出複數個晶片搭載部TAB1~4各者之背面(第2面)之方式,使用圖30所示之密封樹脂120進行密封(形成密封體MR)。 首先,如圖28所示,將具有複數個製品形成區域90a(參照圖19)之引線框架90收納於包含上模具110a與下模具110b之塑模模具110之下模具110b之模腔110c。 於收納後,關閉上模具110a與下模具110b,如圖29所示,以上模具110a與下模具110b夾入引線框架90。此時,如圖28及圖29所示,使晶片搭載部TAB1~4各者之背面(背面BS3及背面BS4等)密接於下模具110b之模腔110c之底面110d。另一方面,晶片搭載部TAB5係如圖29所示,成為自模腔110c之底面110d懸空(分離)之狀態。 如此,以使晶片搭載部TAB1~4各者之背面密接於下模具110b之模腔110c之底面110d之狀態,如圖30所示,自塑模模具110之澆口110e(參照圖28)注入密封樹脂120。如圖30及圖31所示,於模腔110c中,即使開始朝向通氣孔110f填充密封樹脂120,由於晶片搭載部TAB1~4各者之背面仍密接於下模具110b之模腔110c之底面110d,故密封樹脂120不會被帶入晶片搭載部TAB1~4與模腔110c之底面110d之間。 於該狀態下,如圖32及圖33所示,完成向密封樹脂120之模腔110c之填充。另,密封樹脂120係例如環氧系樹脂等熱塑性樹脂。 此處,例如若以將絕緣層70與TIM層80貼附於自密封體MR露出之晶片搭載部TAB1~4各者之背面之狀態進行樹脂塑模,則會因塑模模具110之熱,使得絕緣層70及TIM層80劣化,而無法組裝所需品質之半導體模組SA。 因此,於本實施形態1之半導體模組SA之組裝中,於進行形成密封體MR之樹脂塑模時,不將絕緣層70與TIM層80配置於塑模模具110而進行樹脂塑模。即,於本實施形態1之半導體模組SA之組裝中,絕緣層70與TIM層80係於樹脂塑模完成後貼附(接合)於密封體MR之背面BS6。如此,藉由於樹脂塑模完成後將絕緣層70與TIM層80貼附於密封體MR之背面BS6,可防止因塑模模具110之熱導致之絕緣層70及TIM層80劣化,於半導體模組SA之組裝中,可獲得所需之品質。 於塑模完成後,如圖34所示,自圖33之塑模模具110取出引線框架90。於引線框架90之製品形成區域90a(參照圖19)形成密封體MR。且,如圖35及圖36所示,密封體MR之背面BS6成為晶片搭載部TAB1~4之背面(背面BS3或背面BS3等) 露出之構造。 5.鍍覆形成 圖37係顯示於圖1所示之半導體模組之組裝中鍍覆形成後之構造之俯視圖,圖38係顯示沿圖37之A-A線切斷之構造之剖視圖,圖39係顯示沿圖37之B-B線切斷之構造之剖視圖。 於樹脂密封後,進行鍍覆形成。 於鍍覆形成步驟中,如圖37所示,自密封體MR露出之各引線之外引線(外部端子)1a、2a或框部90b、進而如圖38及圖39所示,於包含自相同之密封體MR之背面BS6(第2面)露出之晶片搭載部TAB1~4之背面BS3、4(第2面)各者之背面,形成金屬膜即鍍覆膜130作為外裝鍍覆。 6.引線切斷、成形 圖40係顯示於圖1所示之半導體模組之組裝中引線切斷、成形後之構造之俯視圖,圖41係顯示圖40之半導體模組之構造之背面圖,圖42係顯示沿圖40之A-A線切斷之構造之剖視圖,圖43係顯示沿圖40之B-B線切斷之構造之剖視圖。 於鍍覆形成後,進行引線切斷、成形。 於引線切斷、成形步驟中,如圖40、圖41所示,自圖19所示之引線框架90之框部90b切斷圖1所示之半導體模組SA而單片化(切斷),且如圖42、圖43所示,彎曲成形各外引線(外部端子)1a、2a。此時,各外引線1a、2a向與晶片搭載部TAB1~4之露出側相反側(密封體MR之表面FS6側)彎曲成形。 7.絕緣層、TIM層貼附 圖44係顯示圖1所示之半導體模組之組裝中絕緣層及TIM層貼附後之構造之背面圖,圖45係顯示沿圖44之A-A線切斷之構造之剖視圖,圖46係顯示沿圖44之B-B線切斷之構造之剖視圖。 引線切斷、成形後,進行絕緣層、TIM層貼附。 於上述引線切斷、成形後,首先,於密封體MR之背面(第2面)BS6,以覆蓋包含晶片搭載部TAB1之背面(第2面)BS3與晶片搭載部TAB2之背面(第2面)BS4之晶片搭載部1~4之各背面之方式,貼附絕緣層70。絕緣層70係例如陶瓷或包含絕緣性樹脂材料之絕緣性樹脂薄片,以熱壓接貼附於密封體MR之背面BS6。 此處,絕緣層70具有晶片搭載部TAB1之背面BS3、晶片搭載部TAB2之背面BS4、密封體MR之背面BS6、及各對向之表面(第1面)70a及表面70a相反側之背面(第2面)70b。因此,此處,將絕緣層70之表面70a以覆蓋露出於該背面BS6之晶片搭載部TAB1~4之各背面之方式貼附於密封體MR之背面BS6。 將絕緣層70貼附於密封體MR後,將TIM層(熱傳導材料層)80貼附於絕緣層70。換言之,將TIM層80與絕緣層70積層而接合。另,TIM層80係例如為含有碳粒子之樹脂薄片材、含有金屬或陶瓷之聚矽氧樹脂層或散熱性油脂層等。 又,如圖44所示,於俯視下(背面視),TIM層80之區域包含於絕緣層70之區域。即,於俯視下之TIM層80的大小小於絕緣層70之大小,TIM層80之端部(外周部)位於較絕緣層70之外周部更進入內側之位置。換言之,成為於四邊形之TIM層80之4邊各者,絕緣層70向外推之構造。其結果,藉由絕緣層70,可確保TIM層80與(具有電位之)露出之晶片搭載部TAB1~4之絕緣耐壓(詳細係於後述之圖50進行說明)。 又,如圖45、圖46所示,第1半導體晶片與上述第2半導體晶片即複數個IGBT晶片10或複數個二極體晶片20各者位於TIM層80之區域之內側。 進而,於圖44所示之俯視下,密封體MR係分別具有自如圖45所示之密封體MR之表面(第1面)FS6貫通至背面(第2面)BS6之貫通孔(第1貫通孔)MR1及貫通孔(第2貫通孔)MR2。貫通孔MR1與貫通孔MR2位於與密封體MR之長方形之背面(第2面)BS6之對向2個短邊各者之中央部。且,於半導體模組SA之組裝中,以絕緣層70及TIM層80位於貫通孔MR1與貫通孔MR2之間之方式貼附(接合)絕緣層70與TIM層80。 另,於本實施形態1之半導體模組SA之組裝中,於藉由樹脂塑模形成密封體MR後,且於將絕緣層70貼附於密封體MR之前,較佳為將自密封體MR露出之複數根引線各者之外引線(一部分)1a、2a切斷、成形。即,藉由樹脂塑模形成密封體MR後,進而切斷、成形各外引線1a、2a之後,較佳為將絕緣層70與TIM層80貼附於密封體MR。 如此,於各外引線1a、2a之切斷、成形後,藉由設為將絕緣層70與TIM層80貼附於密封體MR之組裝,於出貨後,亦可由顧客端(用戶)貼附絕緣層70與TIM層80。藉此,可增加半導體模組SA之組裝步驟之變化。 但是,絕緣層70與TIM層80之貼附如果在樹脂塑模後,則無論哪個時機均可,例如,亦可於鍍覆形成步驟等之後。 藉由以上,完成如圖1所示之半導體模組SA之組裝。 接著,針對本實施形態1之半導體模組SA之安裝構造進行說明。圖47係顯示將圖44所示之半導體模組安裝於散熱板之構造沿著圖44之A-A線切斷之剖面構造之剖面圖,圖48係顯示將圖44所示之半導體模組安裝於散熱板之構造沿圖44之B-B線切斷之構造之剖視圖。又,圖49係顯示本發明人比較研究之半導體模組之構造之部分剖視圖,圖50係顯示本實施形態1之半導體模組之構造之部分剖視圖。 如圖47所示,半導體模組SA由於具有複數個功率電晶體,故於其動作時之發熱較大。因此,如圖47所示,於PCB(Printed Circuit Board,印刷電路板)基板160等之安裝基板安裝安裝半導體模組SA時,於半導體模組SA安裝散熱板140。換言之,將半導體模組SA安裝於散熱板140。此時,如圖47、圖48所示,於圖44之貫通孔MR1與貫通孔MR2各者安裝螺栓構件150,藉由螺栓構件150接合密封體MR與散熱板140。即,以螺栓構件150之固結將半導體模組SA之密封體MR安裝於散熱板140。 藉此,若晶片搭載部TAB1~4之任何露出部分與散熱板140之距離過近,則無法確保半導體模組SA與散熱板140之絕緣耐壓。係圖49所示之本案發明人進行比較檢討之構造,且係貼附於密封體MR之背面BS6之絕緣層70與TIM層80之大小大致相同之情形。圖49所示之構造中,例如,晶片搭載部TAB之邊緣部與散熱板140之沿面距離L1較短。 另一方面,於圖50所示之本實施形態1之半導體模組SA之構造中,絕緣層70覆蓋晶片搭載部TAB1(此處雖僅圖示晶片搭載部TAB1,但包含晶片搭載部TAB1~4)之方式貼附於密封體MR之背面BS6,且TIM層80之大小小於絕緣層70之大小(絕緣層70之大小>TIM層80之大小)。藉此,晶體搭載部TAB1之邊緣部與散熱板140之沿面距離L2與圖49之構造之沿面距離L1相比遠遠較長(L2>L1)。 即,設為絕緣層70之大小>TIM層80之大小,且,於俯視下,自四邊形之TIM層80之所有邊絕緣層70向外推之方式貼附絕緣層70與TIM層80,藉此可增長晶片搭載部TAB1之邊緣部與放熱板140之沿面距離L2,可使半導體模組SA與散熱板140之絕緣耐壓量增加。其結果,可確保半導體模組SA之絕緣耐壓。 其次,針對本實施形態1之半導體模組SA中之模組尺寸與絕緣層與TIM層之大小之關係說明具體例。圖51係顯示於本實施形態1之半導體模組之背面側之構造中晶片搭載部之露出部之各部尺寸之一例之背面圖,圖52係顯示本實施形態1之半導體模組之背面側之構造之背面圖。 圖51所示之半導體模組SA係顯示其背面視下之各尺寸之一例者,密封體MR之背面BS6之俯視大小例如為橫長P=38.0 mm,縱長Q=24.0 mm。又,自密封體MR之貫通孔MR1到貫通孔MR2之距離為例如T=31.8 mm。進而,晶片搭載部TAB1~4全體之露出部之大小為例如S=29.9 mm、R=10.4 mm。但是,該等尺寸係一例,當然不限定於上述數值。 圖52係顯示對於圖51之背面構造之絕緣層70與TIM層80各者之大小與貼附位置。如圖52所示,於本實施形態1之半導體模組SA中,將絕緣層70之大小設成絕緣層70之大小≧晶片搭載部TAB1~4之露出部之大小。即,絕緣層70與晶片搭載部TAB1~4之露出部之大小相同尺寸,或大於晶片搭載部TAB1~4之露出部之大小。 藉由將絕緣層70之大小設為絕緣層70之大小≧晶片搭載部TAB1~4之露出部大小,可設為考慮到絕緣層70貼附時之位置偏移之大小(可增大對於位置偏移之容限)。 又,絕緣層70之大小成為絕緣層70之大小>TIM層80之大小。藉此,如圖50之構造所示,可將半導體模組SA安裝於散熱板140時之晶片搭載部TAB1之邊緣部與散熱板140之沿面距離L2增長,可確保絕緣耐壓。 其次,針對本實施形態1之變化例之半導體模組SA之絕緣層70與TIM層80各者之最小大小進行說明。 圖53係顯示本實施形態1之變化例之半導體模組之背面側之構造中晶片搭載部之露出構造之背面圖,圖54係顯示本實施形態1之變化例之半導體模組之背面側之構造之背面圖。 半導體模組SA之絕緣層70由於以絕緣為目的,故必須至少覆蓋晶片搭載部TAB1~4之露出部(圖53所示之區域U1)。即,絕緣層70之最小尺寸與晶片搭載部TAB1~4之露出部(區域U1)之尺寸相同(絕緣層70之最小尺寸=晶片搭載部之露出部之尺寸)。因此,如圖54所示,至少將絕緣層70貼附於對應於圖53之區域U1之區域。 另一方面,TIM層80係以散熱為目的。藉此,TIM層80之最小尺寸係至少覆蓋發熱體(例如,IGBT晶片10)之區域。即,TIM層80之最小尺寸係與圖53所示之區域V1之尺寸相同(TIM層80之最小尺寸=晶片全體區域之尺寸)。因此,如圖54所示,至少將TIM層80貼附於對應於圖53之區域V1之區域。 另,藉由縮小絕緣層70及TIM層80之大小,可謀求半導體模組SA之組裝中之構件成本之削減化。 又,於「絕緣層70之大小>TIM層80之大小」且「於俯視下,TIM層80之區域包含於絕緣層70之區域」之情形時,雖未圖示,但亦存在TIM層80之區域邊緣連接於絕緣層70之區域邊緣之情形。然而,就確保沿面距離L2而言,較佳為如圖52、圖54所示之絕緣層70與TIM層80之大小、位置關係。具體而言,於俯視下,絕緣層70具有於第1方向(x方向)延伸之第1邊71、第1邊71相反側之第2邊72、於與第1方向(x方向)交叉之第2方向(y方向)延伸之第3邊73及第3邊73相反側之第4邊74。又,TIM層80具有於第1方向(x方向)延伸之第5邊81、第5邊81相反側之第6邊82、於第2方向(y方向)延伸之第7邊83及第7邊83相反側之第8邊84。且,於俯視下,TIM層80之第5邊81位於絕緣層70之第1邊71與絕緣層70之第2邊72之間,TIM層80之第6邊82位於絕緣層70之第2邊72與TIM層80之第5邊81之間。進而,TIM層80之第7邊83位於絕緣層70之第3邊73與絕緣層70之第4邊74之間,TIM層80之第8邊84位於絕緣層70之第4邊74與TIM層80之第7邊83之間,絕緣層70與TIM層80較佳為上述大小、位置關係。即,最佳為「絕緣層70之大小>TIM層80之大小」且「於俯視下,TIM層80之區域包含於絕緣層70之區域內」且「於俯視下,TIM層80之區域邊緣較絕緣層70之區域邊緣更自內側遠離而配置」。 另,於本實施形態1中,如圖52、圖54所示,TIM層80之俯視形狀與絕緣層70之俯視形狀各者雖以大致長方形記載,但TIM層80之俯視形狀與絕緣層70之俯視形狀各者並未限定於此,可為大致圓形,亦可為大致多邊形。 <效果> 根據本實施形態1之半導體模組SA,由於可自晶片搭載部TAB1~4經由絕緣層70及TIM層80直接將熱傳達至散熱板140等,故可提高半導體模組SA之散熱性。藉此,可提高半導體模組SA之可靠性(性能)。 又,以TIM層80包含於絕緣層70之方式,即,藉由使TIM層80小於絕緣層70,可提高半導體模組SA之密封體MR與散熱板140之絕緣性。即,可確保半導體模組SA之絕緣耐壓,其結果,可提高半導體模組SA之可靠性。 進而,藉由以TIM層80包含於絕緣層70之方式貼附,可防止於安裝於散熱板140等之時之晶片搭載部TAB1~4間之短路產生。 又,藉由將TIM層80貼附於與發熱體(例如,IGBT晶片10)之區域對應之區域,可提高半導體模組SA之散熱性。 又,於半導體模組SA之組裝中,於樹脂塑模後,藉由將絕緣層70及TIM層80貼附於密封體MR之背面BS6,與露出陶瓷板或金屬基板之構造之半導體模組相比,可降低零件成本。其結果,可謀求半導體模組SA之組裝成本之降低化。 以上,雖基於實施形態具體說明由本發明人完成之發明,但本發明並非限定於至此所記載之實施形態者,當然可於不脫離其主旨之範圍內進行各種變更。 (實施形態2) 圖55係顯示本實施形態2之半導體模組之背面側構造中晶片搭載部之露出構造之背面圖,圖56係顯示本實施形態2之半導體模組之背面側之構造之背面圖。 如圖55所示,於半導體模組SA中,搭載有控制IGBT晶片10之控制晶片30。此時,控制晶片30因靠近IGBT晶片10等發熱體而搭載,故容易受到熱之影響。因此,絕緣層70係以覆蓋包含控制晶片30用之晶片搭載部TAB5之所有晶片搭載部TAB1~5之區域W1之方式,又,TIM層80係以覆蓋所有半導體晶片之區域W2之方式,分別如圖56所示,將絕緣層70及TIM層80貼附於對應之區域。藉此,於如圖56所示之構造中,於透射俯視下,控制晶片30位於絕緣層70之區域與TIM層80之區域。 藉由以覆蓋所有半導體晶片之區域W2之方式貼附TIM層80,可緩和熱對控制晶片30之影響。 另,即使於如圖56所示之構造中,亦滿足絕緣層70之尺寸>TIM層80之尺寸、絕緣層70之尺寸≧晶片搭載部之露出部尺寸、及TIM層80之尺寸≧所有半導體晶片之區域。 又,於半導體模組SA中,因圖47所示藉由螺栓構件150固定於散熱板140,故會擔心封裝裂痕等之固定時之損傷。因此,於本實施形態2之圖56所示之構造中,於俯視下(背面視),絕緣層70與TIM層80係跨及連結密封體MR之貫通孔MR1與貫通孔MR2之各中心之假想線170之兩側而配置。換言之,於上述假想線170上配置絕緣層70與TIM層80。 藉此,藉由於上述假想線170上配置絕緣層70與TIM層80,可緩和螺栓固定時之損傷。 另,於俯視下(背面視)下,沿上述假想線170之方向配置之絕緣層70之一端部(長邊)與假想線170之距離L3和絕緣層70之另一(相反側)端部(長邊)與假想線170之距離L4較佳為相同。即,於圖56所示之構造中,較佳為L3=L4。藉由設為L3=L4,可提高半導體模組SA對於散熱板140以螺栓固定時之安定性。 進而,可在不脫離上述實施形態1、2中說明之技術思想之主旨的範圍內,將實施例與變化例組合而應用。 於上述實施形態1、2中,作為組入半導體模組之功率元件,以功率雙極電晶體(Bipolar Transistor)等、IGBT為例進行說明,但作為組入元件亦可為功率MOSFET等。 又,於上述實施形態1中,絕緣層70與TIM層80為不同之構件,雖分別單獨說明了貼附於密封體MR之情形,但亦可預先準備接合絕緣體70與TIM層80而形成之片材構造體180(參照圖50),於藉由樹脂塑模形成之密封體MR,貼附上述片材構造體180。此時,以絕緣層70覆蓋晶片搭載部TAB1~4之各背面之露出部之方式,將上述片材構造體180貼附於密封體MR之背面BS6。 另,於該情形時,亦於俯視(背面視)下,片材構造體180之TIM層80之區域包含於絕緣層70之區域。 又,絕緣層70及TIM層80亦可以每晶片搭載部、或每半導體晶片予以分割而貼附於密封體MR,於該情況下亦可獲得與實施形態1之半導體模組SA相同之效果。 即,即使絕緣層70及TIM層80以每晶片搭載部或每半導體晶片予以分割,且將該分割之絕緣層70及TIM層80貼附於密封體MR之構造,則只要滿足絕緣層70之尺寸>TIM層80之尺寸、絕緣層70之尺寸≧晶片搭載部之露出部尺寸、TIM層80之尺寸≧所有半導體晶片之區域即可。藉此,可獲得與實施形態1之半導體模組SA相同之效果。 又,實施形態包含以下之形態。 (附記1) 一種片材構造體,其係貼附於具備內置功率電晶體之半導體晶片之半導體模組的片材構造體;且具有 絕緣層,係以搭載上述半導體晶片之晶片搭載部之一部分露出於上述半導體模組之密封體背面,且覆蓋於上述密封體之上述背面露出之上述晶片搭載部之一部分之方式貼附於上述密封體; 熱傳導材料層,其與上述絕緣層積層而接合; 於俯視下,上述熱傳導材料層之區域包含於上述絕緣層之區域。
1a‧‧‧外引線
2a‧‧‧外引線
4‧‧‧二極體芯片
10‧‧‧IGBT晶片
20‧‧‧二極體晶片
30‧‧‧控制晶片
40‧‧‧金導線
50‧‧‧鋁導線
60‧‧‧導電性之接合材
65‧‧‧非導電性之接合材
70‧‧‧絕緣層
70a‧‧‧表面(第1面)
70b‧‧‧背面(第2面)
71‧‧‧第1邊
72‧‧‧第2邊
73‧‧‧第3邊
74‧‧‧第4邊
80‧‧‧TIM層(熱傳導材料層)
81‧‧‧第5邊
82‧‧‧第6邊
83‧‧‧第7邊
84‧‧‧第8邊
90‧‧‧引線框架
90a‧‧‧製品形成區域
90b‧‧‧框部
100‧‧‧半導體模組
110‧‧‧塑模模具
110a‧‧‧上模具
110b‧‧‧下模具
110c‧‧‧模腔
110d‧‧‧底面
110e‧‧‧澆口
110f‧‧‧通氣孔
120‧‧‧密封樹脂
130‧‧‧鍍覆膜
140‧‧‧散熱板
150‧‧‧螺栓構件
160‧‧‧PCB基板
170‧‧‧假想線
180‧‧‧薄片構造體
A-A‧‧‧線
ADE‧‧‧陽極電極
ADP‧‧‧陽極電極墊
B-B‧‧‧線
BS1‧‧‧背面(第2面)
BS2‧‧‧背面(第2面)
BS3‧‧‧背面(第2面)
BS4‧‧‧背面(第2面)
BS5‧‧‧背面(第2面)
BS6‧‧‧背面(第2面)
CDE‧‧‧陰極電極
CE‧‧‧集極電極
CHP1(HU)‧‧‧半導體晶片
CHP1(HV)‧‧‧半導體晶片
CHP1(HW)‧‧‧半導體晶片
CHP1(LU)‧‧‧半導體晶片
CHP1(LV)‧‧‧半導體晶片
CHP1(LW)‧‧‧半導體晶片
CHP2(HU)‧‧‧半導體晶片
CHP2(HV)‧‧‧半導體晶片
CHP2(HW)‧‧‧半導體晶片
CHP2(LU)‧‧‧半導體晶片
CHP2(LV)‧‧‧半導體晶片
CHP2(LW)‧‧‧半導體晶片
CHP3‧‧‧導體晶片
COM‧‧‧端子
EE‧‧‧射極電極
EP‧‧‧射極電極墊
ER‧‧‧n+型半導體區域
ET‧‧‧射極端子
FS1‧‧‧表面(第1面)
FS2‧‧‧表面(第1面)
FS3‧‧‧表面(第1面)
FS4‧‧‧表面(第1面)
FS5‧‧‧表面(第1面)
FS6‧‧‧表面(第1面)
FWD‧‧‧二極體
GCC‧‧‧閘極控制電路
GE‧‧‧閘極電極
GND‧‧‧接地電位
GOX‧‧‧閘極絕緣膜
GP‧‧‧閘極電極墊
GT‧‧‧閘極端子
H1N1‧‧‧端子
H1N2‧‧‧端子
H1N3‧‧‧端子
HDC‧‧‧高側驅動電路
HDC1‧‧‧高側驅動電路
HDC2‧‧‧高側驅動電路
HDC3‧‧‧高側驅動電路
HIN‧‧‧端子
HL‧‧‧懸吊引線
HQ1‧‧‧高側IGBT
INV‧‧‧反相器電路
ISC‧‧‧輸入信號處理電路
ISC1~ISC3‧‧‧輸入信號處理電路
L2‧‧‧沿面距離
L3‧‧‧距離
L4‧‧‧距離
LD1‧‧‧引線
LD2‧‧‧引線
LDC‧‧‧低側驅動電路
LDC1‧‧‧低側驅動電路
LDC2‧‧‧低側驅動電路
LDC3‧‧‧低側驅動電路
LG1‧‧‧第1接腳
LG2‧‧‧第2接腳
LG3‧‧‧第3接腳
LIN‧‧‧端子
LIN1‧‧‧端子
LIN2‧‧‧端子
LIN3‧‧‧端子
LPS‧‧‧低壓電源
LPS1‧‧‧低壓電源
LQ1‧‧‧低側IGBT
LSC‧‧‧位準位移電路
LSC1~LSC3‧‧‧位準位移電路
MR‧‧‧密封體
MR1‧‧‧貫通孔
MR2‧‧‧貫通孔
NC‧‧‧端子
NR1‧‧‧n+型半導體區域
NR2‧‧‧n-型半導體區域
NR3‧‧‧n+型半導體區域
NR4‧‧‧n-型半導體區域
NT‧‧‧負電位端子
NU‧‧‧端子
NV‧‧‧端子
NW‧‧‧端子
P‧‧‧端子
P‧‧‧橫的長度
PR1‧‧‧p+型半導體區域
PR2‧‧‧p型半導體區域
PR3‧‧‧p型半導體區域
PR4‧‧‧p-型半導體區域
PT‧‧‧正電位端子
Q‧‧‧縱長
Q1‧‧‧IGBT
R‧‧‧長度
RT‧‧‧轉子
S‧‧‧長度
SA‧‧‧半導體模組
SS1‧‧‧側面
TAB‧‧‧晶片搭載部
TAB1~TAB5‧‧‧晶片搭載部
TR‧‧‧溝槽
T‧‧‧自貫通孔MR1到貫通孔MR2的距離
U‧‧‧端子
V‧‧‧端子
VB‧‧‧端子
VB1 ~VB3‧‧‧端子
VCC‧‧‧端子
VDD‧‧‧端子
Vs‧‧‧端子
Vss‧‧‧端子
Vs1~Vs3‧‧‧端子
W‧‧‧導線
圖1係顯示實施形態1之半導體模組之構造之俯視圖。 圖2係顯示圖1之半導體模組之構造之背面圖。 圖3係顯示沿著圖2之A-A線切斷之構造之剖視圖。 圖4係顯示沿著圖2之B-B線切斷之構造之剖視圖。 圖5係顯示圖1之半導體模組之內部構造之透射俯視圖。 圖6係顯示本發明人所比較研討之半導體模組之構造之俯視圖。 圖7係顯示圖6之半導體模組之構造之背面圖。 圖8係顯示沿著圖6之A-A線之切斷之構造之剖視圖。 圖9係顯示沿著圖6之B-B線之切斷之構造之剖視圖。 圖10係顯示圖1之半導體模組中之反相器電路及3相感應馬達之馬達電路之構成之電路圖。 圖11係顯示於圖1之半導體模組中形成IGBT之半導體晶片之外形形狀之俯視圖。 圖12係顯示圖11之IGBT之器件構造之剖視圖。 圖13係顯示於圖1之半導體模組中形成二極體之半導體晶片之外形形狀之俯視圖。 圖14係顯示圖13之二極體之器件構造之剖視圖。 圖15係顯示圖1之半導體模組中之閘極控制電路之電路方塊構成之圖。 圖16係顯示圖1之半導體模組中之電路方塊構成之圖。 圖17係顯示圖16之閘極控制電路之內部方塊構成之圖。 圖18係顯示使圖17之閘極控制電路具體化之半導體晶片之構成之模式圖。 圖19係顯示於圖1顯示之半導體模組之組裝中使用之導線框架之構造之俯視圖。 圖20係顯示沿著圖19之A-A線切斷之構造之剖視圖。 圖21係顯示沿著圖19之B-B線切斷之構造之剖視圖。 圖22係顯示於圖1所示之半導體模組之組裝中IGBT晶片與二極體晶片之晶片接合完成時之構造之俯視圖。 圖23係顯示沿著圖22之A-A線切斷之構造之剖視圖。 圖24係顯示沿著圖22之B-B線切斷之構造之剖視圖。 圖25係顯示於圖1所示之半導體模組之組裝中控制晶片之晶片接合完成時之構造之俯視圖。 圖26係顯示於圖1所示之半導體模組之組裝中鋁導線之導線接合完成時之構造之俯視圖。 圖27係顯示圖1所示之半導體模組之組裝中金導線之導線接合完成時之構造之俯視圖。 圖28係顯示於圖1所示之半導體模組之組裝中將於塑模模具之模腔內配置已完成導線接合之導線框架之構造沿圖22之A-A線切斷之構造之剖視圖。 圖29係顯示於圖1所示之半導體模組之組裝中將於塑模模具之模腔內配置已完成導線接合之導線框架之構造沿圖22之B-B線切斷之構造之剖視圖。 圖30係於圖28所示之構造中顯示將樹脂開始注入模腔內之狀態之剖視圖。 圖31係於圖29所示之構造中將樹脂開始注入模腔內之狀態之剖視圖。 圖32係顯示於圖28所示之構造中完成向模腔內注入樹脂之狀態之剖視圖。 圖33係顯示於圖29所示之構造中完成向模腔內注入樹脂之狀態之剖視圖。 圖34係顯示將已完成塑模之導線框架自塑模模具取出之構造之俯視圖。 圖35係顯示沿著圖34之A-A線切斷之構造之剖視圖。 圖36係顯示沿著圖34之B-B線切斷之構造之剖視圖。 圖37係顯示於圖1所示之半導體模組之組裝中鍍覆形成後之構造之俯視圖。 圖38係顯示沿著圖37之A-A線切斷之構造之剖視圖。 圖39係顯示沿著圖37之B-B線切斷之構造之剖視圖。 圖40係顯示圖1所示之半導體模組之組裝中,顯示導線切斷/成形後之構造之俯視圖。 圖41係顯示圖40之半導體模組之構造之背面圖。 圖42係顯示沿著圖40之A-A線切斷之構造之剖視圖。 圖43係顯示沿著圖40之B-B線切斷之構造之剖視圖。 圖44係顯示於圖1所示之半導體模組之組裝中絕緣層及TIM層貼附後之構造之背面圖。 圖45係顯示沿著圖44之A-A線切斷之構造之剖視圖。 圖46係顯示沿著圖44之B-B線切斷之構造之剖視圖。 圖47係顯示將圖44所示之半導體模組安裝於散熱板之構造沿圖44之A-A線切斷之構造之剖視圖。 圖48係顯示將圖44所示之半導體模組安裝於散熱板之構造沿圖44之B-B線切斷之構造之剖視圖。 圖49係顯示本發明人所比較研討之半導體模組之構造之部分剖視圖。 圖50係顯示本實施形態1之半導體模組之構造之部分剖視圖。 圖51係顯示於本實施形態1之半導體模組之背面側之構造中晶片搭載部之露出部之各部尺寸之一例之背面圖。 圖52係顯示本實施形態1之半導體模組之背面側之構造之背面圖。 圖53係顯示於本實施形態1之變化例之半導體模組之背面側之構造中晶片搭載部之露出構造之背面圖。 圖54係顯示本實施形態1之變化例之半導體模組之背面側之構造之背面圖。 圖55係顯示於本實施形態2之半導體模組之背面側之構造中晶片搭載部之露出構造之背面圖。 圖56係顯示本實施形態2之半導體模組之背面側之構造之背面圖。
Claims (18)
- 一種半導體模組之製造方法,其具有以下步驟: (a)準備內置第1功率電晶體、且具有第1面與第2面之第1半導體晶片,該第1面具備電性連接於上述第1功率電晶體之第1端子,該第2面位於上述第1面之相反側,且形成有電性連接於上述第1功率電晶體之第2端子; (b)準備內置第2功率電晶體、且具有第1面與第2面之第2半導體晶片,該第1面具備電性連接於上述第2功率電晶體之第3端子,該第2面位於上述第1面之相反側,且形成有電性連接於上述第2功率電晶體之第4端子; (c)於上述(a)步驟之後,於具有第1面及上述第1面之相反側之第2面之第1晶片搭載部,以上述第1晶片搭載部之上述第1面與上述第1半導體晶片之上述第2面對向之方式,經由導電性之第1接合材而搭載上述第1半導體晶片; (d)上述(b)步驟之後,於具有第1面及上述第1面之相反側之第2面之第2晶片搭載部,以上述第2晶片搭載部之上述第1面與上述第2半導體晶片之上述第2面對向之方式,經由導電性之第2接合材而搭載上述第2半導體晶片; (e)於上述(c)及(d)步驟之後,將上述第1半導體晶片之上述第1端子與上述第2晶片搭載部經由第1導電性構件電性連接; (f)於上述(c)及(d)步驟之後,將上述第2半導體晶片之上述第3端子與導線經由第2導電性構件電性連接; (g)於上述(e)及(f)步驟之後,將上述第1半導體晶片、上述第2半導體晶片、上述第1晶片搭載部之一部分、上述第2晶片搭載部之一部分、上述第1導電性構件、上述第2導電性構件、及上述導線之一部分,以具有第1面及上述第1面之相反側之第2面之密封體,以上述第1晶片搭載部之上述第2面與上述第2晶片搭載部之上述第2面各者自上述密封體之上述第2面露出之方式加以密封; (h)於上述(g)步驟之後,於上述密封體之上述第2面,以覆蓋上述第1晶片搭載部之上述第2面與上述第2晶片搭載部之上述第2面之方式,貼附絕緣層;及 (i)於上述(h)步驟之後,將熱傳導材料層貼附於上述絕緣層; 此處,於上述(i)步驟之後,於俯視下,上述熱傳導材料層之區域包含於上述絕緣層之區域內。
- 如請求項1之半導體模組之製造方法,其中 於上述(i)步驟之後,於透過俯視下,上述第1半導體晶片與上述第2半導體晶片各者位於上述熱傳導材料層之區域之內側。
- 如請求項1之半導體模組之製造方法,其中 於上述(g)步驟之後,且上述(h)步驟之前,具有將自上述密封體露出之複數根上述導線各者之一部分切斷/成形之步驟。
- 如請求項1之半導體模組之製造方法,其中 於俯視下,上述密封體具有各自自上述密封體之上述第1面貫通至上述第2面之第1貫通孔及第2貫通孔; 上述絕緣層及上述熱傳導材料層位於上述第1貫通孔與上述第2貫通孔之間。
- 如請求項4之半導體模組之製造方法,其中 於上述第1貫通孔與上述第2貫通孔各者安裝螺栓構件; 藉由上述螺栓構件而接合上述密封體與散熱板。
- 如請求項5之半導體模組之製造方法,其中 於俯視下,上述絕緣層與上述熱傳導材料層係跨及連結上述第1貫通孔與上述第2貫通孔各者中心之假想線之兩側而配置。
- 如請求項6之半導體模組之製造方法,其中 於俯視下,於沿上述假想線之方向配置之上述絕緣層之一邊與上述假想線之距離、與上述絕緣層之另一邊與上述假想線之距離相同。
- 如請求項1之半導體模組之製造方法,其中 上述半導體模組進而具備控制上述第1半導體晶片與上述第2半導體晶片之控制晶片; 於透過俯視下,上述控制晶片位於上述絕緣層之區域與上述熱傳導材料層之區域。
- 如請求項1之半導體模組之製造方法,其中 上述第1晶片搭載部與上述第2晶片搭載部各者之厚度為上述絕緣層與上述熱傳導材料層各者之厚度以上。
- 如請求項1之半導體模組之製造方法,其中 上述第1半導體晶片之上述第1端子為射極端子,且上述第2端子為集極端子; 上述第2半導體晶片之上述第3端子為射極端子,且上述第4端子為集極端子。
- 如請求項1之半導體模組之製造方法,其中 於上述(i)步驟之後,於俯視下,上述絕緣層具有沿第1方向延伸之第1邊、上述第1邊之相反側之第2邊、於與上述第1方向交叉之第2方向延伸之第3邊及位於上述第3邊之相反側之第4邊,且於俯視下,上述熱傳導材料層具有沿上述第1方向延伸之第5邊、上述第5邊相反側之第6邊、沿上述第2方向延伸之第7邊、及上述第7邊之相反側之第8邊,進而,於俯視下,上述熱傳導材料層之上述第5邊位於上述絕緣層之上述第1邊與上述絕緣層之上述第2邊之間,上述熱傳導材料層之上述第6邊位於上述絕緣層之上述第2邊與上述熱傳導材料層之上述第5邊之間,上述熱傳導材料層之上述第7邊位於上述絕緣層之上述第3邊與上述絕緣層之上述第4邊之間,上述熱傳導材料層之上述第8邊位於上述絕緣層之上述第4邊與上述熱傳導材料層之上述第7邊之間。
- 一種半導體模組之製造方法,其具有以下步驟: (a)準備內置第1功率電晶體、且具有第1面與第2面之第1半導體晶片,該第1面具備電性連接於上述第1功率電晶體之第1端子,該第2面位於上述第1面之相反側,且形成有電性連接於上述第1功率電晶體之第2端子; (b)準備內置第2功率電晶體、且具有第1面與第2面之第2半導體晶片,該第1面具備電性連接於上述第2功率電晶體之第3端子,該第2面位於上述第1面之相反側,且形成有電性連接於上述第2功率電晶體之第4端子; (c)於上述(a)步驟之後,於具有第1面及上述第1面之相反側之第2面之第1晶片搭載部,以上述第1晶片搭載部之上述第1面與上述第1半導體晶片之上述第2面對向之方式,經由導電性之第1接合材而搭載上述第1半導體晶片; (d)上述(b)步驟之後,於具有第1面及上述第1面之相反側之第2面之第2晶片搭載部,以上述第2晶片搭載部之上述第1面與上述第2半導體晶片之上述第2面對向之方式,經由導電性之第2接合材而搭載上述第2半導體晶片; (e)於上述(c)及(d)步驟之後,將上述第1半導體晶片之上述第1端子與上述第2晶片搭載部經由第1導電性構件電性連接; (f)於上述(c)及(d)步驟之後,將上述第2半導體晶片之上述第3端子與導線經由第2導電性構件電性連接; (g)於上述(e)及(f)步驟之後,將上述第1半導體晶片、上述第2半導體晶片、上述第1晶片搭載部之一部分、上述第2晶片搭載部之一部分、上述第1導電性構件、上述第2導電性構件、及上述導線之一部分,以具有第1面及上述第1面之相反側之第2面之密封體,以上述第1晶片搭載部之上述第2面與上述第2晶片搭載部之上述第2面各者自上述密封體之上述第2面露出之方式加以密封; (h)於上述(g)步驟之後,以接合絕緣層與熱傳導材料層而形成之薄片構造體之上述絕緣層覆蓋上述第1晶片搭載部之上述第2面與上述第2晶片搭載部之上述第2面之方式,於上述密封體之上述第2面貼附上述薄片構造體; 於上述(h)步驟之後,於俯視下,上述薄片構造體之上述熱傳導材料層之區域包含於上述絕緣層之區域內。
- 如請求項12之半導體模組之製造方法,其中 於上述(h)步驟之後,於透過俯視下,上述第1半導體晶片與上述第2半導體晶片各者位於上述熱傳導材料層之區域之內側。
- 如請求項12之半導體模組之製造方法,其中 於上述(h)步驟之後,於俯視下,上述絕緣層具有沿第1方向延伸之第1邊、上述第1邊相之反側之第2邊、於與上述第1方向交叉之第2方向延伸之第3邊及位於上述第3邊相反側之第4邊,且於俯視下,上述熱傳導材料層具有沿上述第1方向延伸之第5邊、上述第5邊之相反側之第6邊、沿上述第2方向延伸之第7邊、及上述第7邊之相反側之第8邊,進而,於俯視下,上述熱傳導材料層之上述第5邊位於上述絕緣層之上述第1邊與上述絕緣層之上述第2邊之間,上述熱傳導材料層之上述第6邊位於上述絕緣層之上述第2邊與上述熱傳導材料層之上述第5邊之間,上述熱傳導材料層之上述第7邊位於上述絕緣層之上述第3邊與上述絕緣層之上述第4邊之間,上述熱傳導材料層之上述第8邊位於上述絕緣層之上述第4邊與上述熱傳導材料層之上述第7邊之間。
- 一種半導體模組,其具有: 第1半導體晶片,其內置第1功率電晶體,且具有第1面與第2面,該第1面具備電性連接於上述第1功率電晶體之第1端子,該第2面位於上述第1面之相反側,且形成有電性連接於上述第1功率電晶體之第2端子; 第2半導體晶片,其內置第2功率電晶體,且具有第1面與第2面,該第1面具備電性連接於上述第2功率電晶體之第3端子,該第2面位於上述第1面之相反側,且形成有電性連接於上述第2功率電晶體之第4端子; 第1晶片搭載部,其具有第1面及其相反側之第2面,且以上述第1晶片搭載部之上述第1面與上述第1半導體晶片之上述第2面對向之方式,經由導電性之第1接合材料而搭載上述第1半導體晶片; 第2晶片搭載部,其具有第1面及其相反側之第2面,且以上述第2晶片搭載部之上述第1面與上述第2半導體晶片之上述第2面對向之方式,經由導電性之第2接合材而搭載上述第2半導體晶片; 複數根導線,其配置於上述第1晶片搭載部與上述第2晶片搭載部之周圍; 第1導電性構件,其電性連接上述第1半導體晶片之上述第1端子與上述第2晶片搭載部; 第2導電性構件,其電性連接上述第2半導體晶片之上述第3端子與上述複數根導線中之任一導線; 上述密封體,其具有第1面及上述第1面之相反側之第2面,且將上述第1半導體晶片、上述第2半導體晶片、上述第1晶片搭載部之一部分、上述第2晶片搭載部之一部分、上述第1導電性構件、上述第2導電性構件、及上述複數根導線各者之一部分,以上述第1晶片搭載部之上述第2面與上述第2晶體搭載部之上述第2面各者自上述密封體之上述第2面露出之方式加以密封; 絕緣層,其以覆蓋上述第1晶體搭載部之上述第2面與上述第2晶體搭載部之上述第2面之方式接合於上述密封體之上述第2面; 熱傳導材料層,其與上述絕緣層積層而接合; 於俯視下,上述熱傳導材料層之區域包含於上述絕緣層之區域內。
- 如請求項15之半導體模組,其中 於透過俯視下,上述第1半導體晶片與上述第2半導體晶片各者配置於上述熱傳導材料層之區域之內側。
- 如請求項15之半導體模組,其進而具備: 控制上述第1半導體晶片與上述第2半導體晶片之控制晶片; 於透過俯視下,上述控制晶片配置於上述絕緣層之區域與上述熱傳導材料層之區域。
- 如請求項15之半導體模組,其中 於俯視下,上述絕緣層具有於第1方向延伸之第1邊、上述第1邊之相反側之第2邊、於與上述第1方向交叉之第2方向延伸之第3邊及上述第3邊之相反側之第4邊; 於俯視下,上述熱傳導材料層具有於上述第1方向延伸之第5邊、上述第5邊之相反側之第6邊、於上述第2方向延伸之第7邊及上述第7邊之相反側之第8邊; 於俯視下,上述熱傳導材料層之上述第5邊位於上述絕緣層之上述第1邊與上述絕緣層之上述第2邊之間,上述熱傳導材料層之上述第6邊位於上述絕緣層之上述第2邊與上述熱傳導材料層之上述第5邊之間;上述熱傳導材料層之上述第7邊位於上述絕緣層之上述第3邊與上述絕緣層之上述第4邊之間,上述熱傳導材料層之上述第8邊位於上述絕緣層之上述第4邊與上述熱傳導材料層之上述第7邊之間。
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