TW201901906A - 半導體積體電路以及形成用於半導體積體電路的電力軌的方法 - Google Patents
半導體積體電路以及形成用於半導體積體電路的電力軌的方法 Download PDFInfo
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- TW201901906A TW201901906A TW107109391A TW107109391A TW201901906A TW 201901906 A TW201901906 A TW 201901906A TW 107109391 A TW107109391 A TW 107109391A TW 107109391 A TW107109391 A TW 107109391A TW 201901906 A TW201901906 A TW 201901906A
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- Prior art keywords
- power rail
- integrated circuit
- metal
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 238000000034 method Methods 0.000 title claims description 27
- 229910052751 metal Inorganic materials 0.000 claims abstract description 175
- 239000002184 metal Substances 0.000 claims abstract description 175
- 239000004020 conductor Substances 0.000 claims abstract description 75
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims description 15
- 238000000059 patterning Methods 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 11
- 229910052707 ruthenium Inorganic materials 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 8
- 238000001459 lithography Methods 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 2
- 125000006850 spacer group Chemical group 0.000 claims 2
- 239000010949 copper Substances 0.000 description 14
- 238000004519 manufacturing process Methods 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 238000009413 insulation Methods 0.000 description 6
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 5
- 229910017052 cobalt Inorganic materials 0.000 description 5
- 239000010941 cobalt Substances 0.000 description 5
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 5
- 230000009977 dual effect Effects 0.000 description 5
- 230000008021 deposition Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 239000013590 bulk material Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000010970 precious metal Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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Abstract
本發明提供一種半導體積體電路,其包含一基板、一連串金屬層以及一連串絕緣層。所述金屬層及所述絕緣層以一堆疊的形式交替地佈置在所述基板上。所述半導體積體電路亦包含在所述基板中之至少兩個標準單元及橫越所述至少兩個標準單元之邊界之至少一個電力軌。所述電力軌包含連續延伸穿過所述堆疊之至少兩個垂直層級的導電材料的一垂直區段。所述堆疊之所述兩個垂直層級包含一個金屬層及一個絕緣層。所述絕緣層在所述金屬層上方。
Description
本發明大體上是關於用於半導體積體電路之電力軌結構。
電力軌是用於向積體電路中之標準單元供應電力(例如VSS
、VDD
)的低電阻連接。在相關技術的電力軌中,電力軌包含第一或第二金屬層級(或所述兩者),所述電力軌需要與在所述金屬層級之間延伸的接點或通孔連接。舉例而言,圖1A至圖1B示出包含習知電力軌之半導體積體電路。圖1A至圖1B中所示出之習知電力軌包含最低金屬層M0中之下部電力供應器跡線101、中間金屬層M1中之金屬短線102、上部金屬層M2中之上部電力供應器跡線103、基板104中的連接至下部電力供應器跡線101的接點CA、第一絕緣層105中的在下部電力供應器跡線101與金屬短線102之間延伸並互連下部電力供應器跡線101與金屬短線102的下部通孔V0,以及第二絕緣層106中的在金屬短線102與上部電力供應器跡線103之間延伸並互連金屬短線102與上部電力供應器跡線103的上部通孔V1。電晶體可形成於基板104中,且接點CA可連接至電晶體之終端,例如FET源極終端。
由於在先進技術中金屬線具有高電阻,相關技術的電力軌的製造變得愈來愈具挑戰性。金屬線中之此類高電阻可由小橫截面金屬面積、邊緣散射及/或減少金屬線之有效橫截面面積之襯墊或障壁之存在所致。由於相關技術的電力軌的電阻不斷增加,積體電路設計者必須向電網投入大量貴金屬資源(例如,由於可用的信號選路軌道較少而增加晶粒大小),或設計較高電阻的電網且因此影響產品頻率。此外,使用經通孔連接之多個離散層級的導體並非是高效的,是因為在每一雙鑲嵌層級處有高電阻狹窄通孔及多個高電阻襯墊。此外,每一雙鑲嵌層級處之障壁及襯墊縮小軌尺寸並增加塊體導體材料損失。
提供此背景技術部分中揭露的上述資訊,用於增強對本發明之背景技術的理解,且因此其可含有不構成先前技術的資訊。
本發明是關於半導體積體電路之各種實施例。在一個實施例中,半導體積體電路包含基板、一連串金屬層以及一連串絕緣層。金屬層及絕緣層以堆疊形式交替地佈置在基板上。所述半導體積體電路亦包含在基板中之至少兩個標準單元及橫越所述至少兩個標準單元之邊界之至少一個電力軌。所述電力軌包含連續延伸穿過所述堆疊之至少兩個垂直層級的導電材料之垂直區段。堆疊之兩個垂直層級包含一個金屬層及一個絕緣層。一個絕緣層在一個金屬層上方。
所述至少兩個垂直層級可包含堆疊之至少三個垂直層級。所述三個垂直層級包含所述一連串金屬層中之兩個金屬層及所述一連串絕緣層中的在所述兩個金屬層之間的一個絕緣層。所述兩個金屬層可包含金屬層M0及金屬層M1。半導體積體電路亦可包含在金屬層M2中之上部電力供應器跡線及在上部電力供應器跡線與電力軌的垂直區段之間延伸的通孔。所述兩個金屬層可包含金屬層M1及金屬層M2。半導體積體電路可包含在金屬層M0中之下部電力供應器跡線及在電力軌之垂直區段與下部電力供應器跡線之間延伸的通孔。堆疊之至少三個垂直層級可包含三個金屬層及兩個絕緣層,且三個金屬層可包含金屬層M0、金屬層M1以及金屬層M2。
至少一個電力軌的導電材料之垂直區段可不包含通孔。
半導體積體電路亦可包含在導電材料之垂直區段周圍延伸之襯墊。襯墊並不延伸穿過導電材料之垂直區段。
電力軌之垂直區段可展現實質上等於導電材料之塊體電阻的電阻。
至少一個電力軌之導電材料可包含金屬。至少一個電力軌之填充導體可為包含Cu、Co、Ru或其組合之金屬。
本發明亦是關於形成用於半導體積體電路之電力軌之各種方法。在一個實施例中,所述方法包含蝕刻交替的金屬層及絕緣層在基板上的堆疊以在所述堆疊上形成凹腔,及藉由在所述凹腔中沈積導電材料而形成電力軌。所述電力軌包含連續延伸穿過所述堆疊之至少三個垂直層級的導電材料之垂直區段。所述至少三個垂直層級包含兩個金屬層及在所述兩個金屬層之間的一個絕緣層。
蝕刻堆疊可包含單一蝕刻作業。
所述方法亦可包含在沈積導電材料之前形成襯墊。
形成電力軌的作業可包含在沈積導電材料之後的化學機械平坦化。
形成電力軌可包含遮蔽作業。
形成電力軌可包含單一圖案化作業或微影蝕刻-微影蝕刻(litho-etch, litho-etch;LELE)序列、自對準雙重圖案化(self-aligned quad-patterning;SADP)序列或自對準四重圖案化(self-aligned quad-patterning;SAQP)序列。
導電材料可包含金屬,諸如Cu、Co、Ru或其組合。
一種形成用於根據本發明之另一實施例之半導體積體電路之電力軌的方法包含蝕刻交替的金屬層及絕緣層在基板上的堆疊以在所述堆疊中形成凹腔,及藉由在凹腔中沈積導電材料而形成電力軌。所述電力軌包含連續延伸穿過所述堆疊之至少兩個垂直層級的導電材料之垂直區段。所述至少兩個垂直層級包含一個金屬層及一個絕緣層。堆疊之蝕刻包含單一微影作業。
提供此發明內容以引入本發明之實施例的一系列特徵及概念,所述特徵及概念在下文於詳細描述中得以進一步描述 此發明內容並不意欲識別所主張主題之關鍵特徵或基本特徵,亦不意欲用於限制所主張主題之範疇。所描述特徵中之一或多者可與一或多個其他所描述特徵組合,以提供可工作裝置。
本發明是關於半導體積體電路之各種實施例,所述半導體積體電路包含用於向積體電路中之基於標準單元的邏輯區塊供應電力(例如VSS
、VDD
、GND)之電力軌結構。本發明之電力軌結構經組態以減小電遷移(EM)降級及電壓(IR)下降,所述電力軌結構經組態以改良產品頻率。本發明之電力軌結構包含連續延伸穿過堆疊之至少兩個垂直層級的導電材料之垂直區段(例如,連續延伸穿過兩個金屬層(諸如金屬層M0及M1)及所述兩個金屬層之間的一個絕緣層的導電材料之垂直區段)。因此,根據本發明之各種實施例之電力軌結構用連續延伸穿過積體電路之至少兩個垂直層級之單一塊體金屬填充之結構來替換一或多個跡線及一或多個通孔。
提供連續延伸穿過至少兩個垂直層級之電力軌結構會降低密集通孔之利用率。降低密集通孔之利用率會降低總軌電阻,並緩解對於在積體電路之製造期間主動圖案化的需求。此外,提供連續延伸穿過至少兩個垂直層級之電力軌結構降低高電阻襯墊之利用率,所述高電阻襯墊在習知電力軌結構中慣常包圍相鄰的金屬層及通孔層(例如,在習知電力軌結構中,高電阻襯墊包圍雙鑲嵌層級中之每一者,諸如M2中之跡線及通孔V1或M1短線以及通孔V0,如此增加電力軌結構之總體電阻)。此外,提供連續延伸穿過至少兩個垂直層級之電力軌結構使電力軌結構之幾何大小相較於習知電力軌結構增加,且電力軌結構之增加的幾何大小可導致導電材料呈現等於或實質上等於導電材料(例如銅)之塊體電阻特性的電阻。相比之下,用於習知電力軌結構中之導電材料的相對較小的幾何結構使導電材料呈現大於導電材料之塊體電阻特性(例如近似地是導電材料之塊體電阻兩倍)的電阻。
併入有本發明之電力軌結構之半導體積體電路經組態成具有可用於信號選路之增大的空間,是因為與併入有習知電力軌之半導體積體電路相比,可使電力軌更窄且可以鬆弛間距製作連接到電力軌之垂直綁帶。此外,本發明之電力軌結構可實現單元高度降低及/或及經改良之AC FOM及DC FOM(例如較高Ieff
)。
下文中,將參考附圖更詳細地描述實例實施例,在附圖中,相同圖式元件符號始終是指相同元件。然而,本發明可以各種不同形式體現,且不應解釋為僅限於本文中的所示實施例。確切而言,提供這些實施例作為實例,使得本發明將為透徹且完整的,且將向本領域的技術人員充分傳達本發明的態樣及特徵。因此,可不描述不為本領域的一般技術人員完整理解本發明的態樣及特徵所必需的程序、元件以及技術。除非另外指出,否則相同圖式元件符號貫穿附圖及書面描述表示相同元件,且因此將不重複其描述。
在圖中,可為了清晰起見而放大及/或簡化元件、層以及區域的相對大小。諸如「在…以下」、「在…下方」、「下部」、「在…下面」、「在…上方」、「上部」等的空間相對術語可在本文中為了便於解釋而使用,以描述一個元件或特徵與如圖中所示出之另一元件或特徵的關係。將理解,空間相對術語意欲涵蓋裝置在使用或操作中除圖中所描繪之定向以外的不同定向。舉例而言,若圖中的裝置翻轉,則描述為「在」其他元件或特徵「下方」或「以下」或「下面」的元件將接著被定向為「在」其他元件或特徵「上方」。因此,實例術語「在…下方」及「在…下面」可涵蓋上方及下方的定向兩者。裝置可以其他方式定向(例如,旋轉90度或處於其他定向),且本文中所使用的空間相對描述詞應相應地進行解釋。
應理解,雖然術語「第一」、「第二」、「第三」等可在本文中用以描述各種元件、組件、區域、層及/或區段,但這些元件、組件、區域、層及/或區段不應受這些術語限制。這些術語用以將一個元件、組件、區域、層或區段與另一元件、組件、區域、層或區段相區別。因此,在不脫離本發明的精神及範疇的情況下,下文所描述之第一元件、組件、區域、層或區段可被稱為第二元件、組件、區域、層或區段。
應理解,當元件或層被稱作「在另一元件或層上」、「連接至另一元件或層」或「耦接至另一元件或層」時,所述元件或層可直接在另一元件或層上、直接連接至另一元件或層或耦接至另一元件或層,或可能存在一或多個介入的元件或層。另外,亦將理解,當元件或層被稱作「在兩個元件或層之間」時,所述元件或層可為在兩個元件或層之間的唯一元件或層,或亦可存在一或多個介入的元件或層。
本文中使用之術語僅用於描述特定實施例之目的,且並不意欲限制本發明。如本文所使用,除非上下文另外清晰地指示,否則單數形式「一(a/an)」意欲亦包含複數形式。應進一步理解,術語「包括(comprises/comprising)」以及「包含(includes/including)」在用於本說明書中時指定所陳述特徵、整體、步驟、操作、元件及/或組件的存在,但並不排除一或多個其他特徵、整體、步驟、操作、元件、組件及/或其群組的存在或添加。如本文所使用,術語「及/或」包含相關聯的所列項目中的一或多者中的任一及所有組合。在元件列表前面的表達(諸如「中之至少一者」)修改整個元件列表且並不修改所述列表中之個別元件。
如本文中所使用,術語「實質上」、「約」以及類似術語用作表示近似的術語且並不用作表示程度的術語,且意欲考慮將由本領域的一般技術人員辨識的所量測值或計算值的固有偏差。另外,「可」在描述本發明之實施例時的使用是指「本發明之的一或多個實施例」。如本文中所使用,術語「使用(use/using/used)」可分別被視為與術語「利用(utilize/utilizing/utilized)」同義。此外,術語「例示性」意欲指代實例或說明。
除非另外定義,否則本文所使用之所有術語(包含技術及科學術語)具有與本發明所屬領域的一般技術人員通常理解的相同含義。應進一步理解,術語(諸如常用詞典中所定義之術語)應解釋為具有與其在相關技術之上下文及/或本發明中之含義相一致的含義,且不應在理想化或過度正式的意義上來解釋,除非本文中如此明確定義。
現參考圖2A至圖2B,根據本發明之一個實施例之半導體積體電路200包含:標準單元區塊201,其包含至少兩個標準單元202、203;及電力軌204,其側向越過或延伸在所述兩個標準單元202、203的邊界上方。電力軌204經組態以在積體電路200中向至少兩個標準單元202、203供應電力(例如VSS
、VDD
、GND)。標準單元202、203可為任何類型的單元,例如反相器、反及(NAND)閘、或非(NOR)閘、計數器、正反器或其他邏輯電路。標準單元202、203可具有不同裝置架構,例如基於翅片或薄片的裝置(例如,鰭式場效應電晶體(FinFET)或奈米薄片場效應電晶體,諸如水平奈米片場效應電晶體或垂直場效應電晶體)。在整個圖式中,示意性地描繪標準單元202、203,且為簡單起見而省略標準單元202、203之組件(例如源電極/汲電極及閘極)。
在所示出之實施例中,半導體積體電路200包含以堆疊205之形式交替地佈置在基板206上之一連串金屬層及一連串絕緣通孔層。在所示出之實施例中,堆疊205包含在基板206上之最低金屬層M0、在最低金屬層M0上之下部絕緣層207、在下部絕緣層207上之第二金屬層M1、在第二金屬層M1上之第二絕緣層208以及在第二絕緣層208上之第三金屬層M2。
電力軌204包含連續延伸穿過堆疊205之至少兩個垂直層的導電材料的連續垂直區段209。在圖2A至圖2B中所示出之實施例中,電力軌204之連續垂直區段209連續延伸穿過最低金屬層M0、下部絕緣層207以及第二金屬層M1(亦即,電力軌204之連續垂直區段209連續延伸穿過兩個金屬層及一個絕緣通孔層)。此外,在所示出之實施例中,半導體積體電路200包含在電力軌204的導電材料的連續垂直區段209周圍延伸的襯墊210。襯墊210並不延伸穿過(例如平分)電力軌204之連續垂直區段209。
因此,圖2A至圖2B中所示出之電力軌204之實施例的連續垂直區段209在如(例如)圖1A至圖1B中所示的習知電力軌結構中取代下部金屬層M0中之下部電力供應器跡線、金屬層M1中之金屬短線以及在下部電力供應器跡線與金屬短線之間延伸的下部通孔V0。此外,圖2A至圖2B中所示出之電力軌204之實施例的連續垂直區段209消除在習知電力軌結構中將下部電力供應器跡線與下部通孔V0分離的襯墊的部分。以此方式,電力軌204的導電材料之連續垂直區段209降低襯墊及連接離散金屬層級之通孔的利用率,如在(例如)圖1A至圖1B中所示的相關技術的積體電路中一般,所述連續垂直區段連續延伸穿過堆疊205之三個垂直層。
消除高電阻通孔及襯墊之一部分使本發明之電力軌204之總電阻相較於習知電力軌降低。此外,消除通孔使電力軌204之幾何大小(例如體積)相較於習知電力軌結構增加,且電力軌結構204之增加的幾何大小(例如體積)使連續垂直區段209呈現等於或實質上等於連續垂直區段209之導電材料的塊體電阻特性的電阻。相比之下,用於習知電力軌結構中之下部金屬層M0中之金屬短線及下部電力供應器跡線的相對較小的幾何結構使導電材料呈現大於金屬短線及下部電力供應器跡線之導電材料的塊體電阻特性(例如近似地是導電材料之塊體電阻兩倍)的電阻。降低密集通孔之利用率亦緩解對於在積體電路之製造期間主動圖案化的需求。
此外,在所示出之實施例中,電力軌204包含在上部金屬層M2中之上部電力供應器跡線211(例如最高跡線)及在電力軌204之連續垂直區段209與上部電力供應器跡線211之間延伸的第二通孔V1(例如最高通孔)。在所示出之實施例中,積體電路200亦包含包圍上部電力供應器跡線211及第二通孔V1之雙鑲嵌層級的襯墊212。在一或多個實施例中,諸如在高密度(high-density;HD)標準單元中,可自電力軌204中省略第二通孔V1及上部電力供應器跡線211以開放上部金屬層M2中之選路。
電力軌204之連續垂直區段209的導電材料可為金屬。在一或多個實施例中,電力軌204之連續垂直區段209的導電材料(亦即填充導體)可為銅(Cu)、鈷(Co)、釕(Ru)或其組合。
在一或多個實施例中,電力軌之連續垂直區段可連續延伸穿過堆疊中之任何其他數目的金屬層及絕緣層。舉例而言,圖3描繪半導體積體電路之實施例,其中電力軌301包含導電材料(例如,銅(Cu)、鈷(Co)、釕(Ru)或其組合)之連續垂直區段302,所述連續垂直區段連續延伸穿過最低金屬層M0、最低金屬層M0上之下部絕緣層303、下部絕緣層303上之第二金屬層M1、第二金屬層M1上之第二絕緣層304以及第二絕緣層304上之第三金屬層M2(亦即,電力軌301之連續垂直區段302連續延伸穿過三個金屬層及兩個絕緣通孔層)。此外,在所示出之實施例中,電力軌301包含在電力軌301的導電材料之連續垂直區段302周圍延伸的襯墊305。襯墊305並不延伸穿過(例如平分)電力軌301之連續垂直區段302。
因此,圖3中所示出之電力軌301之實施例的連續垂直區段302在如(例如)圖1A至圖1B中所示的習知電力軌結構中取代下部金屬層M0中之下部電力供應器跡線、金屬層M1中之金屬短線、上部金屬層M2中之上部電力供應器跡線、在下部電力供應器跡線與金屬短線之間延伸的下部通孔V0以及在金屬短線與上部電力供應器跡線之間延伸的上部通孔V1。此外,圖3中所示出之電力軌301之實施例的連續垂直區段302消除在習知電力軌結構中將下部電力供應器跡線與下部通孔V0分離及將金屬短線與上部通孔V1分離的襯墊的部分。以此方式,電力軌301的導電材料之連續垂直區段302降低襯底及連接離散金屬層級之通孔的利用率,如在(例如)圖1A至圖1B中所示的相關技術的積體電路中一般,所述連續垂直區段連續延伸穿過堆疊之五個垂直層。
消除高電阻通孔及襯墊之部分使本發明之電力軌301之總電阻相較於習知電力軌降低。此外,消除通孔使電力軌301之幾何大小(例如體積)相較於習知電力軌結構增加,且電力軌結構301之增加的幾何大小(例如體積)使連續垂直區段302呈現等於或實質上等於連續垂直區段302之導電材料的塊體電阻特性的電阻。相比之下,用於習知電力軌結構中之下部電力供應器跡線、金屬短線以及上部電力供應器跡線的相對較小的幾何結構使導電材料呈現大於下部電力供應器跡線、金屬短線以及上部電力供應器跡線之導電材料的塊體電阻特性(例如近似地是導電材料之塊體電阻兩倍)的電阻。降低密集通孔之利用率亦緩解對於在積體電路之製造期間主動圖案化的需求。
圖4描繪半導體積體電路之實施例,其中電力軌401包含導電材料(例如,銅(Cu)、鈷(Co)、釕(Ru)或其組合)之連續垂直區段402,所述連續垂直區段連續延伸穿過第二金屬層M1、第二金屬層M1上之上部絕緣層403以及上部絕緣層403上之第三金屬層M2(亦即,電力軌401之連續垂直區段402連續延伸穿過兩個金屬層及一個絕緣通孔層)。電力軌401亦包含在下部絕緣層404中連接至連續垂直區段402的通孔V0。
在所示出之實施例中,半導體積體電路亦包含在電力軌401的導電材料的連續垂直區段402周圍延伸的襯墊405。襯墊405並不延伸穿過(例如平分)電力軌401之連續垂直區段402。此外,在所示出之實施例中,電力軌401包含最低金屬層M0中之下部電力供應器跡線406及包圍下部電力供應器跡線406及連接至下部電力供應器跡線406的接點CA的鑲嵌層級之襯墊407。
可利用圖4中所示出的電力軌401之組態,電力軌未處於最低金屬層M0上。在此情況下,增加的M0信號選路資源可供使用。
因此,圖4中所示出之電力軌401之實施例的連續垂直區段402在如(例如)圖1A至圖1B中所示的習知電力軌結構中取代金屬層M1中之金屬短線、上部金屬層M2中之上部電力供應器跡線以及在金屬短線與上部電力供應器跡線之間延伸的上部通孔V1。此外,圖4中所示出之電力軌401之實施例的連續垂直區段402消除在習知電力軌結構中將金屬短線與上部通孔V1分離的襯墊的部分。以此方式,電力軌401的導電材料之連續垂直區段402降低襯墊及連接離散金屬層級之通孔的利用率,如在(例如)圖1A至圖1B中所示的相關技術的積體電路中一般,所述連續垂直區段連續延伸穿過堆疊之三個垂直層。
如上文所描述,消除高電阻通孔及襯墊之一部分使本發明之電力軌401之總電阻相較於習知電力軌降低。此外,消除通孔使電力軌401之幾何大小(例如體積)相較於習知電力軌結構增加,且電力軌結構401之增加的幾何大小(例如體積)使連續垂直區段402呈現等於或實質上等於連續垂直區段402之導電材料的塊體電阻特性的電阻。相比之下,用於習知電力軌結構中之金屬短線及上部電力供應器跡線的相對較小的幾何結構使導電材料呈現大於金屬短線及上部電力供應器跡線之導電材料的塊體電阻特性(例如近似地是導電材料之塊體電阻兩倍)的電阻。降低密集通孔之利用率亦緩解對於在積體電路之製造期間主動圖案化的需求。
圖5描繪半導體積體電路之實施例,其中電力軌501包含導電材料(例如,銅(Cu)、鈷(Co)、釕(Ru)或其組合)之連續垂直區段502,所述連續垂直區段連續延伸穿過下部絕緣層503及下部絕緣層503上之金屬層M1(亦即,電力軌501之連續垂直區段502連續延伸穿過一個金屬層及一個絕緣通孔層)。
在所示出之實施例中,半導體積體電路亦包含在電力軌501的導電材料的連續垂直區段502周圍延伸的襯墊504。襯墊504並不延伸穿過(例如平分)電力軌501之連續垂直區段502。此外,在所示出之實施例中,電力軌501包含最低金屬層M0中之下部電力供應器跡線505(例如最低跡線)及包圍下部電力供應器跡線505及連接至下部電力供應器跡線505的接點CA的鑲嵌層級之襯墊506。在所示出之實施例中,電力軌501亦包含在上部金屬層M2中之上部電力供應器跡線507(例如最高跡線)及包圍上部電力供應器跡線507及在上部絕緣層509中連接至上部電力供應器跡線507之上部通孔V1的雙鑲嵌層級之襯墊508。
因此,圖5中所示出之電力軌501之實施例的連續垂直區段502在如(例如)圖1A至圖1B中所示的習知電力軌結構中取代金屬層M1中之金屬短線及連接至所述金屬短線的下部通孔V0。以此方式,電力軌501的導電材料之連續垂直區段502降低連接離散金屬層級之通孔的利用率,如在(例如)圖1A至圖1B中所示的相關技術的積體電路中一般,所述連續垂直區段連續延伸穿過堆疊之兩個垂直層。
如上文所描述,消除高電阻通孔使本發明之電力軌501之總電阻相較於習知電力軌降低。此外,消除通孔使電力軌501之幾何大小(例如體積)相較於習知電力軌結構增加,且電力軌結構501之增加的幾何大小(例如體積)使連續垂直區段502呈現等於或實質上等於連續垂直區段502之導電材料的塊體電阻特性的電阻。相比之下,用於習知電力軌結構中之金屬短線的相對較小的幾何結構使導電材料呈現大於金屬短線之導電材料的塊體電阻特性(例如近似地是導電材料之塊體電阻兩倍)的電阻。降低密集通孔之利用率亦緩解對於在積體電路之製造期間主動圖案化的需求。
併入有本文所描述之電力軌之實施例(例如圖2A至圖2B、圖3、圖4或圖5中所描繪的電力軌之實施例)的單元架構可藉由使得上部層級選路軌道(例如第三金屬層M2)能夠僅用於信號選路而實現積體電路大小相較於併入有習知電力軌結構(例如圖1A至圖1B中所描繪的習知電力軌結構)的單元減小。歸因於電力軌與源極/汲極(S/D)區域之間的較低寄生電阻及/或減小的單元高度,併入有本文中所描述之電力軌之實施例的單元架構實現經改良的DC FOM(例如較高Ieff
)及/或AC FOM(例如iso電力下之較高頻率),如此實現後段製程(back-end-of-line;BEOL)延行長度的減小及與單元之間的BEOL延行長度相關聯的寄生電容(Cpara
)或寄生電阻(Rpara
)的相對應減小。併入有本文中所描述之電力軌之實施例(與習知電力軌相比具有相對較窄寬度)的單元架構可具有僅用於信號選路之更多選路軌道,如此實現選路軌道之間距相較於習知單元架構的增加,同時達成與習知單元架構相比相同或減小的單元高度。歸因於選路軌道之增加的線寬及/或增加的間隔,併入有本文中所描述之電力軌之實施例的單元架構與習知單元架構相比可具有增加的選路軌道間距,如此實現與選路軌道之內或之間的材料相關聯的Rpara
或Cpara
的減小。歸因於比與無通孔之大表面電力軌結構連接相關聯的習知單元架構低的Rpara
,併入有本文中所描述之電力軌之實施例的單元架構實現經改良之DC FOM及/或經改良之AC FOM。歸因於因信號選路之擁塞減少而比習知單元架構低的Rpara
及Cpara
,併入有本文中所描述之電力軌之實施例的單元架構實現經改良之DC FOM及/或經改良之AC FOM。歸因於比與選路軌道相關聯之習知單元架構低的Rpara
及Cpara
以及電力軌與源極/汲極區之間的較低Rpara
及/或減小的單元高度,併入有本文中所描述之電力軌之實施例的單元架構實現經改良之DC FOM及/或經改良之AC FOM,從而實現單元之間減小的BEOL延行長度。歸因於(例如)減小單元高度、減小用於配電之上部層級選路軌道之數目及/或增加上部層級選路軌道之間距,相較於習知單元架構,併入有本文中所描述之電力軌之實施例的單元架構實現經改良之DC FOM及/或經改良之AC FOM。
圖6A至圖6B示出製造根據本發明之一個實施例之半導體積體電路之圖3的電力軌301的方法。如圖6A中所示出,所述方法包含以下作業:蝕刻交替的金屬層M0、金屬層M1、金屬層M2以及絕緣通孔層602、隔絕通孔層603在基板604上之堆疊601,以在所述堆疊601中形成深溝槽或凹腔605(例如執行高縱橫比介電質蝕刻)。蝕刻堆疊601之作業可藉由任何合適的程序或技術(例如微影、側壁影像轉移或乾式蝕刻)來執行。蝕刻堆疊601以形成凹腔605之作業可包含單一蝕刻作業或兩個或大於兩個蝕刻作業。在一或多個實施例中,蝕刻交替的金屬層之堆疊601可指代蝕刻金屬層中之絕緣材料以使得金屬稍後可沈積在經蝕刻凹腔中。溝槽或凹腔605垂直地延伸穿過堆疊601之兩個或大於兩個層。可取決於電力軌之所要組態來選擇凹腔605之深度(亦即,凹腔605延伸穿過的層)。舉例而言,在所示出之實施例中,凹腔延伸穿過上部金屬層M2、上部絕緣通孔層603、中間金屬層M1、下部絕緣通孔層602以及下部金屬層M0(亦即,凹腔605始終向下延伸至基板604)。在一或多個實施例中,凹腔605可延伸穿過上部金屬層M2、上部絕緣通孔層603以及中間金屬層M1。在一或多個實施例中,凹腔605可僅延伸穿過下部金屬層M0、下部絕緣通孔層602以及中間金屬層M1。在一或多個實施例中,凹腔605可僅延伸穿過中間金屬層M1及下部絕緣通孔層602。
現參考圖6B,所述方法亦包含藉由在凹腔605中沈積導電材料606而形成圖3之電力軌301的作業。在凹腔605中沈積導電材料606的作業可包含單一沈積作業且可藉由本領域中現今已知或下文開發的任何合適技術或程序執行。在一或多個實施例中,形成電力軌301之作業可包含額外遮蔽作業。在一或多個實施例中,導電材料可為金屬,諸如銅(Cu)、鈷(Co)、釕(Ru)或其組合。
在一或多個實施例中,形成電力軌301之作業可包含在於凹腔605中沈積導電材料606的作業之前形成襯墊607(例如沈積襯墊)的作業。此外,在一或多個實施例中,形成電力軌301之作業可包含在於凹腔605中沈積導電材料606的作業之後進行化學機械平坦化(chemical-mechanical planarization;CMP)的作業。在所示出之實施例中,CMP作業經組態以將沈積至凹腔605中之導電材料606處理成與上部金屬層M2具有相同的表面結構(topology)(上表面層級)。
在一或多個實施例中,形成電力軌301之作業可利用單一圖案化層來執行。在一或多個實施例中,形成電力軌301之作業可利用現今已知或下文開發之任何合適的圖案化技術執行,諸如利用多重圖案化技術(例如微影蝕刻-微影蝕刻(LELE)序列)或自對準圖案化序列(諸如自對準雙重圖案化(SADP)或自對準四重圖案化(SAQP))來執行。在一或多個實施例中,形成電力軌301之作業可共用與由電力軌301覆蓋之最頂金屬層(例如金屬層M2)相同的沈積/填充作業及/或相同的CMP作業。
如圖6B中所示出,圖3之電力軌301包含所沈積導電材料606(例如金屬,諸如Cu、Co、Ru或其組合)的連續垂直區段608,所述連續垂直區段連續延伸穿過下部金屬層M0、下部絕緣層602、中間金屬層M1、上部絕緣層603以及上部金屬層M2(亦即,電力軌301之連續垂直區段608延伸穿過三個金屬層M0、M1、M2以及兩個絕緣層602、603)。在一或多個實施例中,電力軌之連續垂直區段608可取決於在蝕刻堆疊601之作業期間形成的凹腔605的組態(例如深度)而連續延伸穿過任何其他數目之金屬層及絕緣層。舉例而言,在一或多個實施例中,所沈積材料606之連續垂直區段608可連續延伸穿過最低金屬層M0、下部絕緣通孔層602以及中間金屬層M1(亦即,電力軌之連續垂直區段608延伸穿過兩個金屬層M0、M1及一個絕緣層602)。在一或多個實施例中,所沈積材料606之連續垂直區段608可連續延伸穿過中間金屬層M1、上部絕緣通孔層603以及上部金屬層M2(亦即,電力軌之連續垂直區段608延伸穿過兩個金屬層M1、M2及一個絕緣層603)。此外,在一或多個實施例中,所沈積材料606之連續垂直區段608可僅連續延伸穿過金屬層M1及下部絕緣層602(亦即,電力軌之連續垂直區段608延伸穿過一個金屬層M1及一個絕緣層602)。根據本發明之方法形成的電力軌可具有任何合適的組態,諸如上文參考圖2A至圖5中所示出的實施例所描述之電力軌的任何組態。在一或多個實施例中,可形成兩個或大於兩個電力軌,且可以不同深度形成不同的電力軌結構,例如以滿足電壓(IR)下降及電遷移(EM)需求。
儘管已參考實例實施例描述本發明,但本領域的技術人員將認識到,可在完全不脫離本發明的精神以及範疇的情況下執行對所描述實施例的各種改變以及修改。另外,熟習各項技術者將認識到,本文中所描述的本發明將建議對其他作業的解決方案以及對其他應用的調適。申請人的目的為,在完全不脫離本發明的精神以及範疇的情況下,藉由本文中之申請專利範圍涵蓋本發明的所有此類用途,以及出於揭露的目的可對本文中所選擇之本發明的實例實施例作出的那些改變以及修改。因此,本發明之實例實施例在所有方面均應被視為說明性而非限定性的,其中本發明之精神以及範疇是由所附申請專利範圍及其等效物而指示。
101、406、505‧‧‧下部電力供應器跡線
102‧‧‧金屬短線
103、211、507‧‧‧上部電力供應器跡線
104、206、604‧‧‧基板
105‧‧‧第一絕緣層
106‧‧‧第二絕緣層
200‧‧‧半導體積體電路
201‧‧‧標準單元區塊
202、203‧‧‧標準單元
204、301、401、501‧‧‧電力軌
205、601‧‧‧堆疊
209、302、402、502、608‧‧‧連續垂直區段
210、212、305、405、407、504、506、508、607‧‧‧襯墊
207、303、404、503‧‧‧下部絕緣層
208、304‧‧‧第二絕緣層
403、509‧‧‧上部絕緣層
602‧‧‧下部絕緣通孔層
603‧‧‧上部絕緣通孔層
605‧‧‧凹腔
606‧‧‧導電材料
M0‧‧‧最低金屬層
M1‧‧‧中間金屬層
M2‧‧‧上部金屬層
V0‧‧‧下部通孔
V1‧‧‧上部通孔
CA‧‧‧接點
2B‧‧‧剖面線
當結合下圖考慮時,藉由參考以下詳細描述,本發明之實施例的所述及其他特徵以及優勢將變得更顯而易見。在圖中,貫串諸圖使用相同圖式元件符號以指代相同特徵及組件。圖式未必按比例繪製。 圖1A至圖1B是包含相關技術的電力軌的半導體積體電路之示意性剖面圖,所述相關技術的電力軌包含互連離散金屬層級之一連串通孔。 圖2A至圖2B分別是根據本發明之一個實施例的包含電力軌之半導體積體電路的示意性平面圖及剖面圖。 圖3是根據本發明之另一實施例的包含電力軌之半導體積體電路的示意性剖面圖。 圖4是根據本發明之另外的實施例的包含電力軌之半導體積體電路的示意性剖面圖。 圖5是根據本發明之另外的實施例的包含電力軌之半導體積體電路的示意性剖面圖。 圖6A至圖6B描繪形成根據本發明之一個實施例的具有電力軌之半導體積體電路之方法的作業的示意性剖面圖。
Claims (20)
- 一種半導體積體電路,其包括: 一基板; 多個金屬層; 多個絕緣層,其中所述多個金屬層及所述多個絕緣層以一堆疊的形式交替地佈置在所述基板上; 所述基板中之至少兩個標準單元;以及 越過所述至少兩個標準單元之邊界的至少一個電力軌,所述至少一個電力軌包括連續延伸穿過所述堆疊之至少兩個垂直層級的導電材料的一垂直區段,所述至少兩個垂直層級包括所述多個金屬層中的一個金屬層以及所述多個絕緣層中的一個絕緣層,其中所述一個絕緣層在所述一個金屬層上方。
- 如申請專利範圍第1項所述的半導體積體電路,其中所述至少兩個垂直層級包括所述堆疊之至少三個垂直層級,所述至少三個垂直層級包括所述多個金屬層中的兩個金屬層以及所述多個絕緣層中的在所述兩個金屬層之間的一個絕緣層。
- 如申請專利範圍第1項所述的半導體積體電路,其中所述至少一個電力軌之所述導電材料的所述垂直區段不包含一通孔。
- 如申請專利範圍第1項所述的半導體積體電路,其更包括在所述導電材料之所述垂直區段周圍延伸的一襯墊,且其中所述襯墊並不延伸穿過所述導電材料之所述垂直區段。
- 如申請專利範圍第1項所述的半導體積體電路,其中所述電力軌之所述垂直區段呈現實質上等於所述導電材料之一塊體電阻的一電阻。
- 如申請專利範圍第1項所述的半導體積體電路,其中所述至少一個電力軌之所述導電材料包括一金屬。
- 如申請專利範圍第1項所述的半導體積體電路,其中所述至少一個電力軌之一填充導體為一金屬,其包括Cu、Co、Ru或其組合。
- 如申請專利範圍第2項所述的半導體積體電路,其中所述兩個金屬層包括金屬層M0及金屬層M1。
- 如申請專利範圍第8項所述的半導體積體電路,其更包括金屬層M2中之一上部電力供應器跡線以及在所述上部電力供應器跡線與所述電力軌之所述垂直區段之間延伸的一通孔。
- 如申請專利範圍第2項所述的半導體積體電路,其中所述兩個金屬層包括金屬層M1及金屬層M2。
- 如申請專利範圍第10項所述的半導體積體電路,其更包括金屬層M0中之一下部電力供應器跡線以及在所述電力軌之所述垂直區段與所述下部電力供應器跡線之間延伸的一通孔。
- 如申請專利範圍第2項所述的半導體積體電路,其中所述堆疊之所述至少三個垂直層級包括三個金屬層及兩個絕緣層,所述三個金屬層包括金屬層M0、金屬層M1以及金屬層M2。
- 一種形成用於一半導體積體電路的一電力軌的方法,所述方法包括: 蝕刻交替的金屬層及絕緣層在一基板上之一堆疊,以在所述堆疊中形成一凹腔;以及 形成所述電力軌包括在所述凹腔中沈積一導電材料,所述電力軌包括連續延伸穿過所述堆疊的至少三個垂直層級的所述導電材料的一垂直區段,所述至少三個垂直層級包括兩個金屬層以及在所述兩個金屬層之間的一個絕緣層。
- 如申請專利範圍第13項所述的形成電力軌的方法,其中所述蝕刻所述堆疊包括一單一蝕刻作業。
- 如申請專利範圍第13項所述的形成電力軌的方法,其更包括在所述導電材料之所述沈積之前形成一襯墊。
- 如申請專利範圍第13項所述的形成電力軌的方法,其中所述形成所述電力軌更包括在所述導電材料之所述沈積之後進行化學機械平坦化。
- 如申請專利範圍第13項所述的形成電力軌的方法,其中所述形成所述電力軌更包括一遮蔽作業。
- 如申請專利範圍第13項所述的形成電力軌的方法,其中所述形成所述電力軌包括一單一圖案化作業或一微影蝕刻-微影蝕刻序列、自對準雙重圖案化序列或自對準四重圖案化序列。
- 如申請專利範圍第13項所述的形成電力軌的方法,其中所述導電材料包括一金屬,所述金屬是由Cu、Co、Ru及其組合所構成的族群中選出。
- 一種形成用於一半導體積體電路的一電力軌的方法,所述方法包括: 蝕刻交替的金屬層及絕緣層在一基板上之一堆疊,以在所述堆疊中形成一凹腔;以及 形成所述電力軌包括在所述凹腔中沈積一導電材料,所述電力軌包括連續延伸穿過所述堆疊的至少兩個垂直層級的所述導電材料的一垂直區段,所述至少兩個垂直層級包括一個金屬層及一個絕緣層, 其中所述堆疊之所述蝕刻包括一單一微影作業。
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2018
- 2018-03-20 TW TW107109391A patent/TWI754026B/zh active
- 2018-03-20 CN CN201810228911.8A patent/CN108630656B/zh active Active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI782491B (zh) * | 2020-05-12 | 2022-11-01 | 台灣積體電路製造股份有限公司 | 積體電路佈局產生系統、積體電路結構以及產生積體電路佈局圖的方法 |
US11893333B2 (en) | 2020-05-12 | 2024-02-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid sheet layout, method, system, and structure |
Also Published As
Publication number | Publication date |
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CN108630656A (zh) | 2018-10-09 |
KR20180106826A (ko) | 2018-10-01 |
US10784198B2 (en) | 2020-09-22 |
US20180269152A1 (en) | 2018-09-20 |
KR102502870B1 (ko) | 2023-02-22 |
TWI754026B (zh) | 2022-02-01 |
CN108630656B (zh) | 2023-08-11 |
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