TW201843782A - 具有電功能熱傳導結構之半導體裝置組件 - Google Patents

具有電功能熱傳導結構之半導體裝置組件 Download PDF

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TW201843782A
TW201843782A TW107104874A TW107104874A TW201843782A TW 201843782 A TW201843782 A TW 201843782A TW 107104874 A TW107104874 A TW 107104874A TW 107104874 A TW107104874 A TW 107104874A TW 201843782 A TW201843782 A TW 201843782A
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hts
semiconductor device
die
device assembly
semiconductor
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TW107104874A
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TWI685930B (zh
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湯瑪士 H 金斯利
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美商美光科技公司
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    • H01L23/367—Cooling facilitated by shape of device
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Abstract

本文中揭示具有經堆疊半導體晶粒及電功能熱傳導結構(HTS)之半導體裝置組件。在一項實施例中，一半導體裝置組件包含具有一安裝表面之一第一半導體晶粒，該安裝表面具有一基底區域及毗鄰該基底區域之一周邊區域。至少一個第二半導體晶粒可在該基底區域處電耦合至該第一半導體晶粒。該裝置組件亦可包含在該周邊區域處電耦合至該第一半導體晶粒之一HTS。

Description

具有電功能熱傳導結構之半導體裝置組件
所揭示之實施例係關於半導體裝置組件，且特定而言係關於具有電功能熱傳導結構之半導體裝置組件。
包含記憶體晶片、微處理器晶片及成像器晶片之封裝式半導體晶粒通常包含安裝於一基板上且包封於一塑膠保護覆蓋物中之一半導體晶粒。晶粒包含功能特徵，諸如記憶體單元、處理器電路及/或成像器裝置以及電連接至該等功能特徵之接合墊。接合墊可電連接至保護覆蓋物外部之端子以允許晶粒連接至較高階電路。 半導體製造商不斷減小晶粒封裝之大小以裝配於電子裝置之空間約束內，同時亦增加每一封裝之功能能力以滿足操作參數。用於在實質上不增加由封裝覆蓋之表面積(亦即，封裝之「佔據面積」)之情況下增加一半導體封裝之處理能力之一種方法係在一單個封裝中在彼此之頂部上垂直堆疊多個半導體晶粒。此等經垂直堆疊封裝中之晶粒可藉由使用穿矽導通體(TSV)將個別晶粒之接合墊與毗鄰晶粒之接合墊電耦合來互連。在經垂直堆疊封裝中，所產生之熱難以耗散，此增加個別晶粒、其間之接面及作為一整體之封裝之操作溫度。此可致使經堆疊晶粒達到高於其在諸多類型之裝置中之最大操作溫度之溫度。
下文闡述具有電功能熱傳導結構之半導體裝置組件之數項實施例之具體細節。術語「半導體裝置」通常係指包含半導體材料之一固態裝置。一半導體裝置可包含(舉例而言)一半導體基板、晶圓或自一晶圓或基板單粒化之晶粒。貫穿本發明，通常在半導體晶粒之脈絡中闡述半導體裝置；然而，半導體裝置並不限於半導體晶粒。 術語「半導體裝置封裝」可係指具有併入於一共同封裝中之一或多個半導體裝置之一配置。一半導體封裝可包含部分或完全地囊封至少一個半導體裝置之一外殼或殼體。一半導體裝置封裝亦可包含一中介層基板，該中介層基板載運一或多個半導體裝置且附接至或以其他方式併入至殼體中。術語「半導體裝置組件」可係指一或多個半導體裝置、半導體裝置封裝及/或基板(例如，中介層基板、支撐基板或其他適合基板)之一組件。舉例而言，半導體裝置組件可製造成離散封裝形式、條帶或矩陣形式及/或晶圓面板形式。如本文中所使用，術語「垂直」、「橫向」、「上部」及「下部」可係指鑒於各圖中所展示之定向之半導體裝置或裝置組件中之特徵之相對方向或位置。舉例而言，「上部」或「最上部」可分別係指與其他特徵或同一特徵之部分相比位於較接近於或最接近於一頁面之頂部處之一特徵。然而，此等術語應廣泛地解釋為包含具有其他定向(諸如倒置或傾斜定向)之半導體裝置，其中頂部/底部、上方/下方、上面/下面、上/下及左/右取決於定向可互換。 本技術之數項實施例係針對一半導體裝置組件，該半導體裝置組件包括一第一半導體晶粒、堆疊於第一半導體晶粒上之至少一個第二半導體晶粒，及一電功能熱傳導結構(HTS)。第一半導體晶粒包含具有一基底區域及一周邊區域之一安裝表面，該周邊區域圍繞該基底區域之周界延伸。第二半導體晶粒在基底區域處電耦合至第一半導體晶粒，且電功能HTS在周邊區域處電耦合至第一半導體晶粒。電功能HTS高效地傳導來自第一半導體晶粒之周邊區域之熱且亦提供有助於對半導體裝置組件進行操作之電功能性。因此，期望根據本技術之半導體裝置組件之數項實施例能夠給功能構件提供熱高效經堆疊晶粒配置、小的封裝大小及/或較多空間，此乃因電功能性及自第一半導體晶粒之周邊區域之高效熱傳導兩者係由一共同構件執行。 圖1A及圖1B分別係展示具有根據本技術之一實施例組態之電功能熱傳導結構之一半導體裝置組件100的剖面圖及部分分解剖面圖。特定而言，圖1A係展示製作已完成之後之組件100之一剖面圖，且圖1B係圖解說明組件100之一製作程序之部分之一部分分解圖。參考圖1A，組件100包含一封裝支撐基板102 (例如，一中介層)、安裝至支撐基板102之一第一半導體晶粒104及安裝至第一晶粒104之複數個第二半導體晶粒106 (藉由元件符號106a至106d個別地識別)。第一晶粒104包含具有一基底區域108及一周邊區域110 (熟習此項技術者已知為一「廊」或「架」)之一安裝表面107。第二晶粒106在第一晶粒104之基底區域108上配置成一堆疊112 (「晶粒堆疊112」)。 儘管所圖解說明之圖1A及圖1B之實施例包含具有四個個別第二晶粒106a至106d之晶粒堆疊112，但本技術之其他實施例可包含額外或較少第二晶粒106。舉例而言，在數項實施例中，僅一個第二半導體晶粒106安裝至第一半導體晶粒104。在其他實施例中，兩個、三個，五個、六個或更多第二半導體晶粒106可在第一半導體晶粒104上配置成一晶粒堆疊。 組件100進一步包含具有一帽部分116及一壁部分118之一導熱殼體或蓋114。在所圖解說明之實施例中，帽部分116經由一第一接合材料120a (例如，一黏合劑)接合至壁部分118。在其他實施例中，蓋114可係一連續構件，其中帽部分116與壁部分118整體地形成。壁部分118遠離帽部分116垂直延伸且可藉由一第二接合材料120b (例如，一黏合劑)附接至支撐基板102。除提供一保護覆蓋物之外，蓋114亦可充當用以自半導體晶粒104及106吸收熱能量並耗散熱能量之一散熱器。因此，蓋114可由一導熱材料(諸如鎳(Ni)、銅(Cu)、鋁(Al)、具有高導熱性之陶瓷材料(例如，氮化鋁)及/或其他適合導熱材料)製成。 在某些實施例中，第一接合材料120a及/或第二接合材料120b可由經設計以增加表面接面(例如，一晶粒表面與一散熱器之間)處之接觸導熱性之此項技術中稱為「熱介面材料」或「TIM」之材料製成。TIM可包含摻雜有傳導材料(例如，碳奈米管、焊料材料、類鑽碳(DLC)等)之基於聚矽氧之油脂、凝膠或黏合劑以及相變材料。在其他實施例中，第一接合材料120a及/或第二接合材料120b可包含其他適合材料，諸如金屬(例如，銅)及/或其他適合導熱材料。 第一半導體晶粒104及/或第二半導體晶粒106中之某些或所有可至少部分地囊封於一介電質底部填充材料121中。底部填充材料121可沈積於或以其他方式形成於晶粒中之某些晶粒或所有晶粒周圍或之間以增強與一晶粒之一機械連接及/或提供導電特徵及/或結構(例如，互連件)之間的電隔離。底部填充材料121可係一非導電環氧樹脂膏、一毛細管底部填充物、一非導電膜、一模製底部填充物及/或包含其他適合電絕緣材料。在數項實施例中，可基於其導熱性來選擇底部填充材料121以增強透過組件100之晶粒之熱耗散。在某些實施例中，底部填充材料121可用於代替第一接合材料120a及/或第二接合材料120b以將蓋114附接至最頂部半導體晶粒106d。 第一晶粒104及第二晶粒106可包含各種類型之半導體構件及功能特徵，諸如動態隨機存取記憶體(DRAM)、靜態隨機存取記憶體(SRAM)、快閃記憶體，其他形式之積體電路記憶體、處理電路、成像構件及/或其他半導體特徵。在各種實施例中，舉例而言，組件100可組態為一混合記憶體立方體(HMC)，其中經堆疊第二晶粒106係DRAM晶粒或提供資料儲存之其他記憶體晶粒且第一晶粒104係提供HMC內之記憶體控制(例如，DRAM控制)之一高速邏輯晶粒。在其他實施例中，第一晶粒104及第二晶粒106可包含其他半導體構件及/或晶粒堆疊112中之個別第二晶粒106之半導體構件可不同。在圖1A中所圖解說明之實施例中，第一晶粒104包含可彼此電耦合及/或電耦合至第一晶粒104內之其他電路及/或構件之複數個積體電路122 (個別地識別為一第一積體電路122a、一第二積體電路122b及一第三積體電路122c)。另外，如下文較詳細闡述，積體電路122可係包含第一晶粒104外部之電路構件之相關聯電路之部分。 第一晶粒104及第二晶粒106可電耦合至封裝支撐基板102且藉由複數個導電元件124 (例如，銅柱、焊料凸塊及/或其他導電特徵)彼此耦合。另外，第一晶粒104及第二晶粒106中之每一者可包含複數個穿矽導通體(TSV) 126，該複數個穿矽導通體耦合於與導電元件124對置之側上。除電通信之外，導電元件124及TSV 126至少垂直地遠離晶粒堆疊112且朝向蓋114傳導熱。在某些實施例中，組件100亦可包含間隙地定位於第一晶粒104與第二晶粒106之間以進一步促進透過晶粒堆疊112之熱傳導之複數個導熱元件或「虛設元件」(未展示)。此等虛設元件可一般至少在結構及組成物上與導電元件124及/或TSV 126類似，惟除該等虛設元件不電耦合至第一晶粒104及第二晶粒106之功能電路。 組件100包含安裝至第一晶粒104之周邊區域110之複數個電功能熱傳導結構(HTS) 128 (個別地識別為一第一HTS 128a及一第二HTS 128b)。在數項實施例中，積體電路122中之一或多者可係在操作期間產生相對大量之熱之相關聯電路之部分，諸如串列/解串列化器(SERDES)電路。HTS 128可形成一或多個電子構件，該一或多個電子構件形成與積體電路122相關聯之電路之至少部分。在所圖解說明之圖1A之實施例中，舉例而言，HTS 128包含電容器130，該電容器可經由第一晶粒104及HTS 128上介於接合墊132之間的導電元件134電耦合至積體電路122 (及/或電耦合至第一晶粒104內之其他積體電路或構件)。 在數項實施例中，HTS 128可包含經選擇以提供所要電性質之材料。舉例而言，HTS 128可係由多個矽體積(例如，層)形成之一經堆疊構件。在某些實施例中，個別矽體積可提供大約110 fF/µm2 之電容且個別HTS 128可具有大約2 mm x 13 mm之佔據面積。在一特定實施例中，對應於大約20 µF之一總體電容，HTS可包含八個此等聚矽氧體積。在其他實施例中，HTS 128可包含大於或小於2 mm x 13 mm之其他尺寸及大於或少於20 µF之總體電容。在操作中，由HTS 128提供之電容可產生相對顯著熱，該熱否則將由附接至或位於組件100之其他構件內(例如，附接至基板102或位於第一晶粒104內)之電容器產生。 如圖1A中所展示，HTS 128位於毗鄰於或接近於蓋114之處。特定而言，HTS 128在晶粒堆疊112與蓋114之壁部分118之間橫向延伸，且自第一半導體晶粒104至帽部分116垂直延伸。因此，由HTS 128產生之熱可易於傳導至蓋114，且藉此傳導至蓋114外部之一環境或構件。自HTS 128至蓋114之熱傳導可顯著減小組件100之操作溫度。特定而言，與位於基板102上或位於第一晶粒104內之構件相比，HTS 128快速地將熱傳導至帽部分116及壁部分118。在數項實施例中，HTS 128可與蓋114直接接觸。在其他實施例中，一填充物材料及/或其他構件或材料可在HTS 128與蓋114 (例如，第一接合材料120a)之間。在具有此一介入材料之實施例中，HTS 128可保持相對接近於蓋114及/或與蓋114間接接觸以維持自HTS 128至蓋114之一高的熱傳導速率。舉例而言，介入材料可經選擇以包含適當導熱性(例如，TIM)。 除熱效率之外，本技術之實施例可達成小的封裝大小及/或增加功能構件可用之空間。舉例而言，在現有半導體封裝中，各種電裝置或構件通常整合於或安裝於相關聯封裝基板上、毗鄰於經堆疊晶粒(例如，表面安裝裝置或經整合被動裝置)。此一配置需要在一基底晶粒之佔據面積外部具有可用空間之一封裝基板，且因此需要一較大總體裝置。本文中所揭示之HTS 128可定位為毗鄰於晶粒堆疊112、位於組件100之一部分中，否則該部分將被填充物材料或不直接有助於組件100之電功能之其他非電構件或特徵(例如，被動熱構件)佔據。因此，將電構件及功能性併入HTS 128內可避免否則將位於封裝基板上之電裝置或構件。此可導致小的封裝大小，及/或提供較大效能及功能性之較大或額外構件(例如，較大第一晶粒104)之額外空間。 圖1B之部分分解圖圖解說明組件100之製作程序之一部分。特定而言，第二晶粒106與HTS 128可單獨地製作且隨後附接至第一晶粒104。一起參考圖1A及圖1B，HTS 128具有對應於晶粒堆疊112之最上部表面之一高度之一高度h1 (例如，等於個別第二晶粒106之高度h2 加上其間之導電元件124之總和之一高度)。因此，在裝配時，蓋114之帽部分116可熱耦合至第二晶粒106d之最上部表面且與HTS 128中之一或多者熱耦合。如圖1A中所展示，帽部分116經由第一接合材料120a (及/或經由其他替代或額外介入材料)間接接觸HTS 128中之一或多者。在其他實施例中，帽部分116可直接接觸HTS 128中之一或多者。無論帽部分116直接或間接接觸HTS 128或者以其他方式充分接近於HTS 128，HTS 128至帽部分116之接近皆可提供至組件100外部之相對大量熱傳導。 儘管圖1A及圖1B之所圖解說明實施例包含安裝至第一半導體晶粒104之HTS 128，但其他實施例可包含安裝至其他構件之HTS 128。舉例而言，在數項實施例中，HTS 128可安裝至基板102。在某些此等實施例中，HTS 128可自基板102延伸至帽部分116，且自第一晶粒104及第二晶粒106延伸至壁部分118。另外，此等實施例中之數項實施例可在基板102內包含一重佈層或其他電構件或電路以提供HTS 128與第一晶粒104及/或第二晶粒106之間的電連接。 圖2係技術方案1之半導體裝置組件100沿著圖1A之線2-2之一俯視平面圖。基底區域108佔據第一半導體晶粒104之一安裝表面202之大部分且至少部分地由可對應於第二半導體晶粒106 (圖1A及圖1B)之一佔據面積之一邊界或周界204劃界。周邊區域110圍繞周界204延伸，且接合墊132位於基底區域108及周邊區域110兩者內。如圖1A及圖1B之剖面圖中所展示，第一HTS 128a及第二HTS 128b位於第二晶粒106之兩個相對之側上。然而，將理解，額外HTS 128可位於毗鄰第二晶粒106之額外側處。舉例而言，第一晶粒104可包含額外接合墊206 (以虛線展示)以毗鄰於第二晶粒106之其他相對之側安裝額外HTS 128。在此等實施例中，額外HTS 128可電連接至積體電路122或經由額外接合墊206電連接至第一半導體晶粒104內之其他構件或電路。在數項實施例中，基底區域108可佔據安裝表面202的比圖2中所展示之部分更大之一部分。舉例而言，周邊區域110可在基底區域108之兩個相對之側上延伸，且基底區域108可延伸穿過由圖2中所展示之額外接合墊206佔據的安裝表面202之至少一部分。在此等實施例中，基底區域108可自周邊區域110藉由沿著周界204之各別對置部分同軸延伸之兩個邊界線劃界。 圖3A及圖3B係根據本技術之一實施例之自一半導體晶圓300裂解之熱傳導結構128之俯視平面圖。晶圓300可係經由此項技術中已知之各種技術(例如，物理汽相沈積、化學汽相沈積、微影程序、蝕刻等)而製作。該製作可包含沈積多個半導體材料(例如，矽)體積(例如，層)以形式HTS 128之體積。另外，製作可包含經由各種半導體製作技術形成互連件、接合墊132、穿矽導通體(TSV)及/或其他特徵。在形成晶圓300之後，HTS 128可經由(例如)切粒自晶圓300單粒化。 圖3A中所展示之晶圓300未必按比例繪製，但可包含(例如) 300 mm之一直徑。個別HTS 128 (其亦未必按比例繪製)可經製作以具有可針對一相關聯裝置組件之特定設計要求定製之各種大小。舉例而言，在某些實施例中，個別HTS 128可包含2 mm x 13 mm之一佔據面積。HTS 128與晶圓300相比之相對較小大小可達成由單個晶圓300產生大量HTS 128。在一項實施例中，舉例而言，一單個300 mm晶圓可生產大約2000個個別HTS 128。 如圖3B中所展示，個別HTS 128可包含複數個接合墊132。接合墊132可以各種方式配置，且可提供至相關聯HTS 128之一或多個電構件之電連接。在所圖解說明之實施例中，HTS 128包含沿著一安裝表面302隔開之11對接合墊132。每一個別接合墊對可與相關聯HTS 128之一個別電構件相關聯，如下文較詳細闡述。另外，如藉由比較圖2與圖3B可見，HTS 128之接合墊132可與第一半導體晶粒104上之接合墊132對準以將HTS 128電耦合至第一半導體晶粒104。特定而言，HTS 128之接合墊132配置成一陣列以與第一半導體晶粒104之接合墊132疊加(如圖1A中所展示)。 圖4A係根據本技術之沿著圖3B之線4A-4A截取之HTS 128之一實施例之一剖面圖。在所圖解說明之實施例中，HTS 128包含形成一電容器404之複數個電功能體積或層402。特定而言，HTS 128包含八個經垂直堆疊矽體積402。在數項實施例中，體積402可包含一或多個經摻雜或未經摻雜區域。在一項實施例中，體積402中之一或多者可直接接觸緊密毗鄰體積402，如圖4A中所展示。在其他實施例中，空氣間隙或介入材料(例如，介電質材料)可位於一或多個毗鄰體積402之間。HTS 128進一步包含具有一第一導電材料408a (例如，一金屬)之一穿矽導通體(TSV) 406及將第一導電材料408a之一部分與體積402電隔離之一絕緣或介電質材料410。HTS 128可進一步包含與第一導電材料408間隔開之一第二導電材料408ba，其中體積402之至少一部分位於第一導電材料408a與第二導電材料408b之間。第一導電材料408a及第二導電材料408b電耦合至對應接合墊132。第一導電材料408a延伸穿過最上部體積402之一部分。在操作中，體積402 (及/或任何間隙或介入材料)沿著最上部體積402中之第一導電材料408a與最下部體積402中之第二導電材料408b之間的一路徑提供電容。 圖4B係圖解說明根據本技術之另一實施例組態之一電功能熱傳導結構(HTS) 420之一剖面圖。類似於圖4A，圖4B之剖面圖圖解說明沿著對應於圖3B中之線4A-4A之一線截取之HTS 420。HTS 420包含八個經垂直堆疊矽體積422、接合墊424、第一導電材料426a、第二導電材料426b及介電質材料428。在操作中，體積422及/或介電質材料428可提供第一導電材料426a與第二導電材料426b之間的電容。 在數項實施例中，個別HTS 128或420之個別電功能元件、構件或結構可經由一或多個電障壁彼此電隔離。舉例而言，一垂直障壁可經由蝕刻或此項技術中已知之其他技術形成於HTS 128或420內之鄰接電容器及/或其他電功能構件之間。舉例而言，圖3B中所展示之HTS 128可包含經由位於毗鄰電功能構件之間的十個垂直障壁分隔開之十一個電功能構件(各自具有一對應對接合墊132)。 圖5及圖6分別係具有根據本技術之實施例組態之電功能熱傳導結構(HTS)之半導體裝置組件500及600之剖面圖。在所圖解說明之圖5之實施例中，組件500包含至少大體上類似於上文關於圖1A及圖1B所論述的組件100中之對應構件之各種構件。舉例而言，組件500包含一支撐基板502、一第一半導體晶粒504、複數個第二半導體晶粒506及具有一帽部分510及一壁部分512之一蓋508。另外，組件500包含一第一電功能熱傳導結構(HTS) 514a及一第二HTS 514b。第一HTS 514a及第二HTS 514b可包含至少大體上類似於HTS 128及420之數個特徵，該數個特徵包含形成一或多個電容器516 (示意性地展示)或其他電功能構件(諸如一電阻器518 (亦示意性地展示))之複數個經垂直堆疊矽體積。然而，HTS 514包含相對側上之接合墊520 (而非具有相關聯HTS之一共同側上之接合墊)以提供第一晶粒504內之電路與組件500外部之電路(例如，可安裝至組件500之另一組件內之電路)之間的連接。在具有彼等特徵之某些實施例中，蓋508可係電功能的或具有電功能電路。 第二HTS 514b可以至少大體上類似於HTS 128、420及514a之方式之一方式由一或多個材料體積形成。舉例而言，第二HTS 514b可包含多個經垂直堆疊材料體積。然而，一或多個材料可形成電阻式構件而非形成一電容性構件。在一項實施例中，舉例而言，一或多個材料可包含聚矽化物電阻器。 與組件500一樣，組件600亦包含至少大體上類似於上文關於圖1A及圖1B所論述的組件100中之對應構件之各種構件。舉例而言，組件600包含一支撐基板602、一第一半導體晶粒604、複數個第二半導體晶粒606以及具有一帽部分610及一壁部分612之一蓋608。另外，組件600包含一第一電功能熱傳導結構(HTS) 614a及一第二HTS 614b。第二HTS 614b可實質上類似於上文所論述之HTS 128且可包含一電容器616 (示意性地展示)。第一HTS 614a可包含一個二極體618 (亦示意性地展示)。 類似於上文關於圖5所論述之第一HTS 514a，第一HTS 614a亦可包含電耦合至組件600外部之電路之接合墊622。相比而言，第二HTS 614b包含電耦合至組件600內(例如，第一半導體晶粒604內)之一或多個電路之接合墊624。因此，第一HTS 614a與第二HTS 614b一起可提供內部及外部電連接兩者。另外，在數項實施例中，根據本技術組態之個別HTS可包含提供內部及外部電連接之接合墊。舉例而言，一個別HTS可包含位於一共同側上連接至HTS中之一第一電功能構件之一對接合墊，及位於相對側上連接至一第二電功能構件之一對接合墊。此外，在數項實施例中，HTS可在同一個別HTS內包含一個以上種類之電構件(例如，一電容器及一電阻器、一個二極體及一電容器等)。 可將上文參考圖1A至圖6所闡述之經堆疊半導體裝置組件中之任一者併入至無數較大及/或較複雜系統中之任何者中，該等系統之一代表性實例係圖7中示意性地展示之系統700。系統700可包含一半導體裝置組件702、一電源704、一驅動器706、一處理器708及/或其他子系統或組件710。半導體裝置組件702可包含大體上類似於上文參考圖1A至圖6所闡述之半導體裝置組件100、500及600之特徵之特徵，且因此可包含可增強熱耗散之各種HTS。所得系統700可執行各種各樣之功能(諸如記憶體儲存、資料處理及/或其他適合功能)中之任何者。因此，代表性系統700可無限制地包含手持式裝置(例如，行動電話、平板電腦、數位讀取器及數位音訊播放器)、電腦、運載工具、電器及其他產品。系統700之組件可裝納於一單個單元中或(例如，透過一通信網路)分佈於多個經互連單元上。系統700之組件亦可包含遠端裝置及各種各樣之電腦可讀媒體中之任何者。 依據前述內容，將瞭解，雖然本文中已出於圖解說明的目的而闡述本技術之特定實施例，但可在不背離本發明之情況下做出各種修改。另外，各圖中所圖解說明之各種元件及特徵可未必按比例繪製；且本發明之各項實施例可包含除各圖中所圖解說明之結構之外的結構且明確地不限於各圖中所展示之結構。此外，儘管關於HMC闡述HTS之實施例中之諸多實施例，但在其他實施例中，HTS可經組態以供與其他記憶體裝置或其他類型之經堆疊晶粒組件一起使用。另外，亦可在其他實施例中組合或消除在特定實施例之內容脈絡中所闡述之本新技術之特定態樣。此外，儘管已在本新技術之特定實施例之內容脈絡中闡述與彼等實施例相關聯之優點，但其他實施例亦可展現此等優點且並非所有實施例皆必須展現此等優點以歸屬於本技術之範疇內。因此，本發明及相關聯技術可囊括本文中未明確展示或闡述之其他實施例。
2-2‧‧‧ 線
100‧‧‧半導體裝置組件/組件
102‧‧‧封裝支撐基板/支撐基板/基板
104‧‧‧第一半導體晶粒/第一晶粒/半導體晶粒
106a‧‧‧第二晶粒
106b‧‧‧第二晶粒
106c‧‧‧第二晶粒
106d‧‧‧第二晶粒/最頂部半導體晶粒
107‧‧‧安裝表面
108‧‧‧基底區域
110‧‧‧周邊區域
112‧‧‧堆疊/晶粒堆疊
114‧‧‧導熱殼體/蓋
116‧‧‧帽部分
118‧‧‧壁部分
120a‧‧‧第一接合材料
120b‧‧‧第二接合材料
121‧‧‧介電質底部填充材料/底部填充材料
122a‧‧‧第一積體電路
122b‧‧‧第二積體電路
122c‧‧‧第三積體電路
124‧‧‧導電元件
126‧‧‧穿矽導通體
128a‧‧‧第一熱傳導結構
128b‧‧‧第二熱傳導結構
130‧‧‧電容器
132‧‧‧接合墊
132‧‧‧接合墊
134‧‧‧導電元件
202‧‧‧安裝表面
204‧‧‧邊界/周界
206‧‧‧額外接合墊
300‧‧‧半導體晶圓/晶圓
402‧‧‧電功能體積/層/經垂直堆疊矽體積/體積
404‧‧‧電容器
406‧‧‧穿矽導通體
408a‧‧‧第一導電材料
408b‧‧‧第二導電材料
410‧‧‧絕緣/介電質材料
420‧‧‧電功能熱傳導結構/熱傳導結構
422‧‧‧經垂直堆疊矽體積/體積
424‧‧‧接合墊
426a‧‧‧第一導電材料
426b‧‧‧第二導電材料
428‧‧‧介電質材料
500‧‧‧半導體裝置組件/組件
502‧‧‧支撐基板
504‧‧‧第一半導體晶粒/第一晶粒
506‧‧‧第二半導體晶粒
508‧‧‧蓋
510‧‧‧帽部分
512‧‧‧壁部分
514a‧‧‧第一電功能熱傳導結構/第一熱傳導結構/熱傳導結構
514b‧‧‧第二熱傳導結構
516‧‧‧電容器
518‧‧‧電阻器
520‧‧‧接合墊
600‧‧‧半導體裝置組件/組件
602‧‧‧支撐基板
604‧‧‧第一半導體晶粒
606‧‧‧第二半導體晶粒
608‧‧‧蓋
610‧‧‧帽部分
612‧‧‧壁部分
614a‧‧‧第一電功能熱傳導結構/第一熱傳導結構
614b‧‧‧第二熱傳導結構
616‧‧‧電容器
618‧‧‧二極體
622‧‧‧接合墊
624‧‧‧接合墊
700‧‧‧系統
702‧‧‧半導體裝置組件
704‧‧‧電源
706‧‧‧驅動器
708‧‧‧處理器
710‧‧‧子系統/組件
h1‧‧‧高度
h2‧‧‧高度
圖1A及圖1B分別係展示具有根據本技術之一實施例組態之電功能熱傳導結構之一半導體裝置組件的剖面圖及部分分解剖面圖。 圖2係圖1A及圖1B之半導體裝置組件之一俯視平面圖。 圖3A及圖3B係根據本技術之一實施例之已自一半導體晶圓裂解之電功能熱傳導結構的俯視平面圖。 圖4A及圖4B係根據本技術之實施例組態之電功能熱傳導結構之剖面圖。 圖5及圖6係展示具有根據本技術之實施例組態之電功能熱傳導結構之半導體裝置組件的剖面圖。 圖7係展示包含根據本技術之一實施例組態之一半導體晶粒組件之一系統之一示意圖。

Claims (20)

  1. 一種半導體裝置組件，其包括： 一第一半導體晶粒，其包含具有一基底區域及毗鄰該基底區域之一周邊區域之一安裝表面； 至少一個第二半導體晶粒，其在該基底區域處電耦合至該第一半導體晶粒；及 一電功能熱傳導結構(HTS)，其在該周邊區域處電耦合至該第一半導體晶粒。
  2. 如請求項1之半導體裝置組件，其中該第一半導體晶粒包含一積體電路，且其中該HTS電耦合至該積體電路。
  3. 如請求項1之半導體裝置組件，其進一步包括具有一帽部分之一蓋，且其中該HTS經由一介入材料與該帽部分間接接觸。
  4. 如請求項3之半導體裝置組件，其中該蓋進一步包含一壁部分，且其中該HTS位於接近於該壁部分處。
  5. 如請求項1之半導體裝置組件，其中該HTS包含多個經堆疊矽體積。
  6. 如請求項1之半導體裝置組件，其中該HTS包含一電容器。
  7. 如請求項1之半導體裝置組件，其中該HTS包含形成一電容器之複數個矽體積。
  8. 如請求項1之半導體裝置組件，其進一步包括具有一帽部分及一壁部分之一蓋，其中該至少一個第二半導體晶粒包含複數個經垂直堆疊第二半導體晶粒，且其中該HTS位於該第一半導體晶粒與該帽部分之間及該複數個第二半導體晶粒與該壁部分之間。
  9. 一種半導體裝置組件，其包括： 一封裝基板； 一半導體晶粒，其安裝至該封裝基板且具有一基底區域、毗鄰於該基底區域之一周邊區域及一積體電路； 一半導體晶粒堆疊，其安裝至該半導體晶粒之該基底區域；及 一電功能熱傳導結構(HTS)，其安裝至該半導體晶粒之該周邊區域且包含至少一個電構件，其中該電構件電耦合至該半導體晶粒之該積體電路。
  10. 如請求項9之半導體裝置組件，其進一步包括具有一帽部分及一壁部分之一蓋，其中該蓋經由該壁部分安裝至該封裝基板，且其中該HTS自該半導體晶粒延伸至毗鄰於該帽部分且與該帽部分接觸之一位置。
  11. 如請求項10之半導體裝置組件，其中該HTS與該帽部分之間的該接觸係直接接觸。
  12. 如請求項10之半導體裝置組件，其中該HTS與該帽部分之間的該接觸係經由一介入材料進行之間接接觸。
  13. 如請求項9之半導體裝置組件，其進一步包括安裝至支撐基板之一蓋，其中該電構件係一電容器，且其中該HTS經定位以將由該電容器產生之熱傳導至該蓋。
  14. 如請求項9之半導體裝置組件，其中該電構件係一電容器，且其中該HTS包含形成該電容器之複數個矽體積。
  15. 如請求項9之半導體裝置組件，其中該電構件係一電阻器。
  16. 一種半導體裝置組件，其包括： 一支撐基板； 一第一半導體晶粒，其安裝至該支撐基板，其中該第一半導體晶粒包含： 一基底區域；一周邊區域，其毗鄰於該基底區域；一第一積體電路；及一第二積體電路；一晶粒堆疊，其包含複數個第二半導體晶粒，其中該晶粒堆疊在該基底區域處安裝至該第一半導體晶粒，且電耦合至該第一積體電路；及 一電功能熱傳導結構(HTS)，其安裝至該周邊區域且電耦合至該第二積體電路。
  17. 如請求項16之半導體裝置組件，其中該HTS包含複數個矽體積及至少一對接合墊，且其中該等接合墊提供至至少部分地經由該等矽體積形成之一電容性電路徑之一電連接。
  18. 如請求項16之半導體裝置組件，其中該HTS包含形成一電容器之複數個矽體積。
  19. 如請求項16之半導體裝置組件，其進一步包括安裝至該支撐基板之一蓋，其中該HTS經定位以將熱傳導至該蓋。
  20. 如請求項19之半導體裝置組件，其中該HTS經由一介入材料與該蓋間接接觸。
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