TW201839990A - 半導體元件、鰭式場效電晶體元件及半導體元件的製造方法 - Google Patents

半導體元件、鰭式場效電晶體元件及半導體元件的製造方法 Download PDF

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TW201839990A
TW201839990A TW106142791A TW106142791A TW201839990A TW 201839990 A TW201839990 A TW 201839990A TW 106142791 A TW106142791 A TW 106142791A TW 106142791 A TW106142791 A TW 106142791A TW 201839990 A TW201839990 A TW 201839990A
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layer
type well
semiconductor layer
effect transistor
field effect
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TW106142791A
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TWI662702B (zh
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鄭銘龍
林彥君
林大文
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台灣積體電路製造股份有限公司
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    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
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Abstract

一種半導體元件，包含P型與N型場效電晶體。P型場效電晶體包含位於基板中之N型井、位於N型井上方之第一鰭結構、位於N型井上方之第一襯墊層以及位於第一襯墊層上方之第二襯墊層。第一襯墊層和第二襯墊層包含不同材料組成。N型場效電晶體包含位於基板中之P型井、位於P型井上方之第二鰭結構以及位於P型井上方之第三襯墊層。第三襯墊層和第二襯墊層包含相同材料組成。

Description

具有用於P型場效電晶體和N型場效電晶體的不同襯墊層的鰭式場效電晶體元件及其製造方法
半導體產業已進展至奈米科技，進而追求更高元件密度、更佳效能，以及更低價格之製程節點。於此進展下，來自製造及設計之挑戰促使立體設計諸如鰭式場效電晶體元件之發展。典型鰭式場效電晶體元件係利用薄”鰭”(或是一類似鰭狀之結構)自基板中延伸出以製造。鰭通常包含基矽，並構成電晶體元件主體。電晶體通道於垂直鰭中形成。閘極則位於鰭上方(如環繞包覆鰭)。此種類型之閘極能使電晶體通道得到更好控制。鰭式場效電晶體元件其他優勢包含減少短通道效應(short channel effect)以及提供更高電流等。
然而，典型鰭式場效電晶體元件仍具有相當缺陷。舉例說明，典型鰭式場效電晶體元件中的淺溝槽隔離襯墊無法使鰭式場效電晶體元件表現最佳化。
因此，雖然現有鰭式場效電晶體元件及其製造方法對於特定用途使用大致足夠，然而仍無法完全滿足每一面向。
50‧‧‧鰭式場效電晶體元件
60‧‧‧閘極
60A‧‧‧閘極電極零組件
60B‧‧‧閘極介電質零組件
70‧‧‧源極
80‧‧‧汲極
100‧‧‧鰭式場效電晶體元件
110‧‧‧N型井
110A‧‧‧受到蝕刻之N型井段
110B‧‧‧未受到蝕刻之N型井段
120‧‧‧P型井
120A‧‧‧受到蝕刻之P型井段
120B‧‧‧未受到蝕刻之P型井段
130‧‧‧半導體層
130A‧‧‧位於N型井上方之半導體層
130B‧‧‧位於P型井上方之半導體層
140‧‧‧半導體層厚度
150‧‧‧介電質層
150A‧‧‧圖案化硬遮罩
160‧‧‧介電質層厚度
170‧‧‧圖案化光阻層
190‧‧‧位於N型井上方之半導體層130A厚度
200‧‧‧半導體層
210‧‧‧半導體層厚度
220‧‧‧電晶體元件100之平坦頂面
230‧‧‧覆蓋層
240‧‧‧覆蓋層厚度
270‧‧‧介電質層
280‧‧‧介電質層
290‧‧‧OD圖案化製程
295‧‧‧鰭結構
300‧‧‧沉積製程
310‧‧‧含氮化物襯墊層
320‧‧‧含氮化物襯墊層厚度
330‧‧‧圖案化光阻層
350‧‧‧蝕刻製程
400‧‧‧沉積製程
410‧‧‧含氧化物襯墊層
420‧‧‧含氧化物襯墊層厚度
450‧‧‧鰭結構295間之間隙或溝槽
500‧‧‧介電質隔離結構
600‧‧‧鰭凹部製程
900‧‧‧製造鰭式場效電晶體元件方法
910、920、930、940、950、960‧‧‧步驟
LG‧‧‧閘極60位於X軸方向上之長度
tox‧‧‧閘極介電質零組件60B在Y軸方向厚度
Wfin‧‧‧鰭在Y軸方向上之寬度
X、Y、Z‧‧‧軸向
閱讀以下詳細敘述並搭配對應圖式，可理解本揭露多個樣態。應強調的是，為與產業標準實務一致，多數構造特徵並未依比例畫製，且僅以敘述用途。事實上，可以任意方式增大或縮少其維度，以為明確討論。
第1圖繪示鰭式場效電晶體元件之透視圖實例。
第2至第17圖繪示根據本揭露之多個實施例之不同製造階段下鰭式場效電晶體元件之剖面圖。
第18圖繪示根據本揭露之多個實施例之製造鰭式場效電晶體元件方法之流程圖。
以下揭示內容提供許多不同實施例或示例，用於實施本揭露之不同特徵。下文描述組件及排列之特定實例以簡化本揭露書的內容。當然，該等實例僅為示例且並不意欲為限制性。舉例而言，以下描述中在第二特徵上方或第二特徵上形成第一特徵可包括以直接接觸形成第一特徵及第二特徵的實施例，且亦可包括可在第一特徵與第二特徵之間形成額外特徵以使得第一特徵及第二特徵可不處於直接接觸的實施例。另外，本揭露可在各實例中重複元件符號及/或字母。此重複本身並不指示所論述之各實施例及/或配置之間的關係。
進一步地，為了便於描述，本文可使用空間相對性用語(諸如「之下」、「下方」、「下部」、「上方」、 「上部」及類似者)來描述諸圖中所圖示一個元件或特徵與另一元件(或多個元件)或特徵(或多個特徵)之關係。除了諸圖所描繪之定向外，空間相對性用語意欲包含元件在使用或操作中之不同定向。裝置可經其他方式定向(旋轉90度或處於其他定向)且因此可同樣解讀本文所使用之空間相對性描述詞。
本揭露指向鰭式場效電晶體元件，但不以其他方式限定之。舉例來說，鰭式場效電晶體元件可為互補式金屬氧化物半導體元件，包含P型和N型金屬氧化物半導體鰭式場效電晶體元件。下述揭露續行一或多個鰭式場效電晶體實例來闡述本揭露之多個實施例。然而應理解到除特定主張外，應用端並不限定於元件之特定型式。
半導體產業中，鰭式場效電晶體元件之使用愈來愈受到歡迎。請參閱第1圖，係鰭式場效電晶體元件50之透視圖實例之繪示。鰭式場效電晶體元件50係一建立於基板(如塊狀基板)上方之非平面多閘極電晶體。含有矽之薄鰭狀結構(以下稱為鰭)，構成鰭式場效電晶體元件50之主體。如第1圖所繪示，鰭沿X軸方向延伸出。鰭在和X軸方向正交之Y軸方向上的寬度為Wfin。鰭式場效電晶體元件50之閘極60環繞包覆鰭，例如環繞包覆鰭之頂面和兩對立的側壁表面。因此，部分閘極60位於鰭之上方，而鰭方向係位於與X軸方向和正Y軸方向正交之Z軸方向上。
LG表示閘極60位於X軸方向上之長度(或者為寬度，取決於視角)。閘極60可包含閘極電極零組件60A和 閘極介電質零組件60B。閘極介電質零組件60B在Y軸方向厚度為tox。一部分的閘極60位於如淺溝槽隔離等介電質隔離結構上方。鰭式場效電晶體元件50之源極70和汲極80位於鰭之延伸上，而形成於閘極60之兩個對立側。被閘極60環繞包覆的一部份的鰭，係作為鰭式場效電晶體元件50之通道。鰭之維度決定鰭式場效電晶體元件50之有效通道長度。
對比金屬氧化物半場效電晶體元件(又稱作平面電晶體元件)來說，鰭式場效電晶體元件提供多種優勢。此些優勢包含較佳晶片面積利用效率、提高載子移動率，以及和平面元件製程相容的製程等等。鰭式場效電晶體元件亦和高介電常數金屬閘極製造流程相容。因此，鰭式場效電晶體可作為執行高介電常數金屬閘極之元件，其中每一閘極皆具有高介電常數閘極介電質和金屬閘極電極。上述優勢使得以鰭式場效電晶體元件來設計部分或整體之積體電路係為有利的。
然而，典型鰭式場效電晶體元件之製造方法仍具有缺陷。舉例來說，典型鰭式場效電晶體元件可能使用相同淺隔離結構襯墊材料以製造N型和P型場效電晶體。此種方法無法使鰭式場效電晶體表現最佳化。為改善鰭式場效電晶體元件表現，本揭露利用雙重淺隔離結構襯墊，以同步改善N型和P型場效電晶體表現，並請參閱第2至第18圖，將於下述作進一步討論。
第2至第17圖係為零碎圖示，繪示不同製造階段下鰭式場效電晶體元件100之剖面圖。請參閱第2圖，鰭式場效電晶體元件100包含N型井110和P型井120，兩者皆於基板中形成。基板可為半導體基板，如矽基板。N型井110和P型井 120可利用一或多個離子植入製程以形成，及利用不同摻雜以具有不同導電型式。在一些實施例中，摻雜離子可包含n型材料，如使用砷或磷；在其他實施例中，亦可包含p型材料，如使用硼，而摻雜離子之使用取決於欲製造N型或P型場效電晶體。
半導體層130形成於N型井和P型井上方。在一些實施例中，半導體層130包含矽。半導體層130之矽材料可以磊晶長於N型井110和P型井120上方。半導體層130可磊晶至一厚度140。在一些實施例中，此厚度140介於範圍約30奈米至約70奈米之間。一部分的半導體層130(於執行圖案化製程後)可作為鰭式場效電晶體100之N型場效電晶體(又可稱作N型金屬氧化物半導體)的鰭，並於下述作進一步討論。
請參閱第3圖，介電質層150形成於半導體層130上方。在一些實施例中，介電質層150包含如氧化矽等氧化物材料。介電質層150可利用沉積製程，如化學汽相沉積、物理汽相沉積、原子層沉積，或上述混合方式以形成。介電質層150可沉積至一厚度160。在一些實施例中，此厚度160介於範圍約10奈米至約20奈米之間。介電質層150可在下述圖案化製程中作為硬遮罩使用。
請參閱第4圖，圖案化光阻層170形成於介電質層150上方。在一些實施例中，圖案化光阻層170可利用如光阻塗佈(如光阻旋轉塗佈)、曝光、曝後烤(post-exposure baking)、顯影，以及清洗等一或多個製程以形成。光阻材料的剩餘部分經顯影後，可形成圖案化光阻層170。如第4圖所 繪示，圖案化光阻層170形成於P型井上方，而非位形成於N型井上方。換句話說，圖案化光阻層170和P型井120垂直排列(如於第1圖所繪示之Z軸方向)，而非和N型井垂直排列。
請參閱第5圖，利用圖案化光阻層170圖案化介電質層150，以形成圖案化硬遮罩150A。接著，使用如光阻剝除製程或光阻灰化製程以移除圖案化光阻層170。利用圖案化硬遮罩150A作為保護罩下，執行蝕刻製程以侵蝕一部分的半導體層130。換句話說，圖案化硬遮罩150A保護一部分的半導體層130(130B)及其下方免於蝕刻製程中受到侵蝕，而未受硬遮罩150A保護的一部分的半導體層130則被移除。
如第5圖所繪示，執行蝕刻製程的方式為使一部分的半導體層130(130A)仍保持於N型井110上方。一部分的半導體層130A和半導體層130的剩餘部分具有相同材料組成(如兩者皆含矽)，係因一部分的半導體層130A為半導體層130的一部分。一部分的半導體層130A具有厚度190。在一些實施例中，此厚度190介於範圍約2奈米至約8奈米之間。保留一部分的半導體層130A的其中一原因，係為使後續製程中具有較好的矽化鍺磊晶。舉例來說，一部分的半導體層130A可用以隔離N型井和於後續長於半導體層130上方之矽化鍺材料。
請參閱第6圖，半導體層200形成於一部分的半導體層130A上方。半導體層200和半導體層130具有不同材料組成。舉例來說，在一些實施例中，半導體層200包含矽化鍺。半導體層200可以磊晶形成。如上述討論，由於一部分半導體層130A存在關係，使半導體層不直接形成於N型井上，而形成 於一部分的半導體層130A上。一部分的半導體層130A可隔離N型井110和半導體層200，使半導體層200於較好磊晶品質下形成。半導體層200可磊晶至厚度210。在一些實施例中，此厚度210介於範圍約40奈米至約60奈米之間。半導體層200可作為鰭式場效電晶體元件100之P型場效電晶體(又可稱作P型金屬氧化物半導體)的鰭，並於下述作進一步討論。
請參閱第7圖，利用拋光製程如化學機械研磨製程，以移除圖案化硬遮罩150A。化學機械研磨製程亦可用以移除一部分的半導體層200和一部分的半導體層130B。拋光製程的結果，可使鰭式場效電晶體元件100具有足夠平坦的頂面220。
請參閱第8圖，覆蓋層230形成於半導體層200和一部分的半導體層130B的平坦的頂面220上。在一些實施例中，覆蓋層230包含矽，因此也可稱作矽覆蓋層。覆蓋層230具有厚度240。在一些實施例中，此厚度240介於範圍約0.5奈米至約5奈米之間。覆蓋層230可保護半導體層200免於不希望的氧化。舉例來說，半導體層200中之矽化鍺材料曝露於大氣中(含氧)易於氧化，而此不希望的氧化對矽化鍺材料之特定功能(如作為半導體材料)將產生不利之影響。覆蓋層230之形成可避免半導體層200曝露於大氣中，因而避免半導體層200之矽化鍺材料造成潛在氧化。覆蓋層230將在後續製程中移除。
請參閱第9圖，介電質層270形成於覆蓋層230上方。在一些實施例中，介電質層270包含氧化矽，因而也可稱作墊氧化物層270。接著，介電質層280形成於介電質層280 上方形成於介電質層270上方。在一些實施例中，介電質層280包含氮化矽，因而也可稱作墊氮化物層280。介電質層270和介電質層280可作為硬遮罩之材料，以進行後續光微影圖案化製程。
請參閱第10圖，執行OD(主動區)圖案化製程290以形成向上突出(如於第1圖所繪示，向上之Z軸方向)的鰭結構295。於OD圖案化製程290中，將介電質層270和介電質層280圖案化(如利用圖案化光阻層)以形成圖案化硬遮罩，可界定鰭結構295之橫向維度。接著，圖案化硬遮罩270/280用以圖案化下方各層。舉例來說，未受硬遮罩270/280保護之一部分的層230、200、130B、N型井110以及P型井120，將於一或多個蝕刻製程中受到侵蝕。可見的是，N型井110受到蝕刻，使110A段突出自未受到蝕刻之110B段；P型井120受到蝕刻，使120A段突出自未受到蝕刻之120B段。可理解的是，110A和110B具有相同材料組成，120A和120B具有相同材料組成。然而，110A段和110B段之間的摻雜濃度程度可不相同，120A段和120B段之間的摻雜濃度也可不相同。舉例來說，110B段相較110A段具有較低摻雜濃度程度，120B段相較120A段具有較低摻雜濃度程度。層230、200的剩餘部分、一部分的半導體層130A，以及向上突出之N型井110A段，共同組成P型場效電晶體之鰭結構295；而半導體層130B的剩餘部分和向上突出之P型井120A段，共同組成N型場效電晶體之鰭結構295。N型和P型場效電晶體的通道和源極/汲極區可形成於鰭結構295內，如於半導體層200和部分半導體層130B內。
請參閱第11圖，執行沉積製程300以形成含氮化物襯墊層310於每一鰭結構295之頂面和側表面上。在一些實施例中，沉積製程300包含化學汽相沉積製程，沉積溫度介於範圍約550度攝氏溫度和約950度攝氏溫度之間。舉例來說，在P型場效電晶體中，含氮化物襯墊層310形成於半導體層200之側壁表面以及N型井110A段之側壁表面上。在一些實施例中，含氮化物襯墊層310和半導體層200之側壁表面以及N型井110A段之側壁表面實際接觸。在一些實施例中，含氮化物襯墊層310可包含氮化矽材料。含氮化物襯墊層310可沉積至厚度320。在一些實施例中，執行沉積製程300，可使此厚度320介於範圍約2奈米至約5奈米之間。
襯墊層310之氮化矽材料可避免半導體層200中之矽化鍺材料曝露於大氣中的氧氣。如上述討論，矽化鍺易於產生不希望的氧化。於上述第10圖之討論，執行OD圖案化製程290後，鰭結構295中之半導體層200(含矽化鍺)之側壁會曝露出來。若無採取任何措施，半導體層200曝露於大氣中將使半導體層200內之矽化鍺氧化，進而降低元件表現。
為抑制半導體層200氧化，本揭露形成含氮化物襯墊層310(如含氮化矽)於半導體層之側壁上，以避免半導體層200曝露於大氣中。含氮化物襯墊層310的存在可降低半導體層200發生不利的氧化之可能性。含氮化物襯墊層厚度320亦可用以使含氮化物襯墊層310功能最佳化，例如防止半導體層200氧化。可理解的是，雖然氮化矽係用以含氮化物襯墊層 310的一實施例材料，若其他適宜材料亦可用以防止半導體層200中矽化鍺氧化，則可同樣使用於含氮化物襯墊層310。
應注意含氮化物襯墊層310亦形成於N型場效電晶體之鰭結構295之上。然而，因其實屬非必要，而將於後續製程中移除N型場效電晶體中的含氮化物襯墊層310。
請參閱第12圖，形成圖案化光阻層330係用以罩住鰭式場效電晶體元件100之P型場效電晶體，而使N型場效電晶體曝露出來。換句話說，圖案化光阻層330形成於N型井110B上方的鰭結構295上方，而非形成於P型井120B上方的鰭結構295上方。因此，圖案化光阻層330罩住P型場效電晶體之含氮化物襯墊層310段，而N型場效電晶體之含氮化物襯墊層310段則曝露出來。圖案化光阻層330可於沉積、曝光、顯影，以及烘烤等製程(非必然以此順序執行)中形成。
請參閱第13圖，對鰭式場效電晶體元件100執行蝕刻製程350以移除鰭式場效電晶體元件100中N型場效電晶體的一部分的含氮化物襯墊層310。圖案化光阻層330保護含氮化物襯墊層310及其下免於蝕刻製程350中受到侵蝕。因此，P型場效電晶體中一部分的含氮化物襯墊層310保持完整，未於蝕刻製程350中移除。然而，因N型場效電晶體之一部分的含氮化物襯墊層310並未受到圖案化光阻330之保護而為移除，因而使N型場效電晶體的鰭結構295之頂面和側壁表面曝露出來。舉例來說，半導體層130B之側壁表面和P型井120A段之側壁表面皆曝露出來。
請參閱第14圖，利用光阻剝除製程或光阻灰化製程以移除圖案化光阻層330。移除圖案化光阻層330使含氮化物襯墊層310(包覆P型場效電晶體之鰭結構295)曝露出來。
請參閱第15圖，執行沉積製程400以形成含氧化物襯墊層410於每一鰭結構295之頂面和側表面上。在一些實施例中，沉積製程400包含化學汽相沉積製程，沉積溫度介於範圍約550度攝氏溫度和約950度攝氏溫度之間。舉例來說，在P型場效電晶體中，含氧化物襯墊層410形成於含氮化物襯墊層310上。在一些實施例中，含氧化物襯墊層410和含氮化物襯墊層310實際接觸。在N型場效電晶體中，含氧化物襯墊層410形成於半導體層130B之側壁表面和P型井120A段之側壁表面上。在一些實施例中，含氧化物襯墊層410與半導體層130B之側壁表面和P型井120A段之側壁表面實際接觸。
在一些實施例中，含氧化物襯墊層410可包含氧化矽材料。在一些實施例中，含氧化物襯墊層410可包含氧化鋁材料。含氧化物襯墊層410可沉積至厚度420。在一些實施例中，執行沉積製程300，可使此厚度420介於範圍約2奈米至約5奈米之間。
含氧化物襯墊層410之氧化矽材料可提供應力。舉例來說，因N型場效電晶體之通道形成於半導體層130B中，使含氧化物襯墊層410接近(或實際接觸)半導體層130B，可能對N型場效電晶體之通道提供拉伸應力。受到應力之通道可能導致效能改善，例如加速載子移動率，因此可能是需要的。雖然氮化物襯墊層(如含氮襯墊層310)亦可對N型場效電晶體之 通道造成應力(若以含氮化物襯墊成310取代含氧化物襯墊層410)，然而氮化物材料無法提供和氧化物所能提供同樣多之應力。此外，氮化物材料可帶正電。正電造成N型場效電晶體易開啟，此非為所希望的。再者，若N型場效電晶體易開啟，則可能誘發高漏電。因此，使接近N型場效電晶體之襯墊層保持電中性(如不帶電)或帶負電係為所希望的。
基於上述討論理由，含氧化物襯墊層410之材料組成係用以對N型場效電晶體提供應力，並同時保持電中性或帶正電。氧化矽材料或氧化鋁材料組成可符合此些條件，因此在不同實施例中，含氧化物襯墊層410可包含氧化矽、氧化鋁，或上述混合材料。應注意於第15圖繪示之製造階段下，鰭結構295間存在複數間隙或溝槽450。此些間隙或溝槽450，將於下述討論製程中被填滿。
請參閱第16圖，利用沉積製程如熔爐化學汽相沉積(Furnace Chemical Vapor Deposition,FCVD)形成介電質隔離結構500。介電質隔離結構500係用以填充介於鰭結構295間之間隙或溝槽450。在一些實施例中，介電質隔離結構500可包含淺溝槽隔離。介電質隔離結構500可包含如氧化矽等氧化物材料。在介電質隔離結構形成前或後，可執行拋光製程如化學機械研磨以移除介電質層270和介電質層280(以及一部分的介電質隔離結構500)。拋光製程亦可移除P型場效電晶體的鰭結構295之覆蓋層230。
請參閱第17圖，對鰭式場效電晶體元件100執行鰭凹部製程600，以選擇性地移除P型和N型場效電晶體兩者 一部分的含氧化物襯墊層410，亦可選擇性地移除P型場效電晶體的一部分的含氮化物襯墊層310。進一步詳述，移除N型場效電晶體的一部分的含氧化物襯墊層410，可使半導體層130B包含其頂面和側壁表面曝露出來。同樣地，移除P型場效電晶體的一部分的含氧化物襯墊層410，和一部分的含氮化物襯墊層310，可使半導體層200包含其頂面和側壁表面曝露出來。於鰭凹部製程600中，亦移除一部分的介電質隔離結構500，使半導體層200和半導體層130B之側表面曝露出來。
於此同時，鰭凹部製程600實質上不影響半導體層200和半導體層130B以外的一部分的襯墊層310和襯墊層410。舉例來說，在執行鰭凹部製程後，含氮化物襯墊層310仍保持於N型井110A段和130A之側壁表面，以及N型井110B段之頂面上。含氧化物襯墊層410亦同樣保持於P形場效電晶體之含氮化物襯墊層310上。對於N型場效電晶體來說，含氧化物襯墊層410保持於P型井120A段之側壁表面，以及P型井120B之頂面上。如第17圖之剖面圖繪示，含氧化物襯墊層410環繞包覆介電質隔離結構500之側表面及底面。因本揭露中，N型和P型場效電晶體使用不同襯墊層，可據此稱本揭露中之鰭式場效電晶體元件100為一「雙重襯墊」元件。
在一些實施例中，鰭凹部製程600包含一或多個蝕刻製程，如乾式蝕刻、濕式蝕刻，以及反應式離子蝕刻等等。藉調控不同蝕刻參數，以選擇性地蝕刻襯墊層310和襯墊層410欲蝕刻的量(如洽使半導體層200和半導體層130B曝露出來)。此些蝕刻參數可包含蝕刻劑組成物、蝕刻溫度、蝕刻溶 液濃度、蝕刻時間、蝕刻壓力、電源功率、射頻偏壓電壓、射頻偏壓功率、蝕刻劑流速，或上述混合參數，然不易欲限定之。
第18圖繪示根據本揭露之多個面向之製造鰭式場效電晶體元件方法900之流程圖。製造鰭式場效電晶體元件方法900包含步驟910，形成第一導電層於N型井上方。在一些實施例中，第一導電層的形成包含以矽化鍺磊晶作為N型井上方之第一導電層。
製造鰭式場效電晶體元件方法900包含步驟920，形成第二導電層於P型井上方。在一些實施例中，第二導電層的形成包含以矽磊晶作為P型井上方之第二導電層。在一些實施例中，第二導電層早於第一導電層之前形成。在一些實施例中，執行矽磊晶，使矽長於N型井和P型井上方。在一些實施例中，於形成第二半導體層後，但於形成第一半導體層前，移除位於N型井上方的一部分的第二半導體層。在移除一部分的第二半導體層後，將第一半導體層磊晶長於位於N型井上方之第二半導體的剩餘部分上方。
製造鰭式場效電晶體元件方法900包含步驟930，執行圖案化製程，以形成第一鰭結構和第二鰭結構。第一鰭結構包含一部分的第一半導體層和一部分的N型井，而第二鰭結構包含一部分的第二半導體層和一部分的P型井。
製造鰭式場效電晶體元件方法900包含步驟940，形成第一襯墊層於第一鰭結構、第二鰭結構，以及P型井上方。在一些實施例中，第一襯墊層的形成包含以含氮化物 襯墊層作為第一襯墊層。在一些實施例中，含氮化物襯墊層包含氮化矽。
製造鰭式場效電晶體元件方法900包含步驟950，選擇性地移除第一襯墊層，使位於第二鰭結構和P型井上方之第一襯墊層被移除。形成於於第一鰭結構和N型井上方的第一襯墊層的剩餘部分並不受選擇性移除所影響。
製造鰭式場效電晶體元件方法900包含步驟960，形成第二襯墊層於第二鰭結構、P型井，以及第一襯墊層的剩餘部分上方。第二襯墊層和第一襯墊層具有不同材料組成。在一些實施例中，第二襯墊層的形成包含形成含氧化物襯墊層作為第二襯墊層。在一些實施例中，含氧化物襯墊層包含氧化矽。
在一些實施例中，製造鰭式場效電晶體元件方法900進一步包含移除位於第一半導體層上方的一部分的第一襯墊層和第二襯墊層，以及移除位於第二半導體層上方的一部分的第二襯墊層等步驟。
可理解的是，附加製程步驟可於上述步驟910至960之製造前、後、或期間實施，以完成半導體元件之製造。舉例來說，製造鰭式場效電晶體元件方法900可進一步執行製程以形成閘極結構。閘極結構可使用「先閘極」或「後閘極」等製程以形成。製造鰭式場效電晶體元件方法900亦可進一步包含形成源極/汲極結構以及層間介電層等步驟。此外，可形成包含導電觸點(conductive contacts)、導電通孔(vias)，以 及互連線等互連結構。再者，亦可執行測試和封裝步驟以完成積體電路之製造。
基於上述討論，可見本揭露之鰭式場效電晶體及其製作方法相較典型鰭式場效電晶體更具優勢。然而，可理解的是，其他實施例可提供附加優勢，而本揭露非必然揭示所有優勢，且並非所有實施例皆需要特定優勢。其一優勢為，藉由含氮化物襯墊層的使用，本揭露可減少或免於P型場效電晶體中矽化鍺材料發生不利的氧化。其他優勢為，藉由含氧化物襯墊層的使用，本揭露可對N型場效電晶體之通道增加應力。而含氧化物襯墊層亦非帶正電，意指可使N型場效電晶體不易開啟。基於此些理由，可改善鰭式場效電晶體元件表現。此外，本揭露之不同面向可和現行製程流程相容且易於執行。
本揭露之一實施例包含半導體元件。半導體元件包含P型場效電晶體，其包含：位於基板中之N型井；位於N型井上方之第一鰭結構；位於N型井上方之第一襯墊層；以及位於第一襯墊層上方之第二襯墊層，其中第一襯墊層和第二襯墊層具有不同材料組成。半導體元件亦包含N型場效電晶體，其包含：位於基板中之P型井；位於P型井上方之第二鰭結構；位於P型井上方之第三襯墊層，其中第三襯墊層和第二襯墊層具有相同材料組成。在一些實施例中，第一鰭結構包含矽化鍺層；第二鰭結構包含矽層；第一襯墊層包含用以使矽化鍺層免於氧化之材料；以及第二襯墊層包含用以對N型場效電晶體提供應力之材料。在一些實施例中，第一襯墊層包含含氮化物材料；第二襯墊層包含含氧化物材料；以及第三襯墊層包含含氧 化物材料。在一些實施例中，第一襯墊層包含氮化矽，而第二襯墊層和第三襯墊層皆包含氧化矽。在一些實施例中，第一襯墊層和第二襯墊層皆未位於矽化鍺層之側壁上，第三襯墊層並非位於矽層之側壁上。在一些實施例中，一部分的第一襯墊層位於N型井之側表面上，一部分的第二襯墊層位於P型井之側表面上。在一些實施例中，半導體元件進一步包含：位於P型和N型場效電晶體之間之介電質隔離結構，其中於一側剖面圖中可見第二襯墊層和第三襯墊層環繞包覆介電質隔離結構。
本揭露之另一實施例包含鰭式場效電晶體元件。鰭式場效電晶體元件包含P型場效電晶體，其包含：形成於基板中之N型井，其中N型井包含第一部分及自第一部分突出之第二部分；位於N型井第二部分上方之第一半導體層，其中第一半導體層包含矽化鍺；位於N型井上方但非位於第一半導體層上方之第一襯墊層，其中第一襯墊層包含使矽化鍺免於氧化之材料；以及位於第一襯墊層上方之第二襯墊層之第一段，其中第二襯墊層包含可對矽提供應力之材料。鰭式場效電晶體元件亦包含N型場效電晶體，其包含：形成於基板中之P型井，其中P型井包含第一部分及自第一部分突出之第二部分；位於P型井第二部分上方之第二半導體層，其中第二半導體層包含矽；以及位於P型井上方但非位於第二半導體層上方之第二襯墊層之第二段。在一些實施例中，第一襯墊層包含氮化矽，第二襯墊層之第一段和第二段皆包含氧化矽。在一些實施例中，第一襯墊層和N型井第一部分之側壁實際接觸，第二襯墊層之第二段和P型井第一部分之側壁實際接觸。在一些實施例中， 鰭式場效電晶體進一步包含：位於P型和N型場效電晶體間之介電質隔離結構。介電質隔離結構和第二襯墊層之第一段和第二段實際接觸。
本揭露之又一實施例包含製造半導體元件方法。此方法包含：形成第一半導體層於N型井上方；形成第二半導體層於P型井上方；執行圖案化製程以形成第一鰭結構和第二鰭結構，其中第一鰭結構包含一部分的第一半導體層和一部分的N型井，而第二鰭結構包含一部分的第二半導體層和一部分的P型井；形成第一襯墊層於第一鰭結構、N型井、第二鰭結構，以及P型井上方；選擇性地移除第一襯墊層，以移除形成於第二鰭結構和P型井之上方之第一襯墊層，其中形成於第一鰭結構和N型井上方之第一襯墊層的剩餘部分並不受選擇性移除步驟所影響；以及選擇性地移除第一襯墊層後，形成第二襯墊層於第二鰭結構、P型井，以及第一襯墊層的剩餘部分上方，其中第二襯墊層和第一襯墊層具有不同材料組成。在一些實施例中，製造半導體元件方法進一步包含移除形成於第一半導體層上方的一部分的第一襯墊層和第二襯墊層，以及移除形成於第二半導體層上方的一部分的第二襯墊層等步驟。在一些實施例中，第一襯墊層之形成包含形成含氮化物層作為第一襯墊層。在一些實施例中，含氮化物層包含氮化矽。在一些實施例中，第二襯墊層之形成包含形成含氧化物層作為第二襯墊層。在一些實施例中，含氧化物層包含氧化矽。在一些實施例中，第一半導體層之形成包含以矽化鍺磊晶作為N型井上之第一半導體層；第二半導體層之形成包含以矽磊晶作為P型井上 之第二半導體層。在一些實施例中，第二半導體層早於第一半導體層形成，且執行矽磊晶將矽長於N型井和P型井上方。在一些實施例中，製造半導體元件方法進一步包含：形成第二半導體層後，但於形成第一半導體層前，移除一部分位於N型井上方之第二半導體層，其中在移除一部分的第二半導體層後，將第一半導體層磊晶長於位於N型井上方之第二半導體層的剩餘部分上方。
前述概述之一些實施例可使得所屬技術領域之專業人員更加理解本揭露之多個面向。所屬技術領域之專業人員應了解，可利用本揭露之製程和結構為各種變動或潤飾來實現及/或達到本說明書所述之實施例之相同目的及/或優點，亦應理解所為之各種變動或潤飾不應偏離本揭露之精神和範圍。

Claims (20)

  1. 一種半導體元件，包含：一P型場效電晶體，該P型場效電晶體包含：一N型井，該N型井位於一基板中；一隔離結構，該隔離結構位於該N型井上方；一第一鰭結構，該第一鰭結構位於該N型井上方，其中該第一鰭結構包含一下段和位於該下段上方之一上段，且其中該下段位於該隔離結構頂面下方；一第一襯墊層，該第一襯墊層位於該N型井上方且位於該第一鰭結構下段側壁之上；以及一第二襯墊層，該第二襯墊層位於該第一襯墊層上方，其中該第一襯墊層和該第二襯墊層包含不同材料；以及一N型場效電晶體，該N型場效電晶體包含：一P型井，該P型井位於該基板中；該隔離結構位於該P型井上方；一第二鰭結構，該第二鰭結構位於該P型井上方，其中該第二鰭結構包含一下段和位於該下段上方之一上段，且其中該下段位於該隔離結構頂面下方；以及一第三襯墊層，該第三襯墊層位於該P型井上方且位於該第二鰭結構下段側壁之上，其中該第三襯墊層和該第二襯墊層包含相同材料。
  2. 如請求項1所述之半導體元件，其中：該第一鰭結構包含一矽鍺層； 該第二鰭結構包含一矽層；該第一襯墊層包含一配置以防止該矽鍺層氧化之材料；以及該第二襯墊層包含一配置以提供應力予該N型場效電晶體之材料。
  3. 如請求項2所述之半導體元件，其中：該第一襯墊層包含一含氮化物材料；該第二襯墊層包含一含氧化物材料；以及該第三襯墊層包含該含氧化物材料。
  4. 如請求項3所述之半導體元件，其中：該第一襯墊層包含氮化矽；以及該第二襯墊層以及該第三襯墊層各自包含氧化矽。
  5. 如請求項2所述之半導體元件，其中：該第一襯墊層和該第二襯墊層皆未位於該矽鍺層之側壁上；以及該第三襯墊層並非位於該矽層之側壁上。
  6. 如請求項1所述之半導體元件，其中：一部分的該第一襯墊層位於該N型井之一側表面上；以及一部分的該第二襯墊層位於該P型井之一側表面上。
  7. 如請求項1所述之半導體元件，其中該隔離結構 包含一淺溝槽隔離，且其中於一側剖面圖中可見該第二襯墊層和該第三襯墊層環繞包覆該淺溝槽隔離。
  8. 一種鰭式場效電晶體元件，包含：一P型場效電晶體，該P型場效電晶體包含：一N型井，該N型井於一基板中形成，其中該N型井包含一第一部分和自該第一部分突出之一第二部分；一第一半導體層，該第一半導體層位於該N型井之該第二部分上方，其中該第一半導體層包含矽化鍺，且其中該N型井之該第二部分和該第一半導體層係該P型場效電晶體之一第一鰭結構的一部分；一第一襯墊層，該第一襯墊層位於該N型井之該第一部分上方，且位於該N型井之該第二部分側壁之上，但非位於該第一半導體層上方，其中該第一襯墊層包含一用以防止矽化鍺氧化之材料；以及一第二襯墊層之一第一段，該第一段位於該第一襯墊層上方，其中該第二襯墊層包含一用以提供應力予矽之材料；以及一N型場效電晶體，該N型場效電晶體包含：一P型井，該P型井於該基板中形成，其中該P型井包含一第一部分和自該第一部分突出之一第二部分；一第二半導體層，該第二半導體層位於該P型井之該第二部分上方，其中該第二半導體層包含矽，且其中該P型井之該第二部分和該第二半導體層係該N型場效電晶體之一第二鰭結構的一部分；以及 該第二襯墊層之一第二段，該第二段位於該P型井之該第一部分上方，以及位於該P型井之該第二部分一側壁上，但非位於該第二半導體層上方。
  9. 如請求項8所述之鰭式場效電晶體元件，其中：該第一襯墊層包含一氮化矽；以及該第二襯墊層之該第一段和該第二段各自包含氧化矽。
  10. 如請求項8所述之鰭式場效電晶體元件，其中：該第一襯墊層和該N型井的該第二部分的該側壁實際接觸；以及該第二襯墊層的該第二段和該P型井的該第二部分的該側壁實際接觸。
  11. 如請求項8所述之鰭式場效電晶體元件，進一步包含：一介電質隔離結構，該介電質隔離結構位於該P型和該N型場效電晶體之間，其中該介電質隔離結構係與該第二襯墊層之該第一段和該第二段實際接觸。
  12. 一種製造半導體元件方法，該方法包含：形成一第一半導體層於一N型井上方；形成一第二半導體層於一P型井上方；執行圖案化製程以形成一第一鰭結構和一第二鰭結構，其中該第一鰭結構包含該第一半導體層的一部分和該N型井的一部分，該第二鰭結構包含該第二半導體層的一部分和該P型井的一 部分；形成一第一襯墊層於該第一鰭結構、該N型井、該第二鰭結構，以及該P型井上方；選擇性地移除形成該第一襯墊層，以移除形成於該第二鰭結構和該P型井上方之該第一襯墊層，其中形成於該第一鰭結構和該N型井上方之該第一襯墊層的剩餘部分並不受選擇性移除所影響；以及在選擇性地移除該第一襯墊層後，形成一第二襯墊層於該第二鰭結構、該P型井，以及該第一襯墊層的剩餘部分上方，其中該第二襯墊層和該第一襯墊層具有不同材料組成。
  13. 如請求項12所述之製造半導體元件方法，進一步包含：移除形成於該第一半導體層上方之一部分的該第一襯墊層及該第二襯墊層；以及移除形成於該第二半導體層上一部分的該第二襯墊層。
  14. 如請求項12所述之製造半導體元件方法，其中形成該第一襯墊層包含形成一含氮化物層作為該第一襯墊層。
  15. 如請求項14所述之製造半導體元件方法，其中該含氮化物襯墊層包含氮化矽。
  16. 如請求項12所述之製造半導體元件方法，其中形成該第二襯墊層包含形成一含氧化物襯墊層作為該第二襯墊 層。
  17. 如請求項16所述之製造半導體元件方法，其中該含氧化物襯墊層包含氧化矽。
  18. 如請求項12所述之製造半導體元件方法，其中：該第一半導體層之形成包含以矽化鍺磊晶作為該第一半導體層，該第一半導體層位於該N型井上方；以及該第二半導體層之形成包含以矽磊晶作為該第二半導體層，該第二半導體層位於該P型井上方。
  19. 如請求項18所述之製造半導體元件方法，其中：該第二半導體層早於該第一半導體層之前形成；以及執行矽磊晶，以使矽長於該N型井和該P型井上方。
  20. 如請求項19所述之製造半導體元件方法，進一步包含，在形成該第二半導體層後，但於形成該第一半導體層前，移除一部分位於該N型井上方之該第二半導體層，其中在移除一部分的該第二半導體層後，將該第一半導體層磊晶長於位於該N型井上方之該第二半導體層的剩餘部分上方。
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