TW201824496A - 跳孔結構 - Google Patents
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Abstract
本發明揭露係關於半導體結構並且,尤其,係關於跳孔結構及製造之方法。該結構包含:具有一層或一層以上之線路結構之第一線路層;具有一層或一層以上之線路結構之第二線路層,位在該第一線路層上方;具有金屬化之跳孔,該金屬化穿越通過包含該第二線路層之較高的線路階層並且與該第一線路層之該一層或一層以上之線路結構產生接觸;以及包括保護材料及接觸在該較高的線路階層處之至少一層該一層或一層以上之線路結構之通孔結構。
Description
本發明揭露係關於半導體結構並且,尤其,係關於跳孔結構及製造之方法。
通孔為在穿越一層或一層以上的鄰接層之平面之實體電子電路中於線路結構(例如,線路層)之間之電性連接。例如,在積體電路設計中,通孔是在允許傳導連接於不同的線路層之間的絕緣氧化層中之小的開孔。連接金屬的最低層至擴散或複晶之通孔通常稱為”接觸(contact)”。
在通孔技術中,跳孔可以是穿過很多絕緣層而形成,例如,旁通一層或一層以上之位在該絕緣層內之線路結構,以與較低的線路結構連接。該方法提供改良的電阻特性、最小化用於較低線路結構之電容(例如,在M0層處),以及提供面積效率於該晶片製造流程中。
使用跳孔具有很多挑戰。例如,在該製造流程中,該跳孔將落在較低階層(例如,M0層)中之該線路結構上,而該一般的通孔將落在較高的階層(例如,M1或以上的階層)中之該線路結構上。然而,由於該跳孔蝕 刻製程,在該較高的階層中之該線路結構及通孔內連線結構之間之界面處將會造成損壞。意即,由於該不同的蝕刻深度,因此,該跳孔蝕刻製程對於該較上方的線路結構(例如,銅材料)將造成表面損壞。這種損壞造成較高的電阻率,反過來,該較高的電阻率降低裝置效能。
在本發明揭露之態樣中,結構包括:具有一層或一層以上之線路結構之第一線路層;具有一層或一層以上之線路結構之第二線路層,位在該第一線路層上方;具有金屬化之跳孔,該金屬化穿越通過包含該第二線路層之較高的線路階層並且與該第一線路層之該一層或一層以上之線路結構產生接觸;以及包括保護材料及接觸在該較高的線路階層處之至少一層該一層或一層以上之線路結構之通孔結構。
在本發明揭露之態樣中,方法包括:形成通孔,以曝露出較高的線路層之一層或一層以上之線路結構;形成保護材料於該通孔中,以遮罩該較高的線路層之該曝露的一層或一層以上之線路結構;以及形成穿越通過該較高的線路層及曝露較低的線路層之一層或一層以上之線路結構之跳孔,而該保護材料保護該較高的線路層之該曝露的一層或一層以上之線路結構。
在本發明揭露之態樣中,方法,包括:形成具有一層或一層以上之線路結構之線路層於較低的線路層中;形成具有一層或一層以上之線路結構之線路層於較高 的線路層中,位在該較低的線路層上方;形成通孔,以曝露該較高的線路層之該一層或一層以上之線路結構及穿越通過該較高的線路層並且落在該較低的線路層上方之通孔;形成保護材料於該通孔中,以遮罩該較高的線路層之該曝露的一層或一層以上之線路結構;延伸落在該較低的線路層之該通孔至形成曝露該較低的線路層之該一層或一層以上之線路結構之跳孔,而該保護材料保護該較高的線路層之該曝露的一層或一層以上之線路結構;以及以傳導材料填覆至少該跳孔,以接觸該較低的線路層之該一層或一層以上之線路結構及與該較高的線路層之該一層或一層以上之線路結構以電性連接。
10‧‧‧結構
10’‧‧‧結構
10”‧‧‧結構
12‧‧‧絕緣材料
14‧‧‧線路結構
16‧‧‧覆蓋層
18‧‧‧絕緣層
20‧‧‧線路結構
22‧‧‧內連線結構
24‧‧‧覆蓋層
26‧‧‧絕緣層
28‧‧‧遮罩材料
32a‧‧‧通孔
32a’‧‧‧通孔
32b‧‧‧通孔
34‧‧‧保護層
34’‧‧‧保護材料
34”‧‧‧保護材料
36‧‧‧溝槽
38‧‧‧傳導材料
40‧‧‧覆蓋層
本發明揭露描述於下面的該詳細說明中,藉由本發明揭露之例示性的實施例之非限定的例子而參考該提到的複數個圖式。
第1圖依據本發明揭露之態樣顯示結構及相對應的製造流程。
第2圖,依據本發明揭露之態樣,除了其它特徵之外,顯示形成於溝槽中之保護層(例如,犠牲插塞)及相對應的製造流程。
第3圖依據本發明揭露之態樣,除了其它特徵之外,顯示跳孔結構及相對應的製程流程。
第4圖依據本發明揭露之態樣,除了其它特徵之外,顯示金屬化於該跳孔結構與一般通孔結構中及相 對應的製造流程。
第5圖依據本發明揭露之額外的態樣顯示替代的結構及相對應的製造流程。
第6圖依據本發明揭露之額外的態樣顯示替代的結構及相對應的製造流程。
本發明揭露係關於半導體結構並且,尤其,係關於跳孔結構及製造之方法。尤其,本發明揭露提供解決較高階層的通孔形成之不相等的通孔蝕刻時間問題(例如,來自於在跳孔蝕刻製程期間之發生於較高的線路層之損害)之製造流程及最終的跳孔結構。因此並且有利的是,該製造流程及最終的跳孔結構將不會因為通孔蝕刻深度之任何差異性而對於較高的線路結構造成損害。易言之,在此所提供之該方法在跳孔形成期間將不會造成銅或其它金屬化材料在該較高的線路階層(例如,M1階層)處之過蝕。
在實施例中,在此所描述之該製程在該跳孔蝕刻製程期間提供保護材料於較高的線路結構(例如,M1階層)之曝露的表面上。在實施例中,該保護材料可以是形成於通孔中之犠牲插塞材料,以保護該較高的線路結構之曝露的表面。意即,該犠牲插塞在跳孔蝕刻製程期間將當作遮罩,以保護該較高的線路結構。在實施例中,該犠牲插塞在跳孔形成之後可以移除,並接續習知的金屬化製程,以形成該內連線結構用於一般通孔填覆及跳孔填覆兩者。在此所描述之該製程是有利於所有的技術節點並且尤 其有利於7奈米及更高的技術。
本發明揭露之該跳孔結構可以以各種方式使用各種不同的工具而製造。通常,雖然該方法及工具是使用以形成具有尺寸以該微米及奈米尺度之結構。經使用以製造本發明揭露之該跳孔結構之該方法(意即,技術),已經由積體電路(IC,Integrated Circuit)技術所採用。例如,該結構是建立在晶圓上並且是實現於藉由光學微影製程於晶圓之表面上所圖案化之材料薄膜中。尤其,該跳孔結構之該製造使用三個基本的建立區塊:(i)沉積薄膜材料於基板上,(ii)藉由光學微影影像施加圖案化遮罩於該薄膜之表面上,以及(iii)針對該遮罩選擇性蝕刻該薄膜。
第1圖依據本發明揭露之態樣顯示結構及相對應的製造流程。尤其,該結構10包含複數個線路階層(例如,M0、M1等等)於晶粒中。例如,該結構10包含提供於絕緣材料12中之線路結構14。如同應該由熟習該項技藝之人士所瞭解的是,在該絕緣材料12中之該線路結構14是較低的線路結構,代表性指定在M0階層;雖然該線路結構14可以提供在該結構之任何較低的階層處。在實施例中,該絕緣材料14為氧化物(例如,層間介電材料),該氧化物可以藉由習知的沉積方法所沉積,例如,化學氣相沉積(CVD,Chemical Vapor Deposition)。該線路結構14可以由任何傳導材料所組成,諸如,銅、鎢、鋁等等。
該線路結構14可以藉由熟習該項技藝之人士已知之習知的微影、蝕刻及沉積方法所形成。例如,形成 於該絕緣材料12上方之光阻經曝露於能量(光)以形成圖案(開孔)。具有選擇性化學之蝕刻製程(例如,活性離子蝕刻(RIE,Reactive Ion Etching)),將會使用以透過該光阻之該開孔形成一個或一個以上之溝槽於該絕緣材料12中。該光阻接著可以藉由習知的氧灰化製程或其它已知的剝離劑而移除。接續該光阻移除,傳導材料可以藉由任何習知的沉積製程(例如化學氣相沉積(CVD,Chemical Vapor Deposition)製程),而沉積於該一個或一個以上之溝槽中。在該絕緣材料12之該表面上之任何殘留的材料14可以藉由習知的化學機械研磨(CMP,Chemical Mechanical Polishing)製程所移除。
接續該化學機械研磨製程,覆蓋層16是形成於該線路結構14及絕緣材料12上。在實施例中,該覆蓋層16可以是擴散阻障層(例如,銅擴散阻障層),該擴散阻障層避免銅或其它金屬化擴散至較高的絕緣層18以及氧擴散至該線路結構14。
仍然參考第1圖,線路結構20及通孔內連線結構22是形成於該較高的絕緣層18中。在實施例中,該線路結構20及該內連線結構22可以形成於在該線路結構14之上方之任何線路層中。因此,該線路結構20於該絕緣材料18中為較高的線路結構,指定在M1、M2等等階層。該線路結構20及該內連線結構22可以使用習知的微影、蝕刻及沉積而形成,類似於相對於該較低的線路結構14之該形成所討論之技術。該線路結構20及該通孔內連線結 構22可以由諸如,例如,銅、鎢、鋁等等之任何傳導材料所組成。接續化學機械研磨製程以移除來自該絕緣材料18之該表面之任何殘留的材料,覆蓋層24為形成在該線路結構20及絕緣材料18上。在實施例中,該覆蓋層24可以是如同上文所描述之擴散阻障層,例如,銅擴散阻障層。
遮罩材料28是形成在該絕緣材料18之該表面上,在於該M1階層上之選擇的線路結構20及於該M0階層上之線路結構14的邊緣之間。該遮罩材料28可以是氮化鈦,由習知的沉積及蝕刻製程所沉積及圖案化,例如,活性離子蝕刻。光阻是形成於該遮罩材料28及絕緣材料18上,該光阻經曝露於能量(光)以分別地形成與一個或一個以上之線路結構14、22對準之圖案(開孔)於該M0、M1階層處。具有選擇性化學(例如,活性離子蝕刻)之蝕刻製程將會使用以透過該光阻之該開孔形成一個或一個以上之通孔32a、32b於該絕緣材料18及覆蓋層24中。該蝕刻製程為定時終止於某一深度處,其中,該較高的線路結構20之表面是藉由該通孔32b所曝露。在這種方式中,該通孔32b將是在落在曝露於該M1階層上之該線路結構20之表面上之深度,而該通孔將落在該較低的線路層上(穿越通過該較高的線路層,例如,M1階層)。
在第2圖中,保護層(例如,犠牲插塞)34是形成於該通孔32b中,直接在該較高的線路結構20之該表面上方及/或之上。在實施例中,該保護層34可以是能夠選擇性地成長於該線路結構20之該曝露的表面上之 鈷、釕或其它保護材料。在實施例中,該保護層34可以藉由無電電鍍製程沉積至在大約10奈米至大約30奈米之厚度;雖然其它尺寸也是經考量而與該遮罩材料一起使用。
在第3圖中,跳孔蝕刻製程連續穿過該較高的階層(例如,M1階層)至位在該結構之較低的階層上之該線路結構14,例如,M0階層。在實施例中,該跳孔蝕刻延伸(加深)該通孔32a’,落在該較低的階層上之該線路結構14上。在這種跳孔蝕刻製程期間,該保護層(例如,犠牲插塞)34將保護(遮罩)在該較高的階層(該線路結構14之上方)上之該線路結構20之該表面,免於受到可能會由使用於該跳孔蝕刻製程之蝕刻化學所造成之損害。該光阻接著可以由習知的氧灰化製程或其它已知的剝離劑所移除,接續於溝槽活性離子蝕刻以形成溝槽36(較高的階層,例如,階層M2)並且接著藉由濕式製程之該遮罩材料28之移除。該保護層(例如,犠牲插塞)34在該遮罩材料之該移除期間亦將保護在該M1階層上之該線路結構20之該表面。
仍然參考第3圖,在該遮罩材料28之移除之後,在該M1階層上之該線路結構20之該表面上之該保護層(例如,犠牲插塞)34將移除。例如,具有選擇性化學之濕式製程可以使用以移除該保護層(例如,犠牲插塞)34。
如同在第4圖中所顯示,該通孔32a’與32b及溝槽36是以傳導材料38填覆,以形成雙鑲嵌結構,例 如,內連線結構及較高的線路結構。由熟習該項技藝之人士應該瞭解的是形成於該通孔32a’內之該內連線結構將是跳孔結構,電性上及直接地連接至在該M0階層上之線路結構14,例如,旁通於該M1或上方階層之任何連線。於該通孔32b中之該傳導材料38,另一方面,將是一般的通孔內連線結構,提供電性及直接連線至在該較低的階層上之該線路結構20。在實施例中,該金屬材料可以是銅,鋁、鎢等等,以列出幾個考量的材料。該傳導材料38可以藉由習知的沉積方法而沉積(例如,化學氣相沉積及/或電漿氣相沉積(PVD,Plasma Vapor Deposition)及/或原子層沉積(ALD,Atomic Layer Deposition)),並接續習知的平坦化製程(例如化學機械研磨),以移除任何殘留材料於該絕緣層26上。覆蓋層40接著可以形成於該絕緣層26及傳導材料38之上方。
第5圖依據本發明揭露之另外的態樣顯示替代的結構及相對應的製造流程。在這個實施例中,保護材料在後續的溝槽及通孔填覆製程期間(例如,金屬化製程),仍然留在該溝槽32b中。例如,從在第1圖中所顯示之該結構開始,在第5圖之該結構10’中,保護材料34’之材料層可以沉積在該通孔32b內及在該線路結構20之該曝露的表面上。在實施例中,如同已經在此所描述在該跳孔蝕刻製程期間,該保護材料34’將提供保護遮罩,該保護遮罩可以是金屬,例如,鈷或釕。該保護材料34’可以藉由化學氣相沉積或無電電鍍製程而成長至大約10奈米 至大約30奈米或者以上之厚度;雖然其它尺寸在此也是可加以考量,該厚度在後續蝕刻製程期間將提供對於該線路結構20之保護。
在這個實施例中,該保護材料34’將仍然於該通孔32b’中與在該M1階層上之該線路結構20直接電性連接。接續延伸(加深)該通孔32a’以落在該較低的階層上(例如,M0階層)之該線路結構14上之該跳孔蝕刻製程,該光阻及遮罩材料可以由活性離子蝕刻及濕式蝕刻製程所移除。當具有該保護層(例如,犠牲插塞)34時,在該遮罩材料之該移除期間,該保護材料34’亦將保護在該較低的階層(例如,M1階層)上之該線路結構20之該表面。在該遮罩材料28之該移除之後,該通孔32a’、該溝槽32b及溝槽36之剩餘部分以傳導材料38填覆,以形成雙鑲嵌結構,例如,內連線結構及較高的線路結構。
如同在此已經提出的,形成於該通孔32a’中之該內連線結構將是跳孔結構,電性上及直接地連接至在該較低的M0階層上之線路結構14,例如,旁通任何連接在較高的M1中或上方階層。該傳導材料38及在該通孔32b中之保護材料34’(另一方面,將是一般的溝槽/通孔內連線結構)提供電性及直接連接至在該較高的階層上之該線路結構20。在實施例中,該傳導材料可以是銅、鋁、鎢等等,以列舉一些考量的材料,藉由習知的沉積方法所沉積(例如化學氣相沉積及/或電漿氣相沉積(PVD,Plasma Vapor Deposition)及/或原子層沉積(ALD,Atomic Layer Deposition)),並接續習知的平坦化製程(例如化學機械研磨),以移除任何殘留材料於該絕緣層26上。覆蓋層40接著可以形成於該絕緣層26及傳導材料38之上方。
第6圖依據本發明揭露之另外的態樣顯示替代的結構及相對應的製造流程。在這個實施例中,保護材料完全地或實質上完全地填覆該通孔32b,並且在後續的通孔填覆及線路形成期間將仍然存在於該溝槽32b內。例如,從在第1圖中所顯示之該結構開始,在第6圖之該結構10”中,保護材料34”填覆該通孔32b並且經由沉積以與該線路結構20之該曝露的表面直接電性連接。在這個實施例中,該保護材料34”亦可以是金屬,例如,鈷或釕,如同已經在此所描述的,該金屬在該跳孔蝕刻製程期間當作保護遮罩。該保護材料34”可以是藉由化學氣相積或無電電鍍製程所成長以完全地填覆該溝槽32b。
在這個實施例中,該保護材料34”將仍然存在於該通孔32b中以與在該較高的階層上(例如,M1階層)之該線路結構20直接電性連接。接續延伸(加深)該通孔32a’以落在該較低的階層(例如,M0階層)上之該線路結構14上之該跳孔蝕刻製程,該光阻及遮罩材料可以由濕式蝕刻製程所移除。當具有該保護層(例如,犠牲插塞)34時,在該溝槽36之該形成(活性離子蝕刻製程)及該遮罩材料之該濕式移除期間,該保護材料34’亦將保護在該較低的階層上之該線路結構20之該表面。在該遮罩材料28之該移除之後,該溝槽通孔及該溝槽36以傳導材料38 填覆,以形成雙鑲嵌結構,例如,內連線結構及較高的線路結構。
如同在此已經提出的,形成於該通孔32a’中之該內連線結構將是跳孔結構,電性上及直接地連接至在該M0階層上之線路結構14,例如,旁通任何連接在該M1中或較高的金屬階層。在該通孔32b中之該保護材料34’(另一方面,將是一般的通孔內連線結構)提供電性及直接連接至藉由該傳導材料38所形成之在該M1階層上及較高的階層上之該線路結構20。在實施例中,該金屬材料可以是銅、鋁、鎢等等,以列舉一些考量的材料,藉由習知的沉積方法所沉積(例如化學氣相沉積及/或電漿氣相沉積(PVD,Plasma Vapor Deposition)及/或原子層沉積(ALD,Atomic Layer Deposition)),並接續習知的平坦化製程(例如化學機械研磨),以移除任何殘留材料於該絕緣層26上。覆蓋層40接著可以形成於該絕緣層26及傳導材料38之上方。
上文所描述之該方法是使用於製造積體電路晶片。該最終的積體電路晶片可以藉由該製造者以原始晶圓形式(意即,作為具有多個未封裝的晶片之單一晶圓)所分配,成為裸晶或以封裝形式。在該後者的例子中該晶片是安裝於單一晶片封裝中(諸如塑膠載板,具有固定於主機板之導線或其它較高階層載板)或以多晶片封裝(諸如具有任一的或兩者的表面內連線或埋置內連線之陶瓷載板)。在任何例子中該晶片是接著與其它晶片、離散電路元 件及/或其它訊號處理裝置積體化而作為部分不論是(a)中間產品(諸如主機板)或(b)終端產品。該終端產品可以是包含積體電路晶片之任何產品,範圍從玩具及其它低端應用至具有顯示器、鍵盤或其它輸入裝置之先進電腦產品,以及中央處理器。
本發明揭露之該各種實施例之該描述已經呈現用於說明之態樣,但是並非意在耗盡或限定於所揭露之該實施例。很多修正及變化對於熟習該項技藝之人士將是顯而易見的而不會違反該描述的實施例之該範疇及精神。在此所使用之該術語是經選定以最佳解釋該實施例、該實施應用或經由技術發現於該市場中之技術改良之原理,或者使得熟習該項技藝之人士能夠瞭解在此所揭露之該實施例。
Claims (20)
- 一種結構,包括:第一線路層,具有一層或一層以上之線路結構;第二線路層,具有一層或一層以上之線路結構,位在該第一線路層之上方;跳孔,具有金屬化,該金屬化穿越通過包含該第二線路層之較高的線路階層並且使得與該第一線路層之該一層或一層以上之線路結構產生接觸;以及通孔結構,包括保護材料及接觸在該較高的線路階層處之至少一層該一層或一層以上之線路結構。
- 如申請專利圍第1項所述之結構,其中,該保護材料是金屬。
- 如申請專利圍第2項所述之結構,其中,該金屬是鈷及釕的其中一者。
- 如申請專利圍第1項所述之結構,其中,該保護材料完全地或實質上完全地填覆該通孔結構。
- 如申請專利圍第4項所述之結構,其中,該金屬化形成線路層,該線路層在該通孔結構上方的該保護金屬上方並與該保護金屬產生接觸。
- 如申請專利圍第1項所述之結構,其中,該保護材料部分地填覆該通孔結構。
- 如申請專利圍第6項所述之結構,其中,該金屬化填覆該通孔結構之剩餘部分,與該保護材料產生接觸。
- 如申請專利圍第7項所述之結構,其中,該金屬化為在 該通孔結構上方並與該通孔結構產生接觸的線路層。
- 如申請專利圍第6項所述之結構,其中,該保護材料為金屬。
- 一種方法,包括:形成通孔,以曝露較高的線路層之一層或一層以上之線路結構;形成保護層材料於該通孔中,以遮罩該較高的線路層之該曝露的一層或一層以上之線路結構;以及形成穿越通過該較高的線路層及曝露較低的線路層之一層或一層以上之線路結構之跳孔,而該保護材料保護該較高的線路層之該曝露的一層或一層以上之線路結構。
- 如申請專利圍第10項所述之方法,復包括在該跳孔之形成之後及金屬化製程以填覆該跳孔及該通孔之前,移除該保護材料。
- 如申請專利圍第10項所述之方法,其中,在後續的金屬化製程以填覆至少該跳孔期間,該保護材料仍然留在該通孔中。
- 如申請專利圍第10項所述之方法,其中,該保護材料填覆或實質上填覆該通孔,並且復包括金屬化製程填覆該至少一個跳孔及形成較高的金屬線路以與該填覆的跳孔及該通孔兩者接觸。
- 如申請專利圍第10項所述之方法,其中,該保護材料為金屬。
- 如申請專利圍第10項所述之方法,其中,該保護材料部分地填覆該通孔,並且復包括後續的金屬化製程填覆該跳孔、該通孔之剩餘部分及形成較高的金屬線路以與該填覆的跳孔及該通孔接觸。
- 一種方法,包括:形成具有一層或一層以上之線路結構之線路層於較低的線路層中;形成具有一層或一層以上之線路結構之線路層於較高的線路層中,位在該較低的線路層之上方;形成通孔,以曝露該較高的線路層之該一層或一層以上之該線路結構及穿越通過該較高的線路層及落在該較低的線路層之上方之通孔;形成保護材料於該通孔中,以遮罩該較高的線路層之該曝露的一層或一層以上之線路結構;延伸落在該較低的線路層上之該通孔,以形成曝露該較低的線路層之該一層或一層以上之線路結構之跳孔,而該保護材料保護該較高的線路層之該曝露的一層或一層以上之線路結構;以及以傳導材料填覆至少該跳孔,以接觸該較低的線路層之該一層或一層以上之線路結構及以與該較高的線路層之該一層或一層以上之線路結構接觸。
- 如申請專利圍第16項所述之方法,復包括在該跳孔之形成之後及該跳孔與該通孔之該填覆之前,移除該保護材料。
- 如申請專利圍第16項所述之方法,其中,在該跳孔之該填覆期間,該保護材料仍然存在於該通孔中。
- 如申請專利圍第16項所述之方法,其中,該保護材料為金屬。
- 如申請專利圍第16項所述之方法,其中,該保護材料部分填覆該通孔,並且該填覆包含該傳導材料於該通孔中之沉積。
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