TW201824330A - 用於主動電子掃描陣列（ａｅｓａ）之磚片 - Google Patents

用於主動電子掃描陣列（ａｅｓａ）之磚片 Download PDF

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TW201824330A
TW201824330A TW106135418A TW106135418A TW201824330A TW 201824330 A TW201824330 A TW 201824330A TW 106135418 A TW106135418 A TW 106135418A TW 106135418 A TW106135418 A TW 106135418A TW 201824330 A TW201824330 A TW 201824330A
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aesa
tile
patent application
beamformer
wafer
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TW106135418A
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TWI690970B (zh
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瑪莉 手柴
傑森 米恩
凱文 羅斯頓
約翰 德拉布
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美商雷森公司
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Abstract

於一形態中，主動電子掃描陣列(AESA)磚片包括輻射器結構及氧化物接合的半導體晶圓，該氧化物接合的半導體晶圓係裝附至該輻射器結構並包含射頻(RF)岐管和波束形成器。通過該些氧化物接合晶圓之RF信號路徑包含一朝向該波束形成器而傳播之第一部分及一平行於該波束形成器而傳播之第二部分。

Description

用於主動電子掃描陣列（ＡＥＳＡ）之磚片
本發明係有關用於主動電子掃描陣列(AESA)之磚片。
如本技術中所已知，相位陣列天線包括以已知距離所彼此分隔開的複數主動電路。主動電路之各者係透過複數移相器電路、放大器電路及/或其他電路而被耦合至傳輸器與接收器之任一者或兩者。於某些情況下，移相器、放大器電路、及其他電路(例如，混合器電路)被提供於所謂的傳輸/接收(T/R)模組中且被視為傳輸器及/或接收器之部分。 　　移相器、放大器及其他電路(例如，T/R模組)常需要外部電源供應(例如，DC電源供應)以供正確地操作。因此，該些電路被稱為「主動電路」或「主動組件」。因此，包括主動電路之相位陣列天線常被稱為「主動相位陣列」。主動相位陣列雷達亦已知為一種主動電子掃描陣列(AESA)。 　　主動電路係以熱的形式消耗功率。大量的熱可造成主動電路變為無法操作。因此，主動相位陣列應被冷卻。於一範例中，熱槽被裝附至各主動電路以供散熱。
於一形態中，主動電子掃描陣列(AESA)磚片包括輻射器結構及氧化物接合的半導體晶圓，該氧化物接合的半導體晶圓係裝附至該輻射器結構並包含射頻(RF)岐管和波束形成器。通過該些氧化物接合晶圓之RF信號路徑包含一朝向該波束形成器而傳播之第一部分及一平行於該波束形成器而傳播之第二部分。 　　上述形態可具有以下特徵之一或更多者。通過該些氧化物接合晶圓之該RF信號路徑可包括一遠離該波束形成器而傳播之第三部分。該RF信號路徑進一步可包括第三路徑，其係延伸入該波束形成器並離開該波束形成器。該些氧化物接合晶圓可為熔凝矽土。該些氧化物接合晶圓可包括金屬柱，其中來自一晶圓之金屬柱可被連接至另一晶圓之金屬柱。波束形成器可包括移相器、放大器、或特定應用積體電路(ASIC)之至少一者。波束形成器可被製造於矽鍺(SiGe)晶圓上。該輻射器結構可提供針對該波束形成器之輻射屏蔽。該RF岐管可傳播RF信號且不傳播任何DC信號。該波束形成器可包括再分佈層，用以容許表面裝附至印刷電路板。電力、信號及RF可藉由晶圓通孔而從該PWB被配送通過該波束形成器。該些氧化物接合半導體晶圓可由高電阻率矽所製造。該RF信號可使用帶線、共面波導(CPW)、微帶及同軸RF結構之至少一者而被配送。該磚片可包括時間延遲結構及過濾結構。主動元件間隔係配適於λ/2內以致能達60度之寬掃描。主動元件之數目係介於十六至六十四主動元件之間。該些磚片為可擴縮至主動元件之N × N陣列，其中N ＞ 1。
文中所述者為一種毫米波射頻(RF)磚片，其被使用為主動電子掃描陣列(AESA)並可擴縮以形成較大的N × N AESA，舉例而言。磚片(如文中所述)係結合低損失玻璃RF岐管，其被直接地晶圓級接合至波束形成電路及輻射屏蔽輻射器。 　　如本技術中所理解，較高的頻率需要介於主動元件間之較緊密的晶格間隔，其係留下較少的空間給主動電路。當針對寬掃描角度需要λ/2(於傳輸頻率之半波長)間隔時，此變為更加緊密。文中所述之磚片結構致能(例如)使用通孔以橫越Z軸，藉此容許較高的頻率(諸如Ka頻帶及更高)被達成。一或更多磚片可被裝附至印刷電路板，其係致能可擴縮性。例如，磚片提供高密度RF封裝及互連。於一範例中，磚片包括低損失熔凝矽土中之僅RF岐管。於一範例中，磚片提供矽鍺(SiGe)中之波束形成器功能，而SiGe波束形成器可被設置接近於冷卻劑以提供熱管理。於一範例中，RF輻射器亦可提供SiGe波束形成器之屏蔽(例如)自輻射效應。於其他範例中，波束形成器可被製造以其他半導體，諸如高電阻率矽、碳化矽、砷化鎵，等等。於其他範例中，其他功能可被包括於RF岐管層中，諸如過濾及時間延遲。於一範例中，時間延遲功能包括配送較長的軌線長度以延遲信號。這些其他功能可被加入該堆疊中所結合之額外晶圓。 　　參考圖1，AESA可被用於數個應用。例如，如圖1中所示，AESA 100之陣列12可被用於行動環境，諸如行動平台單元10。於此範例中，AESA 100被配置於4 × 4陣列中。雖然圖1係描繪矩形之形狀的AESA 100，但AESA 100可被建構為圓形、三角形或任何多角形狀。同時，雖然陣列12為方形之形狀，但該陣列可為矩形、圓形、三角形或任何多角形配置。再者，AESA 100之數目可為一至任何數目的AESA 100。 　　於其他應用中，一或更多AESA 100可被用於海軍艦艇之側面上、於地面結構、地面艦艇、空中艦艇、太空艦艇等等上。於一特定範例中，AESA 100可被置於星球或行星探針上。如將於文中所示，AESA 100為用以形成一種AESA系統(其為模組式及純量的)之「建立區塊」。於一特定範例中，AESA 100為毫米波AESA。 　　參考圖2，於一特定範例中，AESA 100包括磚片200之陣列(例如，磚片200之9 × 9陣列)。磚片200亦已知為「已知良好磚片」(KGT)。AESA 100亦包括冷卻板204及印刷電路板(PCB)206。於一範例中，各磚片200被裝附至PCB 206，其係由冷卻板204所冷卻。各磚片200包括主動元件222，其係傳輸並接收信號。於此範例中，主動元件222被配置於8 × 8陣列中。如將被進一步描述於文中，磚片200被製造自氧化物接合晶圓之堆疊，其係使用射頻直接接合混成(RF-DBH)並透過晶圓通孔而被互連。 　　參考圖3，磚片200包括晶圓(例如，晶圓304a、晶圓304b、晶圓304c和晶圓304d)、波束形成器312及輻射器/屏蔽結構324。晶圓304a-304d被氧化物接合。例如，晶圓304a之氧化物306a被接合與晶圓304b之氧化物306b、晶圓304b之氧化物306c被接合與晶圓304c之氧化物306d以及晶圓304c之氧化物306e被接合與晶圓304d之氧化物306f。氧化物亦被用以將波束形成器312接合至晶圓堆疊(晶圓304d上之氧化物306g被接合與波束形成器312之氧化物306h)。 　　RF岐管320被配置於晶圓304a-304d內。於一特定範例中，RF岐管係位於晶圓304a-304d中間(如圖3中所示)，但可被置於圖3中所示者以外的其他晶圓中。RF岐管320作用為RF結合器/分割器。例如，針對六十四主動元件，岐管將是64：1 RF結合器/分割器。於一範例中，在晶圓304a-304d內，岐管320僅配送RF信號，且(特別地)沒有DC電力或控制信號之配送於晶圓304a-304d。岐管320延伸於XY平面(亦即，進入圖3)而岐管320之範例被描繪於圖5中之XY平面中。於一範例中，岐管320包括由高電阻率矽所製之層。 　　於一範例中，晶圓304a-304d為熔凝矽土晶圓。於一特定範例中，各矽土晶圓為100微米厚。於一特定範例中，熔凝矽土為低損失熔凝矽土，其中k = 3.82而損失正切係等於.0007於60 GHz。於一範例中，晶圓304a-304d可為低損失、高電阻率矽。於進一步範例中，晶圓304a-304d可為多於或少於四個晶圓。 　　通孔被用以提供通過磚片200之電路徑。例如，晶圓304a包括通孔(例如，通孔308a及通孔308b)、晶圓304b包括通孔(例如，通孔308c及通孔308d)、晶圓304c包括通孔(例如，通孔308e、通孔308f、通孔308g、通孔308h、及通孔308i)而晶圓304d包括通孔(例如，通孔308j、通孔308k、通孔308l、通孔308m、及通孔308n)。 　　通孔可被連接至金屬軌線，其被連接至金屬柱。例如，晶圓304a包括金屬柱313及金屬軌線314。如進一步於圖4中所述，金屬柱係提供從一晶圓至另一晶圓之電連接。 　　氧化物接合晶圓304a-304d包括用於電互連之金屬化層。於一範例中，金屬層310a提供介於通孔308j與通孔308k之間的互連。於另一範例中，氧化物306h包括金屬層互連310b，其係提供介於通孔308f、通孔308g與通孔308h之間的電連接。於進一步範例中，氧化物306h包括互連310c，其係提供介於通孔308m與通孔308n之間的電連接。通孔308係連接晶圓304之兩側上的金屬，而介於該晶圓上的金屬墊之間的互連被形成於與金屬柱(顯示以金屬柱313)的氧化物接合期間。 　　波束形成器312包括至少一控制特定應用積體電路ASIC(例如，ASIC 340)、放大器(例如，放大器344a和放大器344b)及移相器(例如，移相器346a和移相器346b)。於一範例中，波束形成器312可被製造於矽鍺(SiGe)晶圓上。於其他範例中，波束形成器312提供RF衰減及RF切換。 　　波束形成器312亦包括背面再分佈層(RDL)(例如，RDL 348a)，其包括互連墊348b，用以致能使用標準表面安裝技術而裝附至PCB 206。波束形成器312係藉由使用焊料凸塊(例如，焊料凸塊350a-350e)而被裝附至PCB 206。於一範例中，焊料凸塊350a係攜載控制信號，焊料凸塊350b、350d被裝附至接地，焊料凸塊350c係攜載RF信號而焊料凸塊350e係攜載電力。 　　輻射器/屏蔽結構324係藉由金屬互連而被接合至晶圓。於一範例中，互連可為焊料凸塊。於另一範例中，其可為銦凸塊。例如，輻射器/屏蔽結構324係藉由焊料凸塊380a而被接合至晶圓304a之通孔308a，及輻射器/屏蔽結構324係藉由焊料凸塊380a而被接合至晶圓304a之通孔308b。於一範例中，輻射器/屏蔽結構324被設計成傳播RF信號通過輻射器並提供輻射屏蔽給波束形成器312。於一範例中，輻射器係由具有低膨脹係數之金屬(如銦鋼)所製，用以減少針對晶圓堆疊之連接的應力，且該金屬夠厚以提供正確量的輻射屏蔽。 　　於一特定範例中，RF信號路徑370係開始於輻射器/屏蔽結構324，並繼續通過連接380b、晶圓304a之通孔308b、通過晶圓304b之通孔308d、通過晶圓304c之通孔308i及通過晶圓30da之通孔308n。RF信號路徑370繼續於波束形成器312中，藉由通過放大器344b及移相器346。RF信號繼續回頭遠離波束形成器312並進入晶圓304c、304d，藉由通過晶圓304d之通孔308m、通過晶圓304c之通孔308h。RF信號路徑370繼續通過互連310b、通過晶圓304c之通孔308g、通過晶圓304d之通孔308i。RF信號傳播回入波束形成器312並通過304c而至PCB 206，通過凸塊350c。 　　RF路徑370移動於晶圓內之至少兩軸。例如，RF信號路徑370沿著兩軸而移動(例如，其沿著X軸及Z軸移動)。於其他範例中，信號路徑370亦可移動於Y軸(未顯示)。於其他範例中，RF信號路徑可流動在與RF信號路徑370相反的方向上。其他RF信號路徑未被信號路徑370所限制。亦即，其他RF信號路徑及組合是可能的，且RF信號路徑370僅為圖3中所可能的許多RF信號路徑之一範例。 　　圖4描繪其被氧化物接合的兩晶圓之一範例，例如，以一種氧化物接合晶圓304a-304d被組態的方式。例如，晶圓404a之氧化物406a被接合至晶圓404b之氧化物406b。於一範例中，氧化物鍵為一種於室溫所形成的分子鍵。DBH包括金屬柱，諸如接合至晶圓404b之柱412c的晶圓404a之柱412a及接合至晶圓404b之柱412d的晶圓404a之柱412b。於一範例中，柱412a-412d係由金屬所製。於一特定範例中，柱412a-412d為銅柱。於另一特定範例中，柱412a-412d為鎳柱。於進一步特定範例中，柱412a-412d為鋁柱。於一範例中，柱412a-412d具有少於10微米的節距能力。 　　柱可由金屬軌線層所連接(例如，柱412c係藉由金屬軌線層414而被連接至柱412d)。金屬軌線層可被連接至通孔(例如，金屬軌線層414被連接至通孔408)。於一範例中，通孔408可有約25微米之直徑。於一範例中，通孔408可為銅通孔。 　　圖5描繪RF岐管320為RF岐管520之範例。於此範例中，RF岐管520為針對十六個元件(例如，主動元件522a-522p)之16：1 RF結合器/分割器。於一範例中，岐管520被製造於其為低損失、高電阻率矽之晶圓304a-304d中。 　　文中所述之程序不限於所述之特定實施例。文中所述之不同實施例的元件可被結合以形成未明確地提出於上的其他實施例。未明確地描述於文中之其他實施例亦落入以下申請專利範圍之範圍內。
10‧‧‧行動平台單元
12‧‧‧陣列
100‧‧‧AESA
200‧‧‧磚片
204‧‧‧冷卻板
206‧‧‧印刷電路板（PCB）
222‧‧‧主動元件
304a-304d‧‧‧晶圓
306a-306h‧‧‧氧化物
308a-308n‧‧‧通孔
310a-310c‧‧‧金屬層
312‧‧‧波束形成器
313‧‧‧金屬柱
314‧‧‧金屬軌線
320‧‧‧RF岐管
324‧‧‧輻射器/屏蔽結構
340‧‧‧ASIC
344a、344b‧‧‧放大器
346a、346b‧‧‧移相器
348a‧‧‧再分佈層（RDL）
348b‧‧‧互連墊
350a-350e‧‧‧焊料凸塊
370‧‧‧RF信號路徑
380a‧‧‧焊料凸塊
380b‧‧‧連接
404a、404b‧‧‧晶圓
406a、406b‧‧‧氧化物
408‧‧‧通孔
412a-412d‧‧‧柱
414‧‧‧金屬軌線層
520‧‧‧RF岐管
522a-522p‧‧‧主動元件
圖1為配置於行動平台上之主動電子掃描陣列(AESA)的陣列之一範例的圖形。 　　圖2為AESA之範例的圖形。 　　圖3為具有磚片的AESA之範例的橫斷面視圖。 　　圖4為兩個氧化物接合晶圓之範例的橫斷面視圖。 　　圖5為射頻(RF)岐管之範例的圖形。

Claims (17)

  1. 一種主動電子掃描陣列(AESA)磚片，包含： 　　輻射器結構；及 　　氧化物接合半導體晶圓，其係裝附至該輻射器結構並包含射頻(RF)岐管和波束形成器； 　　其中通過該些氧化物接合晶圓之RF信號路徑包含一朝向該波束形成器而傳播之第一部分及一平行於該波束形成器而傳播之第二部分。
  2. 如申請專利範圍第1項之AESA磚片，其中通過該些氧化物接合晶圓之該RF信號路徑進一步包含一遠離該波束形成器而傳播之第三部分。
  3. 如申請專利範圍第1項之AESA磚片，其中該RF信號路徑進一步包含第三路徑，其係延伸入該波束形成器並離開該波束形成器。
  4. 如申請專利範圍第1項之AESA磚片，其中該些氧化物接合晶圓為熔凝矽土。
  5. 如申請專利範圍第1項之AESA磚片，其中該些氧化物接合晶圓包含金屬柱，及 　　其中來自一晶圓之金屬柱被連接至另一晶圓之金屬柱。
  6. 如申請專利範圍第1項之AESA磚片，其中該波束形成器包含移相器、放大器、或特定應用積體電路(ASIC)之至少一者。
  7. 如申請專利範圍第1項之AESA磚片，其中該波束形成器被製造於矽鍺(SiGe)晶圓上。
  8. 如申請專利範圍第1項之AESA磚片，其中該輻射器結構提供針對該波束形成器之輻射屏蔽。
  9. 如申請專利範圍第1項之AESA磚片，其中該RF岐管係傳播RF信號且無DC信號。
  10. 如申請專利範圍第1項之AESA磚片，其中該波束形成器包括再分佈層，用以容許表面安裝至印刷電路板。
  11. 如申請專利範圍第1項之AESA磚片，其中電力、信號及RF係藉由晶圓通孔而從該PWB被配送通過該波束形成器。
  12. 如申請專利範圍第1項之AESA磚片，其中該些氧化物接合半導體晶圓係由高電阻率矽所製。
  13. 如申請專利範圍第1項之AESA磚片，其中該RF信號係使用帶線、共面波導(CPW)、埋入式微帶及同軸RF結構之至少一者而被配送。
  14. 如申請專利範圍第1項之AESA磚片，其中該磚片包含時間延遲結構及過濾結構。
  15. 如申請專利範圍第1項之AESA磚片，進一步包含主動元件， 　　其中主動元件間隔係配適於λ/2內以致能達60度之寬掃描。
  16. 如申請專利範圍第15項之AESA磚片，其中主動元件之數目係介於十六至六十四主動元件之間。
  17. 如申請專利範圍第15項之AESA磚片，其中該些磚片為可擴縮至主動元件之N × N陣列，其中N ＞ 1。
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