CN109891674A - 用于有源电子扫描阵列(aesa)的瓦片 - Google Patents
用于有源电子扫描阵列(aesa)的瓦片 Download PDFInfo
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- CN109891674A CN109891674A CN201780066115.2A CN201780066115A CN109891674A CN 109891674 A CN109891674 A CN 109891674A CN 201780066115 A CN201780066115 A CN 201780066115A CN 109891674 A CN109891674 A CN 109891674A
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Abstract
在一个方面,一种有源电子扫描阵列(AESA)瓦片,包括:辐射器结构;以及氧化物结合的半导体晶片,附接到辐射器结构并包括射频(RF)歧管和波束形成器。通过所述氧化物结合的晶片的RF信号路径包括朝向所述波束形成器传播的第一部分和平行于所述波束形成器传播的第二部分。
Description
背景技术
如本领域所公知的,相控阵天线包括以已知距离彼此间隔开的多个有源电路。每一个有源电路通过多个移相器电路、放大器电路和/或其他电路耦合到发送器和接收器中的任一个或两者。在一些情况下,移相器、放大器电路和其他电路(例如,混频器电路)提供在所谓的发送/接收(T/R)模块中,并且被认为是发送器和/或接收器的部分。
移相器、放大器和其他电路(例如,T/R模块)通常需要外部电源(例如,DC电源)来能正确地操作。因此,这些电路被称为“有源电路”或“有源组件”。因此,包括有源电路的相控阵天线通常被称为“有源相控阵”。有源相控阵雷达也被称为有源电子扫描阵列(AESA)。
有源电路以热的形式耗散功率。大量的热会导致有源电路无法操作。因此,应冷却有源相控阵。在一个示例中,热沉(单个或多个)附接到每一个有源电路以散热。
发明内容
在一个方面,一种有源电子扫描阵列(AESA)瓦片,包括:辐射器结构;以及氧化物结合的(oxide-bonded)半导体晶片,附接到所述辐射器结构并包括射频(RF)歧管和波束形成器。通过所述氧化物结合的晶片的RF信号路径包括朝向所述波束形成器传播的第一部分和平行于所述波束形成器传播的第二部分。
以上方面可以具有一个或多个以下特征。通过所述氧化物结合的晶片的所述RF信号路径可以包括远离所述波束形成器传播的第三部分。所述RF信号路径还可以包括第三路径,所述第三路径延伸到所述波束形成器中并且延伸出所述波束形成器。所述氧化物结合的晶片可以是熔融二氧化硅(silica)。所述氧化物结合的晶片可以包括金属柱,其中,来自一个晶片的金属柱可以连接到另一个晶片的金属柱。所述波束形成器可以包括移相器、放大器或专用集成电路(ASIC)中的至少一个。所述波束形成器可以制造在硅锗(SiGe)晶片上。所述辐射器结构可以为所述波束形成器提供辐射屏蔽。所述RF歧管可以传播RF信号而不传播任何DC信号。所述波束形成器可以包括再分布层,以容许表面安装到印刷电路板。可以通过晶片过孔使功率、信号和RF从PWB路由通过所述波束形成器。所述氧化物结合的半导体晶片可以由高电阻率硅制成。可以使用带状线、共面波导(CPW)、掩埋微带和同轴RF结构中的至少一种来路由所述RF信号。所述瓦片可以包括时间延迟结构和滤波结构。有源元件间隔适合在λ/2内以使得能够实现至60度的宽扫描。有源元件的数量在十六到六十四个有源元件之间。所述瓦片能够缩放到有源元件的N×N阵列,其中N>1。
附图说明
图1是设置在移动平台上的有源电子扫描阵列(AESA)的阵列的一个示例的图。
图2是AESA的示例的图。
图3是具有瓦片(tile)的AESA的示例的横截面图。
图4是两个氧化物结合晶片的示例的横截面图。
图5是射频(RF)歧管(manifold)的示例的图。
具体实施方式
本文描述的是毫米波射频(RF)瓦片,其用作有源电子扫描阵列(AESA)并且可缩放以形成例如更大的N×N AESA。如本文所述,瓦片并入有低损耗玻璃RF歧管,其晶片级直接结合到波束形成电路和辐射屏蔽辐射器。
如本领域所理解的,较高频率需要有源元件之间更紧密的晶格间距,这为有源电路留下较小的空间。当对宽扫描角需要λ/2(发射频率处的半波长)间隔时,这变得甚至更紧密。本文描述的瓦片结构使得信号能够例如使用过孔穿过Z轴,从而容许实现诸如Ka波段及以上的更高频率。可以将一个或多个瓦片安装到印刷电路板上,这实现了可缩放性。例如,瓦片提供高密度RF封装和互连。在一个示例中,瓦片包括低损耗熔融二氧化硅中的仅RF歧管。在一个示例中,瓦片在硅锗(SiGe)中提供波束形成器功能,并且SiGe波束形成器可以紧邻冷却剂放置以提供热管理。在一个示例中,RF辐射器还可以提供对SiGe波束形成器的屏蔽,例如,以免受辐射影响。在其他示例中,波束形成器可以在其他半导体中制造,诸如高电阻率硅、碳化硅、砷化镓等。在其他示例中,其他功能可以包括在诸如滤波和时间延迟的RF歧管层中。在一个示例中,时间延迟功能包括路由较长的迹线长度以延迟信号。这些其他功能可以添加到包含在堆叠体中的附加晶片中。
参考图1,AESA可用于许多应用中。例如,如图1中所示,AESA 100的阵列12可以用在诸如移动平台单元10的移动环境中。在此示例中,AESA 100以4×4阵列布置。虽然图1描绘了呈矩形形状的AESA 100,但是AESA 100可以被构造为圆形、三角形或任何多边形形状。而且,尽管阵列12呈方形,但是阵列可以是矩形、圆形、三角形或任何多边形布置。此外,AESA 100的数量可以是一至任意数量的AESA 100。
在其他应用中,一个或多个AESA 100可以用于海军舰艇侧面上、地面结构、地面船只(ground vessel)、空气罐(air vessel)、太空船(space vessel)等上。在一个特定示例中,AESA 100可以放置在恒星或行星探测器上。如本文将示出的,AESA 100是用于形成模块化和标量的AESA系统的“构建块”。在一个特定示例中,AESA 100是毫米波AESA。
参考图2,在一个特定示例中,AESA 100包括瓦片200的阵列(例如,瓦片200的9×9的阵列)。瓦片200也称为“已知良好瓦片”(KGT)。AESA 100还包括冷却板204和印刷电路板(PCB)206。在一个示例中,每一个瓦片200附接到PCB 206,其由冷板204冷却。每一个瓦片200包括发送和接收信号的有源元件222。在一个示例中,有源元件222布置成8×8阵列。如本文将进一步描述的,瓦片200由氧化物结合的晶片的堆叠体制成,其使用射频直接结合杂化(RF-DBH)并经晶片过孔互连。
参考图3,瓦片200包括晶片(例如,晶片304a、晶片304b、晶片304c和晶片304d)、波束形成器312和辐射器/屏蔽结构324。晶片304a-304d是氧化物结合的。例如,晶片304a的氧化物306a与晶片304b的氧化物306b结合,晶片304b的氧化物306c与晶片304c的氧化物306d结合,且晶片304c的氧化物306e与晶片304d的氧化物306f结合。氧化物还用于将波束形成器312结合到晶片堆叠体(例如,晶片304d上的氧化物306g与波束形成器312的氧化物306h结合)。
RF歧管320设置在晶片304a-304d内。在一个特定示例中,RF歧管位于图3中所描绘的晶片304a-304d的中间,但是可以位于图3中所示的晶片以外的其他晶片中。该RF歧管320个用作RF组合器/分配器。例如,对于64个有源元件,歧管将是64:1RF组合器/分配器。在一个示例中,在晶片304a-304d内,歧管320仅路由RF信号,并且特别地,在晶片304a-304d中不路由DC功率或控制信号。歧管320在XY平面中延伸(即,进入图3中),并且歧管320的示例描绘于图5中的XY平面中。在一个示例中,歧管320包括由高电阻率硅制成的层。
在一个示例中,晶片304a-304d是熔融二氧化硅晶片。在一个特定示例中,每一个二氧化硅晶片为100微米厚。在一个特定示例中,熔融二氧化硅是低损耗熔融二氧化硅,其中k=3.82并且损耗角正切在60GHz处等于0.0007。在一个示例中,晶片304a-304d可以是低损耗、高电阻率的硅。在另外的示例中,晶片304a-304d可以多于或少于四个晶片。
过孔用于提供通过瓦片200的电路径。例如,晶片304a包括过孔(例如,过孔308a和过孔308b),晶片304b包括过孔(例如,过孔308c和过孔308d),晶片304c包括过孔(例如,过孔308e、过孔308f、过孔308g、过孔308h和过孔308i),并且晶片304d包括过孔(例如,过孔308j、过孔308k、过孔308l、过孔308m和过孔308n)。
过孔可以连接到金属迹线,金属迹线连接到金属柱。例如,晶片304a包括金属柱313和金属迹线314。如图4中进一步所示,金属柱提供从一个晶片到另一个晶片的电连接。
氧化物结合晶片304a-304d包括用于电互连的金属化层。在一个示例中,金属层310a提供过孔308j和过孔308k之间的互连。在另一示例中,氧化物306h包括金属层互连310b,金属层互连310b提供过孔308f、过孔308g和过孔308h之间的电连接。在另一示例中,氧化物306h包括互连310c,互连310c提供过孔308m和过孔308n之间的电连接。过孔308连接晶片304两侧的金属,并且在与以金属柱313示出的金属柱的氧化物结合期间制造晶片上的金属焊盘之间的互连。
波束形成器312包括至少一个控制专用集成电路ASIC(例如,ASIC 340)、放大器(例如,放大器344a和放大器344b)和移相器(例如,移相器346a和移相器346b)。在一个示例中,波束形成器312制造在硅锗(SiGe)晶片上。在其他示例中,波束形成器312提供RF衰减和RF开关。
波束形成器312还包括背面再分布层(RDL)(例如,RDL 348a),其包括互连焊盘348b,以使得能够使用标准表面安装技术附接到PCB 206。波束形成器312通过焊料凸块(例如,焊料凸块350a-350e)附接到PCB 206。在一个示例中,焊料凸块350a承载控制信号,焊料凸块350b、350d附接到地,焊料凸块350c承载RF信号并且焊料凸块350e承载功率。
辐射器/屏蔽结构324通过金属互连结合到晶片。在一个示例中,互连可以是焊料凸块。在另一个示例中,其可以是铟凸块。例如,辐射器/屏蔽结构324通过焊料凸块380a结合到晶片304a的过孔308a,并且辐射器/屏蔽结构324通过焊料凸块380a结合到晶片304a的过孔308b。在一个示例中,辐射器/屏蔽结构324被设计成通过辐射器传播RF信号并为波束形成器312提供辐射屏蔽。在一个示例中,辐射器由例如不胀钢的具有低膨胀系数的金属制成以减轻与晶片堆叠体连接的应力,并且足够厚以提供正确量的辐射屏蔽。
在一个特定示例中,RF信号路径370在辐射器/屏蔽结构324处开始并且通过连接380b、晶片304a的过孔308b、经晶片304b的过孔308d、经晶片304c的过孔308i并经晶片30da的过孔308n继续。RF信号路径370通过行进通过放大器344b和移相器346而在波束形成器312中继续。RF信号通过行进通过晶片304d的过孔308m、通过晶片304c的过孔308h而继续远离波束形成器312返回并进入晶片304c、304d。RF信号路径370通过互连310b经晶片304c的过孔308g、经晶片304d的过孔308i继续。RF信号传播回波束形成器312中并通过凸块350c经过孔304c传播到PCB 206。
RF路径370沿晶片内的至少两个轴移动。例如,RF信号路径370沿着两个轴移动(例如,它沿着X轴和Z轴移动)。在其他示例中,信号路径370也可以沿Y轴(未示出)移动。在其他示例中,RF信号路径可以在与RF信号路径370相反的方向上流动。其他RF信号路径不受信号路径370的限制。也就是说,其他RF信号路径和组合是可能的并且RF信号路径370仅是图3中可能的许多RF信号路径的一个示例。
图4描绘了氧化物结合的两个晶片的一个示例,例如,以配置氧化物结合的晶片304a-304d的方式。例如,晶片404a的氧化物406a结合到晶片404b的氧化物406b。在一个示例中,氧化物结合是在室温下形成的分子结合。DBH包括金属柱,诸如结合到晶片404b的柱412c的晶片404a的柱412a以及结合到晶片404b的柱412d的晶片404a的柱412b。在一个示例中,柱412a-412d由金属制成。在一个特定示例中,柱412a-412d是铜柱。在另一特定示例中,柱412a-412d是镍柱。在另一特定示例中,柱412a-412d是铝柱。在一个示例中,柱412a-412d具有小于10微米的节距(pitch)性能。
柱可以通过金属迹线层连接(例如,柱412c通过金属迹线层414连接到柱412d)。金属迹线层可以连接到过孔(例如,金属迹线层414连接到过孔408)。在一个示例中,过孔408的直径可以为约25微米。在一个示例中,过孔408可以是铜过孔。
图5描绘了RF歧管320是RF歧管520的示例。在该示例中,RF歧管520是对于16个元件(例如,有源元件522a-522p)的16:1RF组合器/分配器。在一个示例中,歧管520制造在低损耗、高电阻率硅的晶片304a-304d中。
本文描述的过程不限于所描述的具体实施例。可以组合本文描述的不同实施例的元件以形成上面没有具体阐述的其他实施例。本文未具体描述的其他实施例也在以下权利要求的范围内。
Claims (17)
1.一种有源电子扫描阵列(AESA)瓦片,包括:
辐射器结构;以及
氧化物结合的半导体晶片,附接到所述辐射器结构并包括射频(RF)歧管和波束形成器;并且
其中,通过所述氧化物结合的晶片的RF信号路径包括朝向所述波束形成器传播的第一部分和平行于所述波束形成器传播的第二部分。
2.如权利要求1所述的AESA瓦片,其中,通过所述氧化物结合的晶片的所述RF信号路径还包括远离所述波束形成器传播的第三部分。
3.如权利要求1所述的AESA瓦片,其中,所述RF信号路径还包括第三路径,所述第三路径延伸到所述波束形成器中并且延伸出所述波束形成器。
4.如权利要求1所述的AESA瓦片,其中,所述氧化物结合的晶片是熔融二氧化硅。
5.如权利要求1所述的AESA瓦片,其中,所述氧化物结合的晶片包括金属柱,并且
其中,来自一个晶片的金属柱连接到另一个晶片的金属柱。
6.如权利要求1所述的AESA瓦片,其中,所述波束形成器包括移相器、放大器或专用集成电路(ASIC)中的至少一个。
7.如权利要求1所述的AESA瓦片,其中,所述波束形成器制造在硅锗(SiGe)晶片上。
8.如权利要求1所述的AESA瓦片,其中,所述辐射器结构为所述波束形成器提供辐射屏蔽。
9.如权利要求1所述的AESA瓦片,其中,所述RF歧管传播RF信号而不传播DC信号。
10.如权利要求1所述的AESA瓦片,其中,所述波束形成器包括再分布层,以容许表面安装到印刷电路板。
11.如权利要求1所述的AESA瓦片,其中,通过晶片过孔使功率、信号和RF从PWB路由通过所述波束形成器。
12.如权利要求1所述的AESA瓦片,其中,所述氧化物结合的半导体晶片由高电阻率硅制成。
13.如权利要求1所述的AESA瓦片,其中,使用带状线、共面波导(CPW)、掩埋微带和同轴RF结构中的至少一种来路由所述RF信号。
14.如权利要求1所述的AESA瓦片,其中,所述瓦片包括时间延迟结构和滤波结构。
15.如权利要求1所述的AESA瓦片,还包括有源元件,
其中,有源元件间隔适合在λ/2内以使得能够实现至60度的宽扫描。
16.如权利要求15所述的AESA瓦片,其中,有源元件的数量在十六到六十四个有源元件之间。
17.如权利要求15所述的AESA瓦片,其中,所述瓦片能够缩放到有源元件的N×N阵列,其中N>1。
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TW201824330A (zh) | 2018-07-01 |
US10541461B2 (en) | 2020-01-21 |
JP2020502782A (ja) | 2020-01-23 |
KR102193899B1 (ko) | 2020-12-23 |
US20180175476A1 (en) | 2018-06-21 |
EP3555961A1 (en) | 2019-10-23 |
CN109891674B (zh) | 2021-08-24 |
TWI690970B (zh) | 2020-04-11 |
KR20190045941A (ko) | 2019-05-03 |
JP6763087B2 (ja) | 2020-09-30 |
WO2018111386A1 (en) | 2018-06-21 |
EP3555961B1 (en) | 2021-04-28 |
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