TW201802880A - 用以形成交叉耦接接觸之裝置及方法 - Google Patents
用以形成交叉耦接接觸之裝置及方法 Download PDFInfo
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- TW201802880A TW201802880A TW106112178A TW106112178A TW201802880A TW 201802880 A TW201802880 A TW 201802880A TW 106112178 A TW106112178 A TW 106112178A TW 106112178 A TW106112178 A TW 106112178A TW 201802880 A TW201802880 A TW 201802880A
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- 238000000034 method Methods 0.000 title claims abstract description 49
- 239000004065 semiconductor Substances 0.000 claims abstract description 75
- 238000001459 lithography Methods 0.000 claims abstract description 18
- 238000002955 isolation Methods 0.000 claims abstract description 10
- 238000012545 processing Methods 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 174
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 31
- 229920005591 polysilicon Polymers 0.000 claims description 31
- 238000005530 etching Methods 0.000 claims description 21
- 230000008569 process Effects 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 17
- 125000006850 spacer group Chemical group 0.000 claims description 15
- 239000011229 interlayer Substances 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 8
- 238000000206 photolithography Methods 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 238000000926 separation method Methods 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000005429 filling process Methods 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims 1
- 239000011574 phosphorus Substances 0.000 claims 1
- -1 phosphorus nitride Chemical class 0.000 claims 1
- 238000000059 patterning Methods 0.000 abstract description 12
- 229910052732 germanium Inorganic materials 0.000 description 19
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 19
- 238000001020 plasma etching Methods 0.000 description 10
- 150000004767 nitrides Chemical class 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- YZCKVEUIGOORGS-OUBTZVSYSA-N Deuterium Chemical compound [2H] YZCKVEUIGOORGS-OUBTZVSYSA-N 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 229910052805 deuterium Inorganic materials 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910000420 cerium oxide Inorganic materials 0.000 description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- 229910017214 AsGa Inorganic materials 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000012993 chemical processing Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000006880 cross-coupling reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910003468 tantalcarbide Inorganic materials 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/7684—Smoothing; Planarisation
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- H01L21/76841—Barrier, adhesion or liner layers
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Abstract
本發明揭示通過針對交叉耦接拾取(pick-up)圖案化而具有交叉耦接接觸之半導體裝置以及製造該半導體裝置之方法。一種方法包括例如:獲得中間半導體裝置;執行第一光刻,以圖案化第一形狀;執行第二光刻,以圖案化與該第一形狀的部分重疊的第二形狀;處理該第一形狀及該第二形狀,以在該重疊處形成隔離區;以及形成由該隔離區分離的四個區域。本發明還揭露一種中間半導體裝置。
Description
本發明關於半導體裝置、製造半導體裝置的方法,以及通過有限數目的光刻曝光步驟圖案化鄰近形狀的方法,尤其關於針對交叉耦接拾取進行源汲圖案化的方法及裝置。
隨著半導體裝置不斷縮小尺寸,該些裝置的尺寸持續縮小。對於較小的裝置,組件需要縮小尺寸且被設置得彼此更加靠近。為了將接觸設置得彼此更加靠近,通過多個遮罩執行多重圖案化。由於多重圖案化及多個遮罩,製造半導體裝置的成本大大增加。另外,在多重圖案化製程期間,所得接觸可能最終沒有被充分電性分離,從而導致短路及缺陷增加。因此,需要新的裝置及方法以降低執行多重圖案化的成本,同時保持接觸之間的電性分離。
為克服現有技術的缺點並提供額外的優點,在一個態樣中提供一種方法,該方法包括例如:獲得中間半導體裝置;執行第一光刻,以圖案化第一形狀;執行第
二光刻,以圖案化與該第一形狀的部分重疊的第二形狀;處理該第一形狀及該第二形狀,以在該重疊處形成隔離區;以及形成由該隔離區分離的四個區域。
在另一個態樣中,一種方法包括例如:獲得中間半導體裝置;通過使用第一遮罩執行第一光刻,以形成至少一個第一過孔開口;通過使用第二遮罩執行第二光刻,以形成至少一個第二過孔開口,其中,該至少一個第二過孔開口與該至少一個第一過孔開口重疊;以及自該至少一個第一過孔開口及該至少一個第二過孔開口形成至少四個接觸。
在又一個態樣中,提供一種中間半導體裝置,其包括例如:基板;層間介電層,沉積於該基板上;硬遮罩雙層,位於該層間介電層上;多晶矽層,位於該硬遮罩雙層上;蝕刻停止層,位於該多晶矽層上;氧化物層,位於該蝕刻停止層上;至少一個第一開口,自該中間半導體裝置的頂部表面延伸穿過該氧化物層;至少一個第二開口,自該中間半導體裝置的該頂部表面延伸穿過該氧化物層,其中,該至少一個第一開口與該至少一個第二開口重疊;以及自對準區塊,位於該至少一個第一開口與該至少一個第二開口重疊之處。
通過本發明的技術實現額外的特徵及優點。本發明的其它實施例及態樣在本文中作詳細說明並被視為所請求保護的發明的部分。
10~50‧‧‧步驟
100~126‧‧‧步驟
200‧‧‧中間半導體裝置、半導體裝置、裝置
202‧‧‧基板
204‧‧‧層間介電層、ILD層
206‧‧‧硬遮罩雙層、第一硬遮罩層
208‧‧‧硬遮罩雙層、第二硬遮罩層
210‧‧‧多晶矽層
212‧‧‧蝕刻停止層
214‧‧‧氧化物層
216‧‧‧第一光刻堆疊
218‧‧‧第一源/汲過孔圖案
220‧‧‧第一源/汲過孔開口、第一過孔開口、過孔開口
222‧‧‧第二光刻堆疊
224‧‧‧第二源/汲過孔圖案
226‧‧‧區域、重疊區
227‧‧‧凹槽
228‧‧‧第二源/汲過孔開口、過孔開口
230‧‧‧重疊區
232‧‧‧硬遮罩層
234‧‧‧過孔開口
236‧‧‧過孔開口
238‧‧‧間隙壁層、側間隙壁
240‧‧‧過孔開口、第一過孔開口
242‧‧‧過孔開口、第二過孔開口
244‧‧‧自對準多晶矽區塊
246‧‧‧第一過孔開口
248‧‧‧第二過孔開口
250‧‧‧第一源/汲接觸溝槽
252‧‧‧第二源/汲接觸溝槽
254‧‧‧第一源/汲接觸溝槽、接觸溝槽
256‧‧‧第一源/汲接觸溝槽、接觸溝槽
258‧‧‧第二源/汲接觸溝槽、接觸溝槽
260‧‧‧第二源/汲接觸溝槽、接觸溝槽
262‧‧‧阻擋層
264‧‧‧金屬層
266‧‧‧第一源/汲接觸、接觸
268‧‧‧第二源/汲接觸、接觸
270‧‧‧第一源/汲接觸、接觸
272‧‧‧第二源/汲接觸、接觸
274‧‧‧自對準區塊
本發明的一個或多個態樣被特別指出並在說明書的結束處的聲明中被明確稱為示例。從下面結合圖式所作的詳細說明可清楚本發明的上述及其它目的、特徵以及優點,這些圖式中:第1A圖顯示依據本發明的一個或多個態樣在半導體製程期間可使用的圖案化製程的方法的一個實施例;第1B圖顯示依據本發明的一個或多個態樣用於交叉耦接拾取的源汲圖案化的方法的一個實施例;第2圖顯示依據本發明的一個或多個態樣在中間半導體裝置上方具有至少一個光刻堆疊的積體電路的一個實施例的剖切立視圖;第3圖顯示依據本發明的一個或多個態樣在執行光刻以圖案化至少一個第一源/汲過孔以後的第2圖的半導體裝置的剖切立視圖;第4圖顯示依據本發明的一個或多個態樣在蝕刻中間半導體裝置的氧化物層以後的第3圖的半導體裝置的剖切立視圖;第5圖顯示依據本發明的一個或多個態樣在剝離第一光刻堆疊以後的第4圖的半導體裝置的三維視圖;第6圖顯示依據本發明的一個或多個態樣的第5圖的半導體裝置的剖切立視圖;第7圖顯示依據本發明的一個或多個態樣在
沉積第二光刻堆疊以後的第6圖的半導體裝置的剖切立視圖;第8圖顯示依據本發明的一個或多個態樣在執行光刻以圖案化至少一個第二源/汲過孔以後的第7圖的半導體裝置的三維視圖;第9圖顯示依據本發明的一個或多個態樣的第8圖的半導體裝置的剖切立視圖;第10圖顯示依據本發明的一個或多個態樣在執行氮化物反應離子蝕刻以後的第9圖的半導體裝置的三維視圖;第11圖顯示依據本發明的一個或多個態樣在執行氮化物濕式蝕刻以擴大該第一與第二過孔開口之間的分離以後沿線11--11的第10圖的半導體裝置的三維視圖;第12圖顯示依據本發明的一個或多個態樣在蝕刻氧化物層以後的第10圖的半導體裝置的剖切立視圖;第13圖顯示依據本發明的一個或多個態樣的第12圖的半導體裝置的三維視圖;第14圖顯示依據本發明的一個或多個態樣在剝離該第二光刻堆疊以後沿第16圖中的線14--14所作的第12圖的半導體裝置的剖切立視圖;第15圖顯示依據本發明的一個或多個態樣的第14圖的半導體裝置的三維視圖;
第16圖顯示依據本發明的一個或多個態樣在氧化矽以後的第15圖的半導體裝置的三維視圖;第17圖顯示依據本發明的一個或多個態樣沿第16圖中的線17--17所作的該半導體裝置的剖切立視圖;第18圖顯示依據本發明的一個或多個態樣在蝕刻氮化物層以後的第16圖的半導體裝置的三維視圖;第19圖顯示依據本發明的一個或多個態樣在蝕刻多晶矽層以後的第18圖的半導體裝置的剖切立視圖;第20圖顯示依據本發明的一個或多個態樣的第19圖的半導體裝置的三維視圖;第21圖顯示依據本發明的一個或多個態樣在沉積氧化物間隙壁層以後的第19圖的半導體裝置的剖切立視圖;第22圖顯示依據本發明的一個或多個態樣的第21圖的半導體裝置的三維視圖;第23圖顯示依據本發明的一個或多個態樣在該間隙壁層的受控反應離子蝕刻以後的第21圖的半導體裝置的剖切立視圖;第24圖顯示依據本發明的一個或多個態樣的第23圖的半導體裝置的三維視圖;第25圖顯示依據本發明的一個或多個態樣在執行另一個反應離子蝕刻以打穿第二硬遮罩層以後的第
23圖的半導體裝置的剖切立視圖;第26圖顯示依據本發明的一個或多個態樣的第25圖的半導體裝置的三維視圖;第27圖顯示依據本發明的一個或多個態樣在執行等向性蝕刻以移除該間隙壁層以後的第25圖的半導體裝置的剖切立視圖;第28圖顯示依據本發明的一個或多個態樣的第27圖的半導體裝置的三維視圖;第29圖顯示依據本發明的一個或多個態樣在執行另一個反應離子蝕刻以打穿阻擋層以後的第28圖的半導體裝置的三維視圖;第30圖顯示依據本發明的一個或多個態樣在蝕刻層間介電層以形成源/汲接觸溝槽以後的第29圖的半導體裝置的三維視圖;第31圖顯示依據本發明的一個或多個態樣的第30圖的半導體裝置的剖切立視圖;第32圖顯示依據本發明的一個或多個態樣在蝕刻以移除多晶矽層以後的第31圖的半導體裝置的剖切立視圖;第33圖顯示依據本發明的一個或多個態樣的第32圖的半導體裝置的三維視圖;第34圖顯示依據本發明的一個或多個態樣在沉積阻擋層並執行金屬填充製程以填充接觸以後的第33圖的半導體裝置的剖切立視圖;
第35圖顯示依據本發明的一個或多個態樣在執行平坦化以移除多餘金屬層、多餘阻擋層以及硬遮罩雙層以形成源/汲接觸以後的第34圖的半導體裝置的剖切立視圖;以及第36圖顯示依據本發明的一個或多個態樣的第35圖的半導體裝置的三維視圖。
下面通過參照圖式中所示的非限制性例子來更加充分地解釋本發明的態樣及其特定的特徵、優點以及細節。省略對已知材料、製造工具、製程技術等的說明,以免在細節上不必要地模糊本發明。不過,應當理解,當說明本發明的實施例時,詳細說明及具體例子僅作為示例,而非限制。所屬技術領域中具有通常知識者將會從本揭露中瞭解在基礎的發明概念的精神和/或範圍內的各種替代、修改、添加和/或佈局。還要注意,下面參照圖式,為方便理解,該些圖式並非按比例繪製,其中,不同圖式中所使用的相同元件符號表示相同或類似的組件。
一般來說,本文揭露特定半導體裝置,例如場效應電晶體(field-effect transistor;FET),其提供相對上述的現有半導體裝置及製程的優點。有利地,本文中所揭露的半導體裝置製程提供通過使用較少的遮罩所形成的裝置以及具有較大關鍵尺寸且疊置鬆弛的裝置。
在一個態樣中,如第1A圖中所示,顯示在半導體製程期間可使用的圖案化製程。依據本發明的一個或
多個態樣的該圖案化製程可包括例如:獲得具有基板的半導體裝置10;執行第一光刻以圖案化第一形狀20;執行第二光刻以圖案化與第一形狀的部分重疊的第二形狀30;處理該第一形狀及該第二形狀以在該重疊處形成隔離區40;以及形成由該隔離區分離的四個區域50。該圖案化製程可為例如布林運算。該布林運算影響分別由獨立的光刻製程印刷的兩個相交的形狀。該兩個相交形狀可經處理以形成四個形狀或分支,各形狀或分支與其它形狀或分支隔離。各形狀或分支可經形成而為電性獨立。該兩個形狀之間的交點將導致沒有圖案電性分離各該形狀或分支。
在另一個態樣中,在如第1B圖中所示的一個實施例中,依據本發明的一個或多個態樣的半導體裝置形成製程可包括例如:獲得具有形成於基板上方的第一光刻堆疊的半導體裝置100;執行光刻以圖案化第一源/汲過孔開口102;沉積第二光阻堆疊104;執行另一個光刻以圖案化第二源/汲過孔開口106;執行反應離子蝕刻108;執行濕式蝕刻110;執行蝕刻以移除氧化物及第二光阻堆疊112;執行氧化114;執行至少一個蝕刻116;形成間隙壁118;執行蝕刻停止層打穿及等向性蝕刻120;執行阻擋層打穿122;蝕刻以形成源/汲接觸溝槽124;以及執行源/汲接觸金屬化126。
第2至36圖顯示(僅示例)依據本發明的一個或多個態樣的第1A至1B圖的半導體裝置形成製程及中間半導體裝置200的部分的詳細實施例。再次注意,這些
圖式並非按比例繪製,以促進理解本發明,且不同圖式中所使用的相同元件符號表示相同或類似的元件。
第1A至1B圖的該半導體裝置形成製程的部分的一個詳細實施例顯示(僅示例)於第2至36圖中。第2圖顯示通過該製程所獲得的半導體裝置200的部分。裝置200可包括例如基板202。在一些實施例中,基板202可具有或為基本結晶基板材料(也就是塊體矽),而在其它實施例中,基板202可基於絕緣體上矽(silicon-on-insulator;SOI)架構或任意已知基板例如玻璃、氮化鎵(GaN)、砷化鎵(AsGa)、碳化矽(SiC)或類似物形成。
可依據所製造裝置200的設計通過初始製程步驟處理裝置200。例如,裝置200可包括沉積於基板202上的層間介電(interlayer dielectric;ILD)層204。ILD層204可為例如碳摻雜氧化物介電質,例如SiCOH及類似物,或這些常用介電材料的組合。裝置200也可包括硬遮罩雙層206、208,其可包括第一硬遮罩層206及第二硬遮罩層208。第一硬遮罩層206可為例如氮化矽(SiN)、氮氧化矽(SiON)、二氧化鈦(TiO2)、氮化鋁(AlN)、氮化鈦(TiN)、非晶矽(Si)層或類似物。第二硬遮罩層208可為例如TiN、SiN、SiON、TiO2、AlN層或類似物。裝置200也可包括多晶矽層210,例如非晶矽層。裝置200還可包括蝕刻停止層212,例如SiN或AlN層。在蝕刻停止層212上方可沉積氧化物層214。氧化物層214可為例如二氧
化矽(SiO2)層。最後,在氧化物層214上方可沉積第一光刻堆疊216。第一光刻堆疊216可為任意已知的光刻堆疊,例如,第一光刻堆疊216可包括旋塗硬遮罩、介電層、底部抗反射塗(bottom anti-reflection coating;BARC)層以及光阻層。該旋塗硬遮罩可為例如非晶碳膜。該介電層可為例如SiON膜。
接著,如第3圖中所示,通過使用第一遮罩可執行光刻,以圖案化第一光刻堆疊216,從而形成至少一個第一源/汲過孔圖案218。接著,可對裝置200執行蝕刻,以蝕刻至少一個第一源/汲過孔圖案218下方的氧化物層214,從而形成至少一個第一源/汲過孔開口220,如第4圖中所示。該蝕刻一旦完成,即可剝離第一光刻堆疊216,如第5及6圖中所示。接著,如第7圖中所示,在裝置200上方可沉積第二光刻堆疊222。第二光刻堆疊222可為任意已知的光刻堆疊,例如,第二光刻堆疊222可包括間隙填充及自平坦化旋塗硬遮罩、介電層、底部抗反射塗(BARC)層以及光阻層。第二光刻堆疊222的該第一層可填充至少一個第一過孔開口220。
接著,通過使用第二遮罩可執行光刻,以圖案化第二光刻堆疊222,從而形成至少一個第二源/汲過孔圖案224,如第8及9圖中所示。該光刻製程還可包括顯影製程以暴露區域226,該區域形成於至少一個第一源/汲過孔開口220與至少一個第二源/汲過孔圖案224重疊之處,如第8圖中所示。重疊區226可被處理成自對準塊區,
如下面更詳細所述。區域226暴露蝕刻停止層212的部分。接著,可對裝置200執行蝕刻,以暴露重疊區226中的多晶矽層210,如第10圖中所示。該蝕刻可為例如氮化物反應離子蝕刻,其對氧化物具有選擇性,且多晶矽層210可為例如非晶矽。接著,可執行濕式蝕刻以擴大至少一個第一源/汲過孔開口220與至少一個第二源/汲過孔圖案224之間的該分離,如第11圖中所示。該濕式蝕刻可為例如熱磷氮化物濕式蝕刻,其可蝕刻該蝕刻停止層212以形成凹槽227。該些凹槽227可擴大至少一個第一源/汲過孔開口220與至少一個第二源/汲過孔圖案224之間的該分離,以防止在由至少一個第一源/汲過孔開口220及至少一個第二源/汲過孔圖案224形成的最終源/汲接觸中的短路。接著,通過使用至少一個第二源/汲過孔圖案224可執行另一個蝕刻,以蝕刻進入氧化物層214,停止於蝕刻停止層212上並形成至少一個第二源/汲過孔開口228,如第12及13圖中所示。該濕式蝕刻及氧化物蝕刻可形成較大的重疊區230,如第13圖中所示。接著,可自裝置200剝離第二光刻堆疊222,如第14及15圖中所示。
或者,在執行該氮化物反應離子蝕刻以移除蝕刻停止層212的該未覆蓋部分以後,可執行另一個蝕刻,以向下移除氧化物214的部分至蝕刻停止層212,從而形成至少一個第二源/汲過孔開口228。接著,可自裝置200剝離第二光刻堆疊222。在剝離第二光刻堆疊222以後,可執行濕式蝕刻,以擴大過孔開口220、228之間的該
分離。該濕式蝕刻可為例如熱磷氮化物濕式蝕刻,其蝕刻該蝕刻停止層212,以形成凹槽227。
現在請參照第14、16及17圖,可對裝置200執行氧化。該氧化可為例如矽選擇性氧化,以在重疊區230上方形成硬遮罩層232,從而形成非晶矽自對準區塊,如第17圖中所示。硬遮罩層232可為例如氧化物層。也考慮硬遮罩層232可通過使用矽化、磊晶或間隙壁插塞形成,如所屬技術領域中具有通常知識者所已知。接著,可執行另一個蝕刻,以自過孔開口220、228移除蝕刻停止層212,從而暴露多晶矽層210,如第18圖中所示。
如第19及20圖中所示,可對裝置200執行另一個蝕刻,以移除過孔開口220、228中的多晶矽層210的部分,從而形成較深的過孔開口234、236,該些過孔開口向下延伸穿過氧化物層214、蝕刻停止層212及多晶矽層210至第二硬遮罩層208。接著,在裝置200上方可沉積間隙壁層238,包括沉積進入至少一個第一過孔開口234及至少一個第二過孔開口236中,如第21及22圖中所示。間隙壁層238可通過例如原子層沉積(atomic layer deposition;ALD)來沉積且可為例如二氧化矽(SiO2)、氮化矽(SiN)、氮氧化矽(SiON)、二氧化鈦(TiO2)、非晶矽,或類似物。接著,可執行蝕刻,以移除間隙壁層238的水平部分,從而形成側間隙壁238,如第23及24圖中所示。該蝕刻可為例如反應離子蝕刻(RIE),如受控RIE。
在形成側間隙壁238以後,可執行硬遮罩開
口製程,如第25至29圖中所示。首先,如第25及26圖中所示,可執行乾式蝕刻和/或短蝕刻,以打穿或移除至少一個第一過孔開口234及至少一個第二過孔開口236中的第二硬遮罩層208。接著,可執行等向性蝕刻,以移除側間隙壁238並形成過孔開口240、242,如第27及28圖中所示。該等向性蝕刻可為例如二氧化矽(SiO2)蝕刻或SiCoNiTM蝕刻。該等向性蝕刻也可蝕刻至少一個第一過孔開口240及至少一個第二過孔開口242中的氧化物層214的部分。另外,該等向性蝕刻可移除硬遮罩層232,以暴露自對準多晶矽區塊244。接著,可執行乾式蝕刻或RIE短蝕刻或打穿,以打穿第一硬遮罩層206並形成至少一個第一過孔開口246及至少一個第二過孔開口248,如第29圖中所示。該RIE短蝕刻可為例如氮化物蝕刻,其相對氧化物具有選擇性。
接著,可執行至少一個蝕刻,以形成源/汲接觸溝槽,如第30至33圖中所示。現在請參照第30及31圖,可執行蝕刻,以移除至少一個第一過孔開口246及至少一個第二過孔開口248中的ILD層204,從而形成至少一個第一源/汲接觸溝槽250及至少一個第二源/汲接觸溝槽252。該蝕刻可為例如對非晶矽具有選擇性的蝕刻。接著,如第32及33圖中所示,可執行另一個蝕刻以移除多晶矽層210,從而形成至少一個第一源/汲接觸溝槽254、256及至少一個第二源/汲接觸溝槽258、260,各接觸溝槽254、256、258、260由自對準區塊274分離。
最後,可執行金屬化製程,以形成源/汲接觸,如第34至36圖中所示。該金屬化製程可包括例如在裝置200上方及接觸溝槽254、256、258、260中沉積阻擋層262,如第34圖中所示。請繼續參照第34圖,該金屬化製程也可包括例如在裝置200上方執行金屬填充,以用金屬層264填充接觸溝槽254、256、258、260。接著,如第35及36圖中所示,可執行平坦化製程,以移除多餘金屬層264、多餘阻擋層262、第二硬遮罩層208及第一硬遮罩層206,從而形成至少一個第一源/汲接觸266、270以及至少一個第二源/汲接觸268、272。該平坦化可為例如使用過蝕刻的化學機械拋光(chemical mechanical planarization;CMP)。如第36圖中所示,各接觸266、268、270、272可隔開,在各接觸266、268、270、272之間提供電性隔離。
本文中所使用的術語僅是出於說明特定實施例的目的,並非意圖限制本發明。除非上下文中明確指出,否則本文中所使用的單數形式“一個”以及“該”也意圖包括複數形式。還應當理解,術語“包括”(以及任意形式的包括)、“具有”(以及任意形式的具有)以及“包含”(以及任意形式的包含)都是開放式連接動詞。因此,“包括”、“具有”或“包含”一個或多個步驟或元件的方法或裝置具有那些一個或多個步驟或元件,但並不限於僅僅具有那些一個或多個步驟或元件。類似地,“包括”、“具有”或“包含”一個或多個特徵的一種方法的步驟或一種
裝置的元件具有那些一個或多個特徵,但並不限於僅僅具有那些一個或多個特徵。而且,以特定方式配置的裝置或結構至少以那種方式配置,但也可以未列出的方式配置。
所述的申請專利範圍中的所有手段或步驟加功能元件的相應結構、材料、動作及均等物(如果有的話)意圖包括結合具體請求保護的其它請求保護的元件執行該功能的任意結構、材料或動作。本發明的說明用於示例及說明目的,而非意圖詳盡無遺或限於所揭露形式的發明。許多修改及變更將對於所屬技術領域中具有通常知識者顯而易見,而不背離本發明的範圍及精神。這些實施例經選擇及說明以最佳解釋本發明的一個或多個態樣的原理以及實際應用,並使本領域的其他普通技術人員能夠理解針對各種實施例具有適合所考慮的特定應用的各種變更的本發明的一個或多個態樣。
10~50‧‧‧步驟
Claims (20)
- 一種方法,包括:獲得中間半導體裝置;執行第一光刻,以圖案化第一形狀;執行第二光刻,以圖案化與該第一形狀的部分重疊的第二形狀;處理該第一形狀及該第二形狀,以在該重疊處形成隔離區;以及形成由該隔離區分離的四個區域。
- 如申請專利範圍第1項所述之方法,其中,該中間半導體裝置包括:基板;層間介電層,位於該基板上;硬遮罩雙層,位於該層間介電層上;多晶矽層,位於該硬遮罩雙層上;蝕刻停止層,位於該多晶矽層上;氧化物層,位於該蝕刻停止層上;以及第一光刻堆疊,位於該氧化物層上。
- 如申請專利範圍第2項所述之方法,其中,執行該第一光刻以圖案化該第一形狀包括:使用第一遮罩以形成至少一個第一過孔開口,其中,使用該第一遮罩以形成該至少一個第一過孔開口包括:曝光該第一遮罩,以在該第一光刻堆疊中形 成至少一個第一過孔圖案;蝕刻該氧化物層以形成該至少一個第一過孔開口;以及自該中間半導體裝置剝離該第一光刻堆疊。
- 如申請專利範圍第1項所述之方法,其中,該中間半導體裝置包括:基板;層間介電層,位於該基板上;硬遮罩雙層,位於該層間介電層上;多晶矽層,位於該硬遮罩雙層上;蝕刻停止層,位於該多晶矽層上;氧化物層,位於該蝕刻停止層上;以及第二光刻堆疊,位於該氧化物層上。
- 如申請專利範圍第4項所述之方法,其中,執行第二光刻以圖案化與該第一形狀的部分重疊的第二形狀包括:通過使用第二遮罩執行第二光刻,以形成至少一個第二過孔開口,其中,該至少一個第二過孔開口與至少一個第一過孔開口重疊,其中,通過使用該第二遮罩執行該第二光刻以形成該至少一個第二過孔開口包括:曝光該第二遮罩以在該第二光刻堆疊中形成至少一個第二過孔圖案;蝕刻該氧化物層以形成該至少一個第二過孔開口;以及自該中間半導體裝置剝離該第二光刻堆疊。
- 如申請專利範圍第5項所述之方法,其中,通過使用該第二遮罩執行該第二光刻以形成該至少一個第二過孔開口還包括:執行顯影製程,以暴露自對準區塊,在該自對準區塊處,該至少一個第一過孔開口與該至少一個第二過孔圖案重疊;蝕刻該中間半導體裝置,以暴露該自對準區塊的該多晶矽層;以及執行濕式蝕刻,以擴大該至少一個第一過孔開口與該至少一個第二過孔圖案之間的該分離,從而在該蝕刻停止層中形成凹槽。
- 如申請專利範圍第6項所述之方法,其中,用以形成該凹槽的該濕式蝕刻為熱磷氮化物濕式蝕刻。
- 如申請專利範圍第7項所述之方法,其中,形成由該隔離區分離的四個區域包括:自該至少一個第一過孔開口及該至少一個第二過孔開口形成至少四個接觸包括:執行氧化,以在該自對準區塊上形成硬遮罩層;執行第一蝕刻,以移除該蝕刻停止層的部分並暴露該至少一個第一過孔開口及該至少一個第二過孔開口中的該多晶矽層的部分;以及執行第二蝕刻,以移除該多晶矽層的部分並暴露該硬遮罩雙層的部分。
- 如申請專利範圍第8項所述之方法,其中,自該至少一個第一過孔開口及該至少一個第二過孔開口形成該至少四個接觸還包括:在該中間半導體裝置上方沉積間隙壁層;以及蝕刻該間隙壁層,以在該至少一個第一過孔開口及該至少一個第二過孔開口中形成側間隙壁。
- 如申請專利範圍第9項所述之方法,其中,自該至少一個第一過孔開口及該至少一個第二過孔開口形成該至少四個接觸還包括:執行乾式蝕刻,以移除該至少一個第一過孔開口及該至少一個第二過孔開口中的該硬遮罩雙層的第二硬遮罩層的部分;執行等向性蝕刻,以移除該至少一個第一過孔開口及該至少一個第二過孔開口中的該側間隙壁並移除該自對準區塊上的該硬遮罩層,從而暴露自對準多晶矽區塊;以及執行蝕刻,以移除該至少一個第一過孔開口及該至少一個第二過孔開口中的該硬遮罩雙層的該第一硬遮罩層的部分。
- 如申請專利範圍第10項所述之方法,其中,自該至少一個第一過孔開口及該至少一個第二過孔開口形成該至少四個接觸還包括:執行蝕刻,以移除該至少一個第一過孔開口及該至少一個第二過孔開口中的該層間介電層的部分,以形成 至少一個第一接觸溝槽及至少一個第二接觸溝槽;以及執行蝕刻,以自該中間半導體裝置移除該多晶矽層。
- 如申請專利範圍第11項所述之方法,其中,自該至少一個第一過孔開口及該至少一個第二過孔開口形成該至少四個接觸還包括:在該中間半導體裝置上方以及該至少一個第一接觸溝槽及至少一個第二接觸溝槽中沉積阻擋層;執行金屬填充製程,以在該中間半導體裝置上以及該至少一個第一接觸溝槽及至少一個第二接觸溝槽中沉積金屬層;以及執行平坦化,以移除多餘金屬層、多餘阻擋層以及該硬遮罩雙層,從而形成至少兩個第一接觸及至少兩個第二接觸。
- 一種中間半導體裝置,包括:基板;層間介電層,沉積於該基板上;硬遮罩雙層,位於該層間介電層上;多晶矽層,位於該硬遮罩雙層上;蝕刻停止層,位於該多晶矽層上;氧化物層,位於該蝕刻停止層上;以及至少一個第一開口,自該中間半導體裝置的頂部表面延伸穿過該氧化物層;至少一個第二開口,自該中間半導體裝置的該頂部 表面延伸穿過該氧化物層,其中,該至少一個第一開口與該至少一個第二開口重疊;以及自對準區塊,位於該至少一個第一開口與該至少一個第二開口重疊之處。
- 如申請專利範圍第13項所述之裝置,其中,該自對準區塊包括:該多晶矽層的部分;以及硬遮罩層,位於該多晶矽層的該部分上。
- 如申請專利範圍第14項所述之裝置,其中,該蝕刻停止層凹入該至少一個第一開口及該至少一個第二開口內的該氧化物層下方。
- 如申請專利範圍第13項所述之裝置,其中,該至少一個第一開口及該至少一個第二開口進一步延伸穿過該蝕刻停止層、該多晶矽層以及該硬遮罩雙層的第二硬遮罩層。
- 如申請專利範圍第16項所述之裝置,其中,該自對準區塊包括:該硬遮罩雙層的該第二硬遮罩層的部分;以及該硬遮罩雙層的該第二硬遮罩層的該部分上的該多晶矽層的部分。
- 如申請專利範圍第13項所述之裝置,其中,該至少一個第一開口及該至少一個第二開口進一步延伸穿過該蝕刻停止層、該多晶矽層以及該硬遮罩雙層。
- 如申請專利範圍第18項所述之裝置,其中,該自對準 區塊包括:該硬遮罩雙層的部分;以及該硬遮罩雙層的該部分上的該多晶矽層的部分。
- 如申請專利範圍第13項所述之裝置,其中,該至少一個第一開口形成延伸穿過該層間介電層的至少兩個第一接觸;其中,該至少一個第二開口形成延伸穿過該層間介電層的至少兩個第二接觸;以及其中,該自對準區塊電性分離各該至少兩個第一接觸與該至少兩個第二接觸。
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US15/136,384 US10262941B2 (en) | 2016-04-22 | 2016-04-22 | Devices and methods for forming cross coupled contacts |
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US11177132B2 (en) * | 2019-07-03 | 2021-11-16 | International Business Machines Corporation | Self aligned block masks for implantation control |
KR20220143382A (ko) | 2021-04-16 | 2022-10-25 | 삼성전자주식회사 | 비스듬한 절단면을 갖는 게이트 전극을 포함하는 집적회로 칩 및 이의 제조 방법 |
CN116207039B (zh) * | 2023-04-28 | 2023-07-21 | 合肥晶合集成电路股份有限公司 | 半导体结构的制作方法以及半导体结构 |
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US7151040B2 (en) | 2004-08-31 | 2006-12-19 | Micron Technology, Inc. | Methods for increasing photo alignment margins |
US7655387B2 (en) | 2004-09-02 | 2010-02-02 | Micron Technology, Inc. | Method to align mask patterns |
US7253118B2 (en) | 2005-03-15 | 2007-08-07 | Micron Technology, Inc. | Pitch reduced patterns relative to photolithography features |
US9230910B2 (en) * | 2006-03-09 | 2016-01-05 | Tela Innovations, Inc. | Oversized contacts and vias in layout defined by linearly constrained topology |
US8404581B2 (en) | 2009-09-29 | 2013-03-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming an interconnect of a semiconductor device |
KR20130096953A (ko) | 2012-02-23 | 2013-09-02 | 삼성전자주식회사 | 반도체 장치의 제조 방법 |
KR101926418B1 (ko) * | 2012-05-16 | 2018-12-10 | 삼성전자주식회사 | 반도체 소자의 제조 방법 |
US8987128B2 (en) * | 2012-07-30 | 2015-03-24 | Globalfoundries Inc. | Cross-coupling based design using diffusion contact structures |
CN103811338B (zh) * | 2012-11-08 | 2016-12-21 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制备方法 |
US8969207B2 (en) * | 2013-03-13 | 2015-03-03 | Globalfoundries Inc. | Methods of forming a masking layer for patterning underlying structures |
US9501601B2 (en) * | 2013-03-14 | 2016-11-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Layout optimization of a main pattern and a cut pattern |
US9601367B2 (en) | 2013-03-25 | 2017-03-21 | International Business Machines Corporation | Interconnect level structures for confining stitch-induced via structures |
US8969199B1 (en) * | 2013-10-15 | 2015-03-03 | Globalfoundries Inc. | Methods of forming a circuit that includes a cross-coupling gate contact structure wherein the circuit is to be manufactured using a triple patterning process |
US9520502B2 (en) | 2013-10-15 | 2016-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs having epitaxial capping layer on fin and methods for forming the same |
US9454631B2 (en) | 2014-05-23 | 2016-09-27 | International Business Machines Corporation | Stitch-derived via structures and methods of generating the same |
US9634125B2 (en) | 2014-09-18 | 2017-04-25 | United Microelectronics Corporation | Fin field effect transistor device and fabrication method thereof |
US9704862B2 (en) * | 2014-09-18 | 2017-07-11 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods for manufacturing the same |
US9640533B2 (en) | 2015-03-12 | 2017-05-02 | Globalfoundries Inc. | Methods, apparatus and system for providing source-drain epitaxy layer with lateral over-growth suppression |
US9530689B2 (en) | 2015-04-13 | 2016-12-27 | GlobalFoundries, Inc. | Methods for fabricating integrated circuits using multi-patterning processes |
CN106684032B (zh) * | 2015-11-05 | 2019-07-02 | 中芯国际集成电路制造(北京)有限公司 | 互连结构的形成方法和曝光对准系统 |
-
2016
- 2016-04-22 US US15/136,384 patent/US10262941B2/en not_active Expired - Fee Related
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- 2017-04-12 TW TW106112178A patent/TWI651764B/zh not_active IP Right Cessation
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CN107424922B (zh) | 2020-10-13 |
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CN107424922A (zh) | 2017-12-01 |
US20170309560A1 (en) | 2017-10-26 |
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