TW201640973A - 製造電性連接結構之方法 - Google Patents

製造電性連接結構之方法 Download PDF

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Publication number
TW201640973A
TW201640973A TW104140417A TW104140417A TW201640973A TW 201640973 A TW201640973 A TW 201640973A TW 104140417 A TW104140417 A TW 104140417A TW 104140417 A TW104140417 A TW 104140417A TW 201640973 A TW201640973 A TW 201640973A
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Taiwan
Prior art keywords
connection structure
conductive material
dry film
male
forming
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TW104140417A
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English (en)
Inventor
徐英郁
文永周
尹琮光
金榮洙
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Unid有限公司
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Publication of TW201640973A publication Critical patent/TW201640973A/zh

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01RELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R43/00Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors
    • H01R43/007Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors for elastomeric connecting elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • HELECTRICITY
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    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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    • H01R12/00Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
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    • H01R12/51Fixed connections for rigid printed circuits or like structures
    • H01R12/55Fixed connections for rigid printed circuits or like structures characterised by the terminals
    • H01R12/58Fixed connections for rigid printed circuits or like structures characterised by the terminals terminals for insertion into holes
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    • H01R12/00Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
    • H01R12/50Fixed connections
    • H01R12/59Fixed connections for flexible printed circuits, flat or ribbon cables or like structures
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    • H01ELECTRIC ELEMENTS
    • H01RELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R12/00Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
    • H01R12/70Coupling devices
    • H01R12/71Coupling devices for rigid printing circuits or like structures
    • H01R12/72Coupling devices for rigid printing circuits or like structures coupling with the edge of the rigid printed circuits or like structures
    • H01R12/73Coupling devices for rigid printing circuits or like structures coupling with the edge of the rigid printed circuits or like structures connecting to other rigid printed circuits or like structures
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    • H01ELECTRIC ELEMENTS
    • H01RELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/02Contact members
    • H01R13/22Contacts for co-operating by abutting
    • H01R13/24Contacts for co-operating by abutting resilient; resiliently-mounted
    • H01R13/2407Contacts for co-operating by abutting resilient; resiliently-mounted characterized by the resilient means
    • H01R13/2414Contacts for co-operating by abutting resilient; resiliently-mounted characterized by the resilient means conductive elastomers
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    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/325Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
    • H05K3/326Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor the printed circuit having integral resilient or deformable parts, e.g. tabs or parts of flexible circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007Surface contacts, e.g. bumps
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L2224/16237Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
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    • H05K2203/30Details of processes not otherwise provided for in H05K2203/01 - H05K2203/17
    • H05K2203/308Sacrificial means, e.g. for temporarily filling a space for making a via or a cavity or for making rigid-flexible PCBs
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    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4092Integral conductive tabs, i.e. conductive parts partly detached from the substrate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Metallurgy (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Manufacturing Of Electrical Connectors (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

本發明提供製造電性連接結構之方法,其中電性連接結構包含具有在母連接元件的插入孔內部的內導電材料的母連接結構,以及具有配置以被插入且固定於插入孔之中以接觸內導電材料,且形成以從公連接元件突出的導電柱體的公連接結構。該方法包含準備使用於母連接元件及公連接元件的絕緣元件,以及藉由使用微影製程圖樣化在各絕緣元件上之導電材料以形成內導電材料及柱體。

Description

製造電性連接結構之方法
本發明有關於一種製造用於印刷電路板、中介層、電子封裝及用於令其相互電性連接的連接器的內部與外部之間之電性連接的電性連接結構的方法。
需要電性連接結構以連接印刷電路板(PCB)及安裝在其上的裝置(例如,半導體材料封裝、被動裝置、主動裝置、顯示模組及電池),或連接PCB與其他PCB。
一般的電性連接結構可為用於電性連接的連接器,而連接器被用於連接不同的基板至彼此或用於連接基板及電子組件。
通常,用於電性連接的連接器為其中母連接結構與公連接結構彼此耦接的類型,且包含其中連接器使用焊接安裝在基板等上的焊接接合型,以及用於可拆卸耦接的插座型。
通常,用於電性連接的連接器藉由注入成型合成樹脂而被製造為具有特定的形狀。即,連接器是藉由將塑膠加熱及熔化、藉由高壓力注射進入模具之中、及當壓力仍被維持時,冷卻至固化來形成。
當用於電性連接的連接器是藉由注入成型製造時,支付大量的費用來製造模具,且存在當電性連接結構的設計被改變時,再次製造新模具的不方便。
此外,由於用於電性連接的連接器被製造為限於特定的形狀(例如,方形),連接器不應妨礙安裝在印刷電路板上結構(如其他組件或螺絲孔)。因此,問題在於電路設計的自由度因為增加了印刷電路板的尺寸而增加之安裝空間,或當設計電路時考慮到安裝連接器的空間而被抑制。
技術問題
本發明是針對提供一種製造電性連接結構的方法,其使用可能輕易地改變設計且增加安裝位置的程度及空間使用率的效益的印刷電路板的製造方法。
本發明的範疇不限於前述物件,所屬技術領域具有通常知識者可從下面的描述清楚地理解其他未提及的物件。 技術方案
本發明的一個態樣提供一種製造電性連接結構的方法,該電性連接結構包含具有在母連接元件的插入孔內部的內導電材料的母連接結構,以及具有配置以被插入且固定於插入孔之中以接觸內導電材料,且形成以從公連接元件突出的導電柱體的公連接結構。方法包含準備用於母連接元件及公連接元件的絕緣元件;以及藉由使用微影製程圖樣化在各絕緣元件上之導電材料以形成內導電材料及柱體。
根據製造電性連接結構的方法,母連接結構藉由下面的製程來製造,包含:形成插入孔在絕緣元件中,層疊電極層及第一乾膜在絕緣元件上,使用微影製程形成具有對應於插入孔的形狀的圖型孔在第一乾膜中,使用電鍍製程以導電材料填充插入孔,以及藉由在插入孔中蝕刻導電材料來形成內導電材料。
根據製造電性連接結構的方法,公連接結構藉由下面的製程來製造,包含:形成電極層及第二乾膜在絕緣元件上,使用微影製程形成柱體孔在第二乾膜中,以及使用電鍍製程以導電材料填充柱體孔來形成柱體。
根據製造電性連接結構的方法,公連接結構係藉由下面的補充製程來製造,包含:在層疊第二乾膜前層疊第三乾膜及第四乾膜在絕緣元件的兩側表面上,使用微影製程形成用於形成墊片(pad)的圖型孔在第三乾膜及第四乾膜中,以及藉由使用電鍍製程以導電材料填充在第三乾膜及第四乾膜中的圖型孔來形成墊片。
根據製造電性連接結構的方法,公連接結構藉由下面的補充製程來製造,包含:層疊第五乾膜以覆蓋柱體,使用微影製程形成具有對應於彈性片的形狀的圖型孔在第五乾膜中,以及藉由使用電鍍製程以導電材料填充在第五乾膜中的圖型孔來形成彈性片。
根據製造電性連接結構的方法,公連接結構藉由下面的補充製程來製造,包含:層疊分別製造在柱體上的彈性片。
同時,本發明的另一態樣提供一種製造電性連接結構的方法,該電性連接結構包含:具有在母連接元件的插入孔內部的內導電材料的母連接結構、及具有配置以被插入且固定至插入孔之中以接觸內導電材料形成,以從公連接元件突出且具有彈性片在柱體周圍的導電柱體的公連接結構,且公連接結構是藉由以下的製程來製造,包含:準備用於彈性片的金屬板,使用微影製程及鍍覆製程形成柱體在金屬板上,以及層疊用於公連接元件的絕緣元件在柱體上。
根據製造電性連接結構的方法,母連接元件或公連接元件包含主動裝置、被動裝置、用於電性連接的連接器、半導體材料晶片封裝、應用於半導體材料封裝的中介層、具有三維複數層結構的半導體材料晶片及封裝以及複數層陶瓷電容器中之至少其一。 技術效果
根據本發明的例示性實施例,電性連接結構是使用製造印刷電路板的方法來製造,其可能輕易地改變設計且增加安裝位置的程度及空間使用率的效益。
同樣,根據本發明的例示性實施例,優點在於因為不使用傳統的注入成型所以可節省製造模具的費用。
此外,功效在於許多電性連接結構可設置在小空間中,且可因為前述的電性連接結構而實施在連接結構之間的細節距。
此外,優點在於電子訊號速度可藉由實施低高度及接近線性結構的電性連接結構而增加,且訊號品質可藉由減少訊號損失而增加。
在本發明中所揭露的電性連接結構為涵蓋應用於如所有類型的行動電話、顯示裝置等的所有類型的電子裝置的印刷電路板與安裝在印刷電路板上的電子裝置之間,以及在印刷電路板與電性組件之間的電性連接的所有結構的概念。電性連接結構能夠被應用於如所有類型的行動電話、顯示裝置的電子裝置,且在這種情況下,本發明的電性連接結構可被提供在配置以形成電子裝置的外觀的外殼中。這樣的一個例示性實施例可為在安裝在外殼中的印刷電路板與安裝在其上的電子組件之間的電性連接結構。
以下,與本發明有關的可拆卸電性連接結構將參考附圖來詳細描述。
第6圖及第7圖為描繪根據本發明例示性實施例的電性連接結構的剖面圖。
如在第6圖及第7圖中所描繪的,根據本發明例示性實施例的電性連接結構包含藉由公母結構彼此耦接的母連接結構100及公連接結構200。第6圖描繪其中母連接結構100及公連接結構200彼此分離的狀態,而第7圖描繪其中母連接結構100及公連接結構200耦接的狀態。
母連接結構100及公連接結構200可被形成在印刷電路板中或可為配置以被安裝在印刷電路板上的獨立組件。舉例來說,母連接結構100或公連接結構200可包含主動裝置、被動裝置、連接器、應用於半導體材料封裝的中介層、半導體材料晶片封裝、具有三維複數層結構的半導體材料晶片及封裝以及複數層陶瓷電容器中之至少其一。
母連接結構100包含具有插入孔113及提供在插入孔113中的內導電材料120的母連接元件110。
母連接元件110可由絕緣材料或絕緣材料與導電材料的組合來形成。母連接元件110的原始材料可為陶瓷、聚合物、矽、玻璃及金屬等中之其一或超過一個的組合。
內導電材料120被提供在形成在母連接元件110中的插入孔113的內壁上。根據本發明的例示性實施例,插入孔113可具有內凹母連接元件110的表面(在第1圖及第2圖中的下表面)一預定深度而得到的形狀,且可具有圓柱形狀的內凹形狀。然而,插入孔113可具有這樣的形狀以及具有完全穿過母連接元件110的通孔形狀。
內導電材料120可具有以一預定厚度堆疊在插入孔113的內壁上的形狀。根據本發明的例示性實施例,內導電材料120是沿插入孔113的內壁邊緣形成。
公連接結構200包含公連接元件210、從公連接元件210突出的柱體220及從柱體220朝向外部方向延伸的彈性片230。
如母連接元件110,公連接元件210可由絕緣材料或絕緣材料與導電材料的組合形成。
柱體220具有導電材料及從公連接元件120突出的結構。在本發明的例示性實施例中,作為示例,柱體220被安裝在連接至公連接元件210的電路圖樣的墊片240上。
整個柱體220可由導電材料形成,或其外部表面可由導電材料形成而其內部可由絕緣材料形成。作為後者的一個示例,柱體220的內部可由聚合物、矽、玻璃等形成,而只有其外部表面可由導電材料形成。如在第7圖中所描繪,當母連接元件110面對公連接元件210時,柱體220被插入母連接元件110的插入孔113之中。
內導電材料120及柱體220可以陣列形狀設置在母連接元件110及公連接元件120上。舉例來說,內導電材料120及柱體220可能被設置為具有預定數量的行及列的矩陣形狀,或其他各種形狀。
第8圖為描繪在第6圖及第7圖中所描繪的柱體220及彈性片230的平面圖。
彈性片230具有一表面,該表面具有導電材料及配置以延伸至柱體220外部。當柱體220被插入插入孔113之中時,彈性片230被配置以藉由被彈性變形而彈性接觸內導電材料120。
當柱體220被插入插入孔113之中時,彈性片230可在柱體220的插入方向的相對方向彎曲,且可具有與柱體220整合之結構或具有其中附加層層疊在柱體220的上表面上的構造。
彈性片230可由能夠彈性變形的導電材料(例如,金屬)形成,或可藉由表面被塗覆有導電材料(例如,金屬)的彈性材料(例如,聚合物、纖維)來形成。
最好將彈性片230形成為複數個以接觸內導電材料120的複數個區域,而如在第8圖中所描繪,複數個彈性片230可沿柱體220的圓周方向設置以被以預定角度分隔開。儘管第8圖描繪其中四個彈性片230被設置為以90度分隔開的結構,但對彈性片230的數量及形狀做各種改變是可能的。舉例來說,彈性片230可形成為具有環形的複數個或一個。
母連接元件110及公連接元件210分別包含第一連接部分及第二連接部分,且可分別具有複數個其數量。第一連接部分及第二連接部分指配置以藉由在母連接元件110與公連接元件210之間的連接來電性連接的物件,且其示例可包含墊片(pads)、電路圖樣、凸塊(bumps)、焊接球、通路孔等。
根據本發明的例示性實施例,形成在母連接元件110的上表面上的墊片130被提供作為第一連接部分的一個示例,而形成在公連接元件210的下表面上的墊片250被提供作為第二連接部分的一個示例。
由導電材料(例如,金屬)形成的內導電材料120電性連接至第一連接部分,而作為示例,在第1圖及第2圖中的內導電材料120通過插入孔113的底部穿過母連接元件110來連接至墊片130。
柱體220電性連接至公連接元件210的第二連接部分,公連接元件210的下表面的墊片250能夠通過導電結構,如公連接元件210的上表面的墊片240及通路孔電性連接。
以下,是本發明的電性連接結構的操作狀態。
從如在第6圖中所描繪的母連接結構100及公連接結構200彼此分離的狀態,母連接結構100及公連接結構200可如在第7圖中所描繪的藉由將公連接元件210的柱體220插入母連接結構100的插入孔113之中而耦接。在柱體220插入插入孔113之中的過程中,彈性片230的彈性變形是藉由彈性片230被提供於插入孔113的內壁的內導電材料120擠壓而發生,而因此,彈性片230由於彈性片230所產生的恢復力而電性接觸內導電材料120。彈性恢復力用作為在母連接元件110及公連接元件210之間的耦接力,且使母連接元件110及公連接元件210不會變得任意彼此分離。
同時,因電性連接至公連接元件210的第二連接部分的彈性片230與電性連接至母連接元件110的第一連接部分的內導電材料120接觸,所以可能電性連接第一連接部分及第二連接部分。
如前所述,由於一同實施電性連接結構及物理耦接結構,所以不需要額外的物理耦接結構,且優點在於電性連接結構的總厚度能夠藉由在母連接元件110的內部以水平接觸結構實施電性連接結構而減少。此外,優點在於電子訊號速度可藉由實施低高度及接近線性結構的電性連接結構而增加,且訊號品質可藉由減少訊號損失而增加。
同時,儘管彈性片230被提供在柱體220的外部表面上的結構被描述為公連接結構200的結構,但其中不提供彈性片230的結構是可能的,而柱體220被插入及耦接插入孔113,且柱體220直接接觸內導電材料120。
以下,根據本發明例示性實施例的製造電性連接結構的方法將參考第2圖至第5圖描述。
根據本發明的製造電性連接結構的方法,其包含:準備用於母連接元件110及公連接元件210的絕緣元件101及絕緣元件201的製程,及藉由使用微影製程圖樣化在各絕緣元件101及絕緣元件201上之導電材料來形成內導電材料120及柱體220的製程。
以下,母連接結構100及公連接結構200的各製造製程將被詳細描述。
第2圖為描繪根據本發明例示性實施例的製造母連接結構的製程的順序圖。
如在第2圖(a)中所描繪,準備用於母連接元件110的絕緣元件101,而插入孔113被形成在絕緣元件101中。此時,可同時形成用於電性連接墊片130與內導電材料120的導電孔115。
然後,如在第2圖(b)中所描繪的層疊電極層102。如銅的導電膜可被用於電極層102,而當電鍍時這是用於連接電極的結構。
接著,如在第2圖(c)中所描繪,乾膜104被層疊,且使用微影製程將對應於插入孔113的圖型孔123形成在乾膜104中。在附著於絕緣元件101前,提前形成圖型孔123在乾膜104中是可能的。
此時,另一乾膜103被附著在相對於插入孔113的一側,對應於墊片130的圖型孔133可使用微影製程來形成。形成各圖型孔123及圖型孔133的微影製程可同時執行。
接著,如在第2圖(d)中所描繪,插入孔113使用電鍍製程以如銅的導電材料125填充。此時,可能同時以導電材料135填充在相對於插入孔113的一側中的圖型孔133。因此,用於內導電材料120的結構及用於墊片130的結構可藉由在插入孔113的內部及在相對於其的一側中的圖型孔133同時執行電鍍製程來同時形成。
接著,如在第2圖(e)中所描繪,內導電材料120的圖型是藉由機械或化學蝕刻在插入孔113中之導電材料125形成。此外,母連接結構100最後藉由剝離乾膜103及乾膜104,並使用機械或化學蝕刻移除一部分的電極層102來完成。
第3圖為描繪根據本發明第一實施例的公連接結構的製造製程的順序圖。
如在第3圖(a)中所描繪,準備用於公連接元件210的絕緣元件201,並將電極層202層疊在絕緣元件201的一個表面上。在本發明的例示性實施例的情況中,電極層203也形成在絕緣元件201的另一表面上以形成墊片250在相對表面上。在此製程中,可能形成如通路孔等的結構以電性連接絕緣元件201的頂部表面及底部表面。
接著,如在第3圖(b)中所描繪,乾膜204及乾膜205被層疊在電極層202及電極層203外部表面上,且使用微影製程形成圖型孔243及圖型孔253以形成墊片240及墊片250在各乾膜204及乾膜205中。
接著,如在第3圖(c)中所描繪,墊片240及墊片250藉由以如銅的導電材料填充乾膜204及乾膜205的圖型孔243及圖型孔253來形成。此時,電鍍製程可在通路孔的內部上執行以電性連接墊片240及墊片250。
接著,如在第3圖(d)中所描繪,乾膜206及乾膜207被層疊在其中形成柱體220及未形成柱體220的兩側表面上。然後,柱體孔223被形成在其中形成柱體的乾膜206中。柱體孔223也使用與前述的圖型孔243及圖型孔253相同的微影製程來形成。層疊在相對於柱體220的一側上的乾膜207用作為屏障以使電鍍不進一步地執行。
接著,如在第3圖(e)中所描繪,柱體結構220藉由使用電鍍製程以如銅的導電材料225填充柱體孔223來形成。在公連接結構200不需要形成彈性片230的情況下,公連接結構200藉由剝離乾膜204、205、206及207以及去除電極層202及電極層203的不需要的部分來完成。後續製程形成彈性片230。
如在第3圖(f)中所描繪,層疊乾膜208以覆蓋用於柱體220之導電材料225,而使用微影製程在乾膜208中形成具有對應於彈性片230的形狀的圖型孔233。
接著,如在第3圖(g)中所描繪,用於彈性片230的結構係藉由使用電鍍製程以如銅等的導電材料填充圖型孔233來形成。接著,如在第3圖(h)中所描繪,公連接結構200可藉由使用機械或化學蝕刻製程來剝離乾膜204、205、206、207及208,以及去除電極層202及電極層203的不需要的部分以最終完成。
第4圖為描繪根據本發明第二實施例的公連接結構的製造製程的順序圖。
除了形成彈性片230的製程之外,根據本發明的例示性實施例的公連接結構具有與前面的實施例相同的製程。即,第4圖(a)至第4圖(e)的製程與第3圖(a)至第3圖(e)的製程相同。
在本發明的這個實施例中的製造公連接結構的方法,直到形成柱體220的製程為止是相同的,自那以後,如在第4圖(f)中所描繪,將分別製造的彈性片230層疊在柱體220上。
第5圖為描繪根據本發明第三實施例的公連接結構的製造製程的順序圖。
根據本發明例示性實施例的製造公連接結構的方法具有與前面的實施例相反的順序,即,包含將柱體220及絕緣元件210依序層疊在用於彈性片230的金屬板301上的方法。
如在第5圖(a)中所描繪,準備用於彈性片230的金屬板301,且將乾膜302及乾膜303層疊在金屬板301的兩側表面上。
接著,如在第5圖(b)中所描繪,使用微影製程將對應於柱體220的柱體孔323形成在一側上的乾膜302中,且如在第5圖(c)中所描繪,柱體220藉由使用電鍍製程以如銅的導電材料325填充柱體孔323來形成。
接著,如在第5圖(e)中所描繪,層疊乾膜304,且將圖型孔343形成在乾膜304中以形成墊片240。接著,墊片240藉由以導電材料345填充圖型孔343來形成。
接著,如在第5圖(f)中所描繪,層疊用於公連接元件210的絕緣元件210。用於墊片250的金屬層306可能被層疊在絕緣元件210上,且自那以後,可另外包含用於其電性連接的通路孔製程及鍍覆製程等。
接著,如在第5圖(g)中所描繪,公連接結構藉由使用微影製程圖樣化金屬板301及金屬層306以形成彈性片230及墊片250,並去除乾膜302、303及304而被完成。
第1圖為描繪根據本發明的電性連接結構的各種形狀的示意圖。
第1圖描繪安裝在印刷電路板10上的各種形狀的電性連接結構A至D作為示例。在電性連接結構使用製造印刷電路板的方法製造的情況下,母連接元件110或公連接元件210可被製造為各種形狀,且因此,其設計可輕易地被改變。因此,安裝位置的程度被增加且可增加空間使用率的效率。
舉例來說,能夠設計避免螺絲孔15的佈置位置的結構D。
另外,優點在於內導電材料120或柱體220可設置在如藉由在第1圖中的結構A的放大圖描繪的各種形狀的母連接元件110或公連接元件210中。
有關於前述本發明的電性連接結構及其製造方法可被應用於各種領域,如用於電性連接的連接器、半導體材料封裝組合件、倒裝晶片的相互連接結構、複數層陶瓷電容器(MLCC)的電容器的相互連接結構及其他組件(或基板)等。
同時,前述的電性連接結構及其製造方法不限於的前述實施例的構造及方法,而實施例的各種改變可藉由選擇性地結合各實施例的全部或一部分來進行,且各種改變可由所屬技術領域具有通常知識者在不脫離本發明的精神及範疇下進行。
10‧‧‧印刷電路板 15‧‧‧螺絲孔 100‧‧‧母連接結構 101、201‧‧‧絕緣元件 102、202、203‧‧‧電極層 103、104、204、205、206、207、208、302、303、304‧‧‧乾膜 110‧‧‧母連接元件 113‧‧‧插入孔 115‧‧‧導電孔 120‧‧‧內導電材料 123、133、233、243、253、343‧‧‧圖型孔 125、135、225、325、345‧‧‧導電材料 130、240、250‧‧‧墊片 200‧‧‧公連接結構 210‧‧‧公連接元件 220‧‧‧柱體 223、323‧‧‧柱體孔 230‧‧‧彈性片 301‧‧‧金屬板 306‧‧‧金屬層 A、B、C、D‧‧‧結構
第1圖為描繪根據本發明的電性連接結構的各種形狀的示意圖。
第2圖為描繪根據本發明例示性實施例的製造母連接結構的製程的順序圖。
第3圖為描繪根據本發明第一實施例的公連接結構的製造製程的順序圖。
第4圖為描繪根據本發明第二實施例的公連接結構的製造製程的順序圖。
第5圖為描繪根據本發明第三實施例的公連接結構的製造製程的順序圖。
第6圖及第7圖為描繪根據本發明例示性實施例的可拆卸電性連接結構的剖面圖。
第8圖為描繪在第6圖及第7圖中所描繪的柱體及彈性片的平面圖。
101‧‧‧絕緣元件
102‧‧‧電極層
103、104‧‧‧乾膜
110‧‧‧母連接元件
113‧‧‧插入孔
115‧‧‧導電孔
120‧‧‧內導電材料
123、133‧‧‧圖型孔
125、135‧‧‧導電材料
130‧‧‧墊片

Claims (9)

  1. 一種製造電性連接結構的方法,該電性連接結構包含具有在一母連接元件的一插入孔內部的一內導電材料的一母連接結構,以及具有配置以被插入且固定於該插入孔之中以接觸該內導電材料,且形成以從一公連接元件突出的一導電柱體的一公連接結構,該方法包含: 準備用於該母連接元件及該公連接元件的複數個絕緣元件;以及 藉由使用微影製程圖樣化在該複數個絕緣元件中的每一個絕緣元件上之導電材料以形成該內導電材料及該導電柱體。
  2. 如申請專利範圍第1項所述之方法,其中該母連接結構係藉由下面的製程來製造: 形成該插入孔在該絕緣元件中; 層疊一電極層及一第一乾膜在該絕緣元件上; 使用微影製程形成具有對應於該插入孔的形狀的一圖型孔在該第一乾膜中; 使用電鍍製程以導電材料填充該插入孔;以及 藉由蝕刻導電材料來形成該內導電材料在該插入孔中。
  3. 如申請專利範圍第2項所述之方法,其中電鍍該內導電材料時,同時電鍍配置以形成連接至該內導電材料的一墊片的結構。
  4. 如申請專利範圍第1項所述之方法,其中該公連接結構係藉由下面的製程來製造: 層疊一電極層及一第二乾膜在該絕緣元件上; 使用微影製程形成一柱體孔在該第二乾膜中;以及 藉由使用電鍍製程以導電材料填充該柱體孔來形成該導電柱體。
  5. 如申請專利範圍第4項所述之方法,其中該公連接結構係藉由下面的補充製程來製造: 在層疊該第二乾膜前層疊一第三乾膜及一第四乾膜在該絕緣元件的兩側表面上; 使用微影製程形成用於形成一墊片的一圖型孔在該第三乾膜及該第四乾膜中;以及 藉由使用電鍍製程以導電材料填充在該第三乾膜及該第四乾膜中的該圖型孔來形成該墊片。
  6. 如申請專利範圍第4項所述之方法,其中該公連接結構係藉由下面的補充製程來製造: 層疊一第五乾膜以覆蓋該導電柱體; 使用微影製程形成具有對應於一彈性片的形狀的一圖型孔在該第五乾膜中;以及 藉由使用電鍍製程以導電材料填充在該第五乾膜中的該圖型孔來形成該彈性片。
  7. 如申請專利範圍第4項所述之方法,其中該公連接結構係藉由下面的補充製程來製造: 層疊分別製造的一彈性片在該導電柱體上。
  8. 一種製造電性連接結構的方法,該電性連接結構包含具有在一母連接元件的一插入孔內部的一內導電材料的一母連接結構,以及具有配置以被插入且固定於該插入孔之中以接觸該內導電材料、形成以從一公連接元件突出且具有一彈性片在其周圍的一導電柱體的一公連接結構, 其中,該公連接結構係藉由下面的製程來製造: 準備用於該彈性片的一金屬板; 使用微影製程及鍍覆製程形成該導電柱體在該金屬板上;以及 層疊用於該公連接元件的一絕緣元件在該導電柱體上。
  9. 如申請專利範圍第1項至第8項中之任一項所述之方法,其中該母連接元件或該公連接元件包含主動裝置、被動裝置、用於電性連接的連接器、半導體材料晶片封裝、應用於半導體材料封裝的中介層、具有三維複數層結構的半導體材料晶片及封裝以及複數層陶瓷電容器中之至少其一。
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