TW201626511A - 附有Ag基材層之功率模組用基板及功率模組 - Google Patents

附有Ag基材層之功率模組用基板及功率模組 Download PDF

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TW201626511A
TW201626511A TW104132185A TW104132185A TW201626511A TW 201626511 A TW201626511 A TW 201626511A TW 104132185 A TW104132185 A TW 104132185A TW 104132185 A TW104132185 A TW 104132185A TW 201626511 A TW201626511 A TW 201626511A
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layer
substrate
base material
glass
power module
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TW104132185A
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TWI651814B (zh
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西元修司
長友義幸
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三菱綜合材料股份有限公司
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Abstract

本發明係一種附有Ag基材層之功率模組用基板及功率模組,其中,本發明之附有Ag基材層之功率模組用基板係具備加以形成於絕緣層之一方的面之電路層,和加以形成於前述電路層之Ag基材層的附有Ag基材層之功率模組用基板,其特徵為前述Ag基材層係由加以形成於前述電路層側之玻璃層,和加以層積形成於此玻璃層之Ag層所成,而前述Ag基材層係自與前述Ag層之前述玻璃層相反側的面,使入射光入射,在經由拉曼分光法所得到之拉曼光譜中,將自3000cm-1至4000cm-1的波數範圍之強度最高值作為IA,而將自450cm-1至550cm-1的波數範圍之強度最高值作為IB時,IA/IB則為1.1以上者。

Description

附有Ag基材層之功率模組用基板及功率模組
本發明係有關加以形成有電路層於絕緣層之一方的面之附有Ag基材層之功率模組用基板,及使用此之功率模組。
本申請係依據於2014年9月30,加以申請於日本國之日本特願2014-200878號、及於2015年9月18日,加以申請於日本國之日本特願2015-185296號而主張優先權,將其內容援用於此。
LED或功率模組等之半導體裝置係具備加以接合有半導體元件於導電材料所成之電路層上之構造。
為了控制風力發電,電動汽車,油電混合汽車等而加以使用之大電力控制用之功率半導體元件係發熱量為多。因此,作為搭載如此之功率半導體元件之基板,係自以往加以廣泛使用具備:例如AlN(氮化鋁)、Al2O3(氧化鋁)等之陶瓷基板所成之絕緣層,和於此絕緣層之一方的面,配設導電性優越之金屬而形成之電路層的功率模組用 基板。
並且,如此之功率模組用基板係於其電路層上,藉由焊錫材而加以搭載作為功率元件之半導體元件(例如,參照專利文獻1)。
作為構成電路層之金屬,係一般而言,加以使用鋁或鋁合金,或者銅或銅合金。
在此,在鋁或鋁合金所成之電路層中,係於表面加以形成有鋁的自然氧化膜之故,良好地進行經由焊錫材與半導體元件的接合者則為困難。
另外,在銅或銅合金所成之電路層中,係所熔融之焊錫材與銅則產生反應,對於電路層之內部係侵入有焊錫材的成分,而有電路層之特性產生劣化之虞。
因此,以往係如專利文獻1所示,形成Ni電鍍膜於電路層的表面之後,經由焊錫材而實施半導體元件。
另一方面,做為未使用焊錫材之接合方法,例如,對於專利文獻2係加以提案有使用Ag奈米電糊而接合半導體元件之技術。
另外,對於專利文獻3,4,係加以提案有使用包含金屬氧化物粒子與有機物所成之還原劑的氧化物電糊而接合半導體元件之技術。
但如專利文獻2所揭示地,對於未使用焊錫材而使用Ag奈米電糊而接合半導體元件之情況,係Ag奈米電糊所成之接合層則比較於焊錫材,厚度則加以薄化形成之故,熱循環負荷時之應力則容易作用於半導體元 件,而有半導體元件本身產生破損之虞。
另外,如專利文獻3,4所揭示地,對於使用金屬氧化物與還原劑而接合半導體元件之情況,依然,從氧化物電糊之燒成層則加以薄化形成之情況,熱循環負荷時之應力則容易作用於半導體元件,而有功率模組之性能產生劣化之虞。
因此,例如,對於專利文獻5~7,係加以提案有使用玻璃含有Ag電糊而於鋁或銅所成之電路層上,形成Ag基材層之後,藉由焊錫材或Ag電糊而接合電路層與半導體元件而接合電路層與半導體元件之技術。在此技術中,於鋁或銅所成之電路層的表面,經由塗佈玻璃含有Ag電糊而進行燒成之時,使加以形成於電路層之表面的氧化被膜反應於玻璃而除去,形成Ag基材層,於加以形成有此Ag基材層之電路層上,藉由焊錫材而接合半導體元件。
在此,Ag基材層係具備:經由玻璃則與電路層之氧化被膜反應而加以形成之玻璃層,和加以形成於此玻璃層上之Ag層。對於此玻璃層係分散有導電性粒子,而經由此導電性粒子而加以確保玻璃層之導通。
[先前技術文獻] [專利文獻]
[專利文獻1]日本特開2004-172378號公報
[專利文獻2]日本特開2008-208442號公報
[專利文獻3]日本特開2009-267374號公報
[專利文獻4]日本特開2006-202938號公報
[專利文獻5]日本特開2010-287869號公報
[專利文獻6]日本特開2012-109315號公報
[專利文獻7]日本特開2013-012706號公報
但對於為了使電路層與Ag基材層之接合信賴性提升,係增加玻璃含有Ag電糊中之玻璃的含有量者則為有效果。
但當增加玻璃含有Ag電糊中之玻璃的含有量時,在Ag基材層中,玻璃層則變厚。玻璃層係即使加以分散導電性粒子,與Ag層等做比較時,電性阻抗亦高。因此,隨著玻璃層變厚,Ag基材層之電性阻抗值亦有變大的傾向,而使接合信賴性與電性阻抗值之雙方平衡者則為困難。如此,當Ag基材層之電性阻抗值為高時,在藉由焊錫材等而接合加以形成有Ag基材層之電路層與半導體元件時,而有成為無法確保電路層與半導體元件等之電子構件之間的導電性之虞。
此發明係有鑑於前述情事所做為之構成,其目的即使為形成具有玻璃層與Ag層之Ag基材層於電路層上之情況,亦提供充分地降低在Ag基材層之電性阻抗 值之附有Ag基材層之功率模組用基板,功率模組者。
為了解決如此之課題而達成前述目的,本發明之一形態之附有Ag基材層之功率模組用基板係具備加以形成於絕緣層之一方的面之電路層,和加以形成於前述電路層之Ag基材層的附有Ag基材層之功率模組用基板,其中,前述Ag基材層係由加以形成於前述電路層側之玻璃層,和加以層積形成於此玻璃層之Ag層所成,而前述Ag基材層係自與前述Ag層之前述玻璃層相反側的面,使入射光入射,在經由拉曼分光法所得到之拉曼光譜中,將自3000cm-1至4000cm-1的波數範圍之強度最高值作為IA,而將自450cm-1至550cm-1的波數範圍之強度最高值作為IB時,IA/IB則為1.1以上。
作為Ag基材層,經由拉曼分光法之拉曼光譜的特性則為上述之範圍者係加以提高在Ag基材層之Ag離子的移動度者,而即使具有玻璃層,成為亦可大幅度地降低在Ag基材層之電性阻抗值者。因而,成為可提供提高Ag基材層之導電性的附有Ag基材層之功率模組用基板者。
前述Ag基材層係在其厚度方向之電性阻抗值則為10mΩ以下。
此情況,從在Ag基材層之厚度方向的電性阻抗值則為10mΩ以下者,經由加以確保在此Ag基材層之導電 性,而於Ag基材層上搭載半導體元件之時,可得到通電損失少之功率模組者。
前述Ag基材層係玻璃含有Ag電糊之燒成體。
經由此,可自玻璃層,和加以層積形成於此玻璃層之Ag層而構成,而可經由Ag層,提高玻璃層之導電性者。
前述Ag基材層之中,與前述玻璃層相反側的面係進行導電性提升處理的面。
經由此,可實現加以提高Ag基材層之導電性,而大幅度地降低電性阻抗值之附有Ag基材層之功率模組用基板。
本發明之一形態的功率模組係具備:前述各項記載之附有Ag基材層之功率模組用基板,和半導體元件,而前述半導體元件係對於前述Ag基材層而言,藉由接合層而加以接合。
如根據此構成之功率模組,即使於Ag基材層具有玻璃層,亦可大幅度地降低在Ag基材層之電性阻抗值者。因而,可提供對於接合信賴性優越,且確實地加以電性接合電路層與半導體元件之功率模組者。
如根據本發明,即使為形成具有玻璃層與Ag層於電路層上之Ag基材層之情況,亦成為可提供可充分地降低在Ag基材層之電性阻抗值之附有Ag基材層之功 率模組,功率模組。
1‧‧‧功率模組
10‧‧‧附有Ag基材層之功率模組用基板
11‧‧‧陶瓷基板(絕緣層)
12‧‧‧電路層
30‧‧‧Ag基材層
30A‧‧‧高壓噴射面(導電性提升處理面)
31‧‧‧玻璃層
32‧‧‧Ag層
圖1係本發明之實施形態的功率模組之概略說明圖。
圖2係本發明之實施形態的附有Ag基材層之功率模組用基板之概略說明圖。
圖3係顯示Ag基材層與電路層之接合部份之要部擴大剖面圖。
圖4係顯示附有Ag基材層之功率模組用基板之製造方法的一例的流程圖。
圖5係顯示附有Ag基材層之功率模組用基板之製造方法的一例的概略說明圖。
圖6係顯示Ag基材層之厚度方向的電性阻抗值之測定方法的上面說明圖。
圖7係顯示Ag基材層之厚度方向的電性阻抗值之測定方法的側面說明圖。
圖8係觀察在實施例中,導電性提升處理之一例之作為高壓噴射處理之Ag基材層之上面的相片。
圖9係顯示經由Ag基材層之拉曼分光的拉曼光譜之圖表。
以下,對於本發明之實施形態,參照附加的 圖面加以說明。
於圖1,顯示本發明之實施形態的功率模組1。此功率模組1係具備:附有Ag基材層之功率模組用基板10,和藉由接合層2而加以接合於此附有Ag基材層之功率模組用基板10之一方的面(在圖1中為上面)之半導體元件3,和加以配置於附有Ag基材層之功率模組用基板10之另一方的面(在圖1中為下側)之散熱板41。作為半導體元件3係可使用IGBT等之功率半導體元件或LED等之發光元件者。
附有Ag基材層之功率模組用基板10係如圖2所示,具備:構成絕緣層之陶瓷基板11,和加以配設於此陶瓷基板11之一方的面(在圖2中為上面)之電路層12,和加以配設於陶瓷基板11之另一方的面(在圖2中為下面)之金屬層13,和加以形成於電路層12之一方的面之Ag基材層30。
陶瓷基板11係為防止電路層12與金屬層13之間之電性連接的構成,例如,由絕緣性高之AlN(氮化鋁),Si3N4(氮化矽),Al2O3(氧化鋁)等加以構成。在本實施形態中,以散熱性優越之AlN(氮化鋁)而加以構成。另外,陶瓷基板11之厚度係加以設定為0.2mm~1.5mm之範圍內,而在本實施形態中,加以設定為0.635mm。
電路層12係如圖5所示,於陶瓷基板11之一方的面,經由加以接合具有導電性之金屬板22之時而 加以形成。在本實施形態中,電路層12係經由純度為99.99mass%以上的鋁(所謂,4N鋁)之延壓板所成之鋁板則加以接合於陶瓷基板11之時而加以形成。然而,對於電路層12係加以形成有電路圖案,而其一方的面(在圖1中為上面)係作為加以搭載有半導體元件3之搭載面。在此,電路層12(金屬板22)之厚度係加以設定為0.2mm以上3.0mm以下之範圍內,而在本實施形態中,加以設定為0.6mm。
金屬層13係如圖5所示,於陶瓷基板11之另一方的面,經由加以接合金屬板23之時而加以形成。在本實施形態中,金屬層13係由純度為99.99mass%以上的鋁(所謂,4N鋁)之延壓板所成之鋁板則加以接合於陶瓷基板11者而加以形成。在此,金屬層13(金屬板23)之厚度係加以設定為0.2mm以上3.0mm以下之範圍內,而在本實施形態中,加以設定為1.6mm。
Ag基材層30係例如,作為包含玻璃成份之玻璃含有Ag電糊之燒成體。此Ag基材層30係在接合半導體元件3之前的狀態中,如圖2及圖3所示,具備加以形成於電路層12側之玻璃層31,和加以形成於此玻璃層31上之Ag層32。
對於玻璃層31內部係加以分散有粒徑為數毫微米程度之微細的導電性粒子33。此導電性粒子33係作為含有Ag或Al之至少一方之結晶性粒子。然而,玻璃層31內之導電性粒子33係例如,由使用透過型電子顯微鏡 (TEM)者而加以觀察。導電性粒子33係加以推測在燒成時,析出於玻璃層31內部者。
另外,對於Ag層32內部係加以分散有粒徑為數毫微米程度之微細的玻璃粒子(略圖示)。
然而,玻璃層31及Ag層32係認為玻璃含有Ag電糊則燒成時,產生軟化而具有流動性之玻璃則經由Ag之粒成長而使其移動至與電路層12之界面附近之時而形成。
另外,在本實施形態中,從由電路層12為純度99.99mass%以上的鋁而加以構成之情況,對於電路層12之表面,係加以形成在大氣中自然產生之鋁氧化被膜12A。在此,在加以形成有前述Ag基材層30之部分中,加以除去此鋁氧化被膜12A,而於電路層12上直接加以形成有Ag基材層30。也就是,如圖3所示,加以直接接合構成電路層12的鋁與玻璃層31。鋁氧化被膜12A係由與玻璃含有Ag電糊中的玻璃反應者而加以除去。氧化被膜係在玻璃中,作為鋁氧化物而產生溶解。一部分係與Bi2O3或ZnO等之玻璃的成分同時,亦有作為複合氧化物結晶而析出者。
在本實施形態中,如圖3所示,自然產生於電路層12上之鋁氧化被膜12A的厚度to則作為4nm≦to≦6nm。另外,呈成為玻璃層31之厚度tg為0.01μm≦tg≦5μm、後述之高壓噴射處理前之Ag層32的厚度ta為1μm≦ta≦100μm、Ag基材層30全體厚度t1為1.01 μm≦t1≦105μm地加以構成。
如此之構成的Ag基材層30係在使用拉曼分光測定裝置,自與Ag層32之玻璃層31相反側的面30A,使入射光(光源光)入射,經由拉曼分光法所得到之拉曼光譜中,將自3000cm-1至4000cm-1的波數範圍之強度最高值作為IA,而將自450cm-1至550cm-1的波數範圍之強度最高值作為IB時,IA/IB則為1.1以上。此IA/IB則係1.2以上為佳,而1.5以上為更佳。IA/IB係越大越佳,但極度地使IA/IB加大者係招致成本的增加。因此,IA/IB係理想為1.9以下。
當於Ag基材層30,例如,使單波長之入射光入射時,對於構成Ag基材層30之分子產生衝突,而其一部分係加以散射。此散射光的成分係其大部分則為與入射光相同波數之瑞利散射光,但一部分為與入射光不同之波數域的光之拉曼散射光。入射光與拉曼散射光的能帶隙係反應Ag基材層30之分子構造。
構成Ag基材層30之Ag單體係未經由拉曼分光而發現特定之波數峰值之故,經由Ag基材層30之拉曼分光而產生之特定之波數峰值係認為經由含於Ag基材層30之氧化物而產生。因應含於Ag基材層30之Ag的量,拉曼光譜係產生變化。例如,在將波數3500cm-1作為中心之波數3000cm-1~4000cm-1的範圍中,拉曼光譜則產生變化,而產生有波數峰值。在如此作為之波數域的波數峰值係Ag則作為離子化而成為Ag+。因此,在將波數 3500cm-1作為中心之波數3000cm-1~4000cm-1的範圍的波數峰值係關連於作為載體之離子的移動度,而顯示波數峰值之強度變越高,加以提高Ag基材層30之導電性者。
作為一例,使用包含5wt%玻璃成分之Ag基材層30,自Ag層32的面30A,使入射光入射,經由拉曼分光法所得到之拉曼光譜之測定例,示於圖9。如根據此圖9所示之測定結果的一例,加以觀察將波數3500cm-1作為中心之峰值。即,將自3000cm-1至4000cm-1的波數範圍之強度最高值作為IA,而將自450cm-1至550cm-1的波數範圍之強度最高值作為IB時,IA/IB則如為1.1以上時,構成Ag基材層30之Ag則作為離子化而成為Ag+,加以顯示Ag基材層30之導電性為高者。然而,圖9中的(A)之光譜係顯示IA/IB則為1.1以上的例,而(B)的光譜係顯示IA/IB則不足1.1的例。
在本實施形態中,係Ag基材層30的面(在圖3中為上面)30A係作為導電性提升處理面。即,於與Ag層32之玻璃層31相反側的面,經由進行導電性提升處理之時,使Ag之離子化促進而作為Ag+,使Ag基材層30之導電性提升。經由進行如此作為之導電性提升處理之時,可將經由上述拉曼分光法所得到之拉曼光譜之IA/IB作為1.1以上者。
作為導電性提升處理之具體例之一,可舉出高壓噴射處理。即,在本實施形態中,導電性提升處理係為高壓噴射面30A。在此高壓噴射面30A中,由對於Ag 層32而言使高壓噴射研磨粒衝突者而加以形成,具備因應高壓噴射研磨粒之形狀的凹凸。
在高壓噴射面30A之表面粗度Ra係作為0.35μm以上1.50μm以下即可。當表面粗度Ra則不足0.35μm時,高壓噴射處理則成為不充分而有電性阻抗降低之虞。當表面粗度Ra則超過1.50μm時,高壓噴射面30A則變過粗,在經由焊錫等而接合半導體元件時,產生有空隙,而有熱阻抗上升之虞。表面粗度Ra係0.40μm以上1.0μm以下則更佳,但並不限定於此等者。
經由形成此高壓噴射面30A的高壓噴射處理,對於Ag層32係加以負載壓力,而消除Ag層32內部之氣孔。另外,加以形成Ag層32之一部分則與電路層12直接接觸之處。
於與Ag層32之玻璃層31相反側的面,作為導電性提升處理之一例,進行高壓噴射處理時,例如,於作為Ag基材層30之玻璃成分而使用Bi2O3-ZnO-B2O3系玻璃之情況,B-O-B之交聯構造則變化為非交聯構造B-O-,另外,Ag則變化為Ag+。經由如此作為之高壓噴射處理等之導電性提升處理,Ag基材層30之厚度方向的電性阻抗值P係例如,可作為10mΩ以下者。Ag基材層30之厚度方向的電性阻抗值P係5mΩ以下為佳,而1mΩ以下更佳,但並不限定於此。Ag基材層30之厚度方向的電性阻抗值P係越小越佳,但極度地使電性阻抗值P降低者係招致成本之增加。因此,Ag基材層30之厚度方向 的電性阻抗值P係亦可為0.4mΩ以上。
在此,在本實施形態中,在Ag基材層30之厚度方向的電性阻抗值係作為Ag基材層30之上面與電路層12之上面之間的電性阻抗值。此係因構成電路層12之4N鋁的電性阻抗則比較於Ag基材層30之厚度方向之電性阻抗而為非常的小之故。然而,對於此電性阻抗的測定時,係如圖6及圖7所示,測定Ag基材層30之上面中央點,和僅與自Ag基材層30之前述上面中央點至Ag基材層30之端部為止之距離同距離,自Ag基材層30端部遠離之電路層12上的點之間的電性阻抗。
並且,在本實施形態之功率模組1中,於半導體元件3與Ag基材層30之間加以設置接合層2。作為接合層2係例如,可舉出焊錫層。作為形成焊錫層之焊錫材係例如,可舉出Sn-Ag系、Sn-In系、或是Sn-Ag-Cu系。
散熱板41係為了冷卻前述附有Ag基材層之功率模組用基板10者,具備為了流通冷卻媒體(例如,冷卻水)之流路42。在本實施形態中,散熱板41係作為鋁或鋁合金所成之多孔管。在本實施形態中,金屬層13與散熱板41係例如,藉由Al-Si等之焊接填料金屬而加以接合。
接著,對於可使用於Ag基材層30之形成的玻璃含有Ag電糊而加以說明。
此玻璃含有Ag電糊係含有Ag粉末,和玻璃粉末, 和樹脂,和溶劑,和分散劑,而Ag粉末和玻璃粉末所成之粉末成分的含有量則作為玻璃含有Ag電糊全體之60質量%以上90質量%以下,殘留部則作為樹脂,溶劑,分散劑。
然而,在本實施形態中,Ag粉末和玻璃粉末所成之粉末成分的含有量係作為玻璃含有Ag電糊全體之85質量%。
另外,此玻璃含有Ag電糊係加以調整為其黏度為10Pa.s以上500Pa.s以下、更理想為50Pa.s以上300Pa.s以下。
Ag粉末係其粒徑則作為0.05μm以上1.0μm以下,而在本實施形態中,使用平均粒徑0.8μm者。
玻璃粉末係例如,含有氧化鉛,氧化鋅,氧化矽,氧化硼,氧化磷及氧化鉍之任1種或2種以上,其軟化溫度則作為600℃以下。在本實施形態中,由氧化鉛與氧化鋅與氧化硼所成,使用平均粒徑為0.5μm之玻璃粉末。
另外,Ag粉末之重量A與玻璃粉末之重量G之重量比A/G係加以調整為自80/20至99/1之範圍內,在本實施形態中,做成A/G=80/5。
溶劑係沸點則200℃以上者為佳,在本實施形態中,使用乙二醇二丁醚。
樹脂係調整玻璃含有Ag電糊的黏度者,以500℃以上加以分解者為佳。在本實施形態中,使用乙基纖維。
另外,在本實施形態中,添加二羧酸系之分散劑。然 而,未添加分散劑而構成玻璃含有Ag電糊亦可。
此玻璃含有Ag電糊係將混合Ag粉末與玻璃粉末之混合粉末,和混合溶劑與樹脂之有機混合物,與分散劑同時,經由混合器而作為預備混合,將所得之預備混合物,經由輥軋機而揉搓同時進行混合後,經由電糊過濾機而過濾所得到之調和物而加以製造出。
接著,對於本發明之附有Ag基材層之功率模組用基板10之製造方法的一例,參照圖4及圖5而加以說明。
首先,準備成為電路層12之金屬板22及成為金屬層13之金屬板23,將此等金屬板22,23,各藉由焊接填料金屬26而層積於陶瓷基板11之一方的面及另一方的面,再經由加壓.加熱後冷卻之時,接合金屬板22,23與陶瓷基板11(電路層及金屬層形成工程S01)。
然而,在此電路層及金屬層形成工程S01中,作為焊接填料金屬26,使用Al-7.5mass%Si焊接填料金屬箔,將焊接溫度設定為640℃~650℃。
接著,於電路層12之一方的面,形成Ag基材層30(Ag基材層形成工程S02)。
在此Ag基材層形成工程S02中,首先,於電路層12之一方的面,塗佈玻璃含有Ag電糊(塗佈工程S21)。然而,對於在塗佈玻璃含有Ag電糊時,係可採用網版印刷法,平板印刷法,感光性處理等之種種手段者。在本實施形態中,經由網版印刷法而將玻璃含有Ag電糊形成為 圖案狀。
以塗佈玻璃含有Ag電糊於電路層12之一方的面之狀態,裝入致加熱爐內而進行玻璃含有Ag電糊的燒成(燒成工程S22)。然而,此時之燒成溫度係例如,加以設定為350℃~645℃。
經由此燒成工程S22,加以形成具備玻璃層31與Ag層32之Ag基材層30。此時,經由玻璃層31,成為加以熔融除去自然發生於電路層12表面之鋁氧化被膜12A者,而直接加以形成玻璃層31於電路層12。另外,對於玻璃層31內部係加以分散有粒徑為數毫微米程度之微細的導電性粒子33。此導電性粒子33係作為含有Ag或Al之至少一方的結晶性粒子,加以推測在燒成時,析出於玻璃層31內部者。
接著,對於Ag基材層30(Ag層32)之中,與電路層12相反側的面而言,進行導電性提升處理,例如高壓噴射處理,作為高壓噴射面30A(高壓噴射處理工程S23)。
在此高壓噴射處理工程S23中,係作為高壓噴射粒而可使用新莫氏硬度2~7之二氧化矽等之玻璃粒子,陶瓷粒子,金屬粒子,或者樹脂製珠粒等者。在本實施形態中,使用玻璃粒子。另外,高壓噴射粒之粒徑係作為20μm以上150μm以下的範圍內。
另外,高壓噴射壓力係做為0.05MPa以上0.8MPa以下之範圍內,將加工時間作為1秒以上10秒以下之範圍 內。
由如此之作為,如於Ag基材層30進行高壓噴射處理(導電性提升處理),使用拉曼分光測定裝置,自與Ag層32之玻璃層31相反側的面30A,使入射光(光源光)入射,經由拉曼分光法所得到之拉曼光譜中,將自3000cm-1至4000cm-1的波數範圍之強度最高值作為IA,而將自450cm-1至550cm-1的波數範圍之強度最高值作為IB時,IA/IB則為1.1以上,加以離子化Ag而加以形成導電性提升之Ag基材層30。
如以上作為,加以製造本實施形態之附有Ag基材層之功率模組用基板10。
接著,於金屬層13之另一方的面側,藉由焊接填料金屬而層積散熱板41,經由進行加壓.加熱後冷卻之時,接合散熱板41與金屬層13(散熱板接合工程S03)。
然而,在此散熱板接合工程S03中,作為焊接填料金屬,使用Al-10mass%Si焊接填料金屬箔,將焊接溫度設定為590℃~610℃。
並且,於Ag基材層30之高壓噴射面30A,藉由焊錫材而載置IGBT等之功率半導體元件或LED等之發光元件等之半導體元件3,在還原爐內中進行銲錫接合(半導體元件接合工程S04)。
此時,對於經由焊錫材而加以形成之接合層2,係構成Ag基材層30之Ag層32之一部分或全部則產生熔 融。
經由此,加以製作出藉由接合層2而將半導體元件3加以接合於電路層12上之功率模組1。
如根據有關作為如以上構成之本實施形態的功率模組1及附有Ag基材層之功率模組用基板10,於電路層12之一方的面,加以形成玻璃層31與加以層積形成於此玻璃層31之Ag層32所成之Ag基材層30,而因於此Ag基材層30之中,與電路層12相反的面,進行導電性提升處理,例如高壓噴射處理而形成高壓噴射面30A之故,使Ag之離子化促進而成為Ag+,而Ag基材層30之導電性則提升。加以實施導電性提升處理的Ag基材層30係顯示自與Ag層32之玻璃層31相反側的面30A,使入射光(光源光)入射,經由拉曼分光法所得到之拉曼光譜中,將自3000cm-1至4000cm-1的波數範圍之強度最高值作為IA,而將自450cm-1至550cm-1的波數範圍之強度最高值作為IB時,IA/IB則為1.1以上之特性。
另外,在形成此高壓噴射面30A之高壓噴射處理工程S03中,可賦予壓力至Ag層32,加以排除Ag層32內部之氣孔,更且,成為於Ag層32之一部分,加以形成與電路層12直接接觸之部分者,而成為可大幅度地降低在Ag基材層30之電性阻抗值者。
在此,在本實施形態中,在高壓噴射處理工程S03中,因將新莫氏硬度作為2以上7以下之範圍的玻璃粒子,作為高壓噴射研磨粒而使用之故,未有經由高壓 噴射處理而加以除去Ag層32之情況,而可確實地賦予壓力至Ag層32,而成為可大幅度地降低在Ag基材層30之電性阻抗值者。
另外,從在Ag基材層30之厚度方向的電性阻抗值則為10mΩ以下者,經由加以確保在此Ag基材層30之導電性,而於Ag基材層30,藉由接合層2而接合半導體元件3之時,可得到通電損失少之功率模組1者。
以上,對於本發明之實施形態已做過說明,但本發明係未加以限定於此等,而在不脫離其發明之技術思想範圍,可作適宜變更。
例如,在本實施形態中,於與Ag層32之玻璃層31相反側的面30A,作為導電性提升處理,進行高壓噴射處理,但對於高壓噴射處以外,如為使Ag基材層30之Ag的離子化促進而使導電性提升之處理即可,並無加以限定於特定之處理方法者。
另外,在本實施形態中,作為將構成電路層及金屬層之金屬板做成純度99.99mass%之純鋁(4N鋁)之延壓板者加以說明過,但並無加以限定於此,而亦可以其他的鋁或鋁合金而加以構成。另外,將構成電路層及金屬層之金屬板,以銅或銅合金而構成亦可。更且,將銅板與鋁板做成固相擴散接合之構造亦可。
另外,作為由焊接而結合鋁板與陶瓷基板者,已說明過,但並非限定於此者,而亦可適用過渡液相接合法(Transient Liquid Phase Bonding)、鑄造法等。
更且,對於構成電路層及金屬層之金屬板,由銅或銅合金而構成之情況,在接合銅或銅合金所成之金屬板於陶瓷基板時,可適用直接接合法(DBC法)、活性金屬焊接法,鑄造法等者。
另外,作為絕緣層而使用AlN所成之陶瓷基板者加以說明過,但並非限定於此者,亦可使用Si3N4或Al2O3等所成之陶瓷基板,而亦可經由絕緣樹脂而構成絕緣層。
更且,在本實施形態中,作為於Ag基材層上,藉由焊錫材而接合半導體元件者而加以說明過,但並非限定於此者,而使用氧化銀電糊,包含銀粒子之電糊,包含Ag粉末之導電性接著劑等而接合半導體元件於Ag基材層上亦可。此情況,從成為Ag彼此之接合之情況,可使半導體元件與Ag基材層之接合信賴性提升者。
然而,作為氧化銀電糊,係可使用含有氧化銀粉末,和還原劑,和樹脂,和溶劑,和有機金屬化合物粉末者。氧化銀粉末之含有量則作為氧化銀電糊全體之60質量%以上80質量%以下,還原劑之含有量則作為氧化銀電糊全體之5質量%以上15質量%以下,有機金屬化合物粉末之含有量則作為氧化銀電糊全體之0質量%以上10質量%以下,而殘留部則作為溶劑者為佳。在此,在氧化銀電糊中,為了在燒結後,抑制殘存有未反應之有機物情況,而未添加分散劑或樹脂者為佳。
另外,散熱板係並非限定於在本實施形態所 例示之構成者,而對於散熱板的構造未特別有限定。
更且,對於散熱板與金屬層之間,設置緩衝層亦可。作為緩衝層,係可使用鋁或鋁合金,或是包含鋁之複合材(例如,AlSiC等)所成之板材者。
[實施例]
對於為了確認本發明之有效性而進行之確認實驗加以說明。
於陶瓷基板之一方的面,接合金屬板而形成電路層。在此,陶瓷基板係作為AlN,而尺寸係作為27mm×17mm×0.6mm。成為電路層之金屬板係作為表1所示之材質,尺寸係作為25mm×15mm×0.3mm。
然而,對於金屬板為鋁板之情況,係作為接合材而使用Al-Si系焊接填料金屬。另外,對於金屬板為銅板之情況,係作為接合材而使用活性金屬焊接填料金屬(Ag-Cu-Ti焊接填料金屬)。
於電路層的表面,經由塗佈在實施形態所說明之玻璃含有Ag電糊而進行加熱處理之時,形成Ag基材層。
然而,作為玻璃含有Ag電糊之玻璃粉末,使用包含90.6質量%之Bi2O3,2.6質量%之ZnO,6.8質量%之B2O3的無鉛玻璃粉末。另外,作為樹脂而使用乙基纖維,而作為溶劑而使用二乙二醇二甲醚。更且,添加二羧酸系之分散液。
在此,調整在玻璃含有Ag電糊之Ag粉末之重量A與玻璃粉末之重量G的重量比A/G,及塗佈量,如表1所示地,調整玻璃層與Ag層之厚度。
並且,對於所燒成之Ag基材層而言,作為導電性提升處理,以表1所示之條件而實施高壓噴射處理,形成高壓噴射面。所形成之高壓噴射面之觀察結果,示於圖8。在此,圖8(a)係高壓噴射處理前之Ag基材層,圖8(b)係以本發明例7之條件而進行高壓噴射處理之Ag基材層,圖8(c)係以本發明例1之條件進行高壓噴射處理之Ag基材層。
然而,在比較例1-3中,未實施高壓噴射處理。
對於所得到之本發明例1-12及比較例1-3之附有Ag基材層之功率模組用基板,經由記載於圖6及圖7之方法,使用測試器(KEITHLEY公司製:2010MULTIMETER),測定Ag基材層之厚度方向的電性阻抗值。電性阻抗之測定係在Ag基材層之上面中央點,和作為自Ag基材層之上面中央點至Ag基材層端部為止之距離H之情況,自Ag基材層端部僅H離開之電路層上的點之間加以進行。
另外,測定高壓噴射處理後之Ag基材層表面(高壓噴射面)之表面粗度Ra。測定係使用雷射顯微鏡VK-X200(KEYENCE公司製及裝置附屬軟體之VK-Analyzer),將對物鏡倍率作為20倍,測定3視野,將其平均值做成表面粗度Ra。然而,在未實施高壓噴射處 理之比較例1-3中,未加以進行表面粗度Ra之測定。
另外,使用顯微雷射拉曼分光分析裝置(股分有限公司堀場製作所製:型號XploRA),將入射光(光源光)的波長作為532nm,測定本發明例1-12及比較例1-3之Ag基材層之拉曼光譜。並且,自所得到之拉曼光譜之3000cm-1至4000cm-1之波數範圍的強度之最高值(IA)及450cm-1至550cm-1之波數範圍的強度之最高值(IB),算出IA/IB。然而,測定處係作為Ag基材層上之玻璃的範圍,積算次數係作為3次。
將以上的各評估結果示於表1。
在對於Ag基材層進行高壓噴射處理而形成高壓噴射面之本發明例1-12中,對於具有同一厚度之玻璃層及Ag層之比較例1-3而言,電性阻抗率則變低。
在本發明例1-12中,將拉曼光譜之3000cm-1至4000cm-1之波數範圍的強度之最高值作為IA、將450cm-1至550cm-1之波數範圍的強度之最高值作為IB時,IA/IB則為1.1以上。另一方面,在比較例1-3中,IA/IB則不足1.0。
從以上的情況,如根據本發明,加以確認到可提供具備電性阻抗低之Ag基材層之附有Ag基材層之功率模組用基板者。
[產業上之利用可能性]
如根據本發明之功率模組,即使於Ag基材層具有玻璃層,亦可大幅度地降低在Ag基材層之電性阻抗值者。因此,本發明之功率模組係對於為了控制風力發電,電動汽車,油電混合汽車等所使用之大電力控制用之功率半導體元件為最佳。
10‧‧‧附有Ag基材層之功率模組用基板
11‧‧‧陶瓷基板(絕緣層)
12‧‧‧電路層
13‧‧‧金屬層
30‧‧‧Ag基材層
31‧‧‧玻璃層
32‧‧‧Ag層

Claims (5)

  1. 一種附有Ag基材層之功率模組用基板,係具備加以形成於絕緣層之一方的面之電路層,和加以形成於前述電路層之Ag基材層的附有Ag基材層之功率模組用基板,其特徵為前述Ag基材層係由加以形成於前述電路層側之玻璃層,和加以層積形成於此玻璃層之Ag層所成,前述Ag基材層係顯示自與前述Ag層之前述玻璃層相反側的面,使入射光入射,經由拉曼分光法所得到之拉曼光譜中,將自3000cm-1至4000cm-1的波數範圍之強度最高值作為IA,而將自450cm-1至550cm-1的波數範圍之強度最高值作為IB時,IA/IB則為1.1以上者。
  2. 如申請專利範圍第1項記載之附有Ag基材層之功率模組用基板,其中,前述Ag基材層係在其厚度方向之電性阻抗值為10mΩ以下者。
  3. 如申請專利範圍第1項或第2項記載之附有Ag基材層之功率模組用基板,其中,前述Ag基材層係為含有玻璃之Ag電糊之燒成體者。
  4. 如申請專利範圍第1項乃至第3項任一項記載之附有Ag基材層之功率模組用基板,其中,前述Ag基材層之中,與前述玻璃層相反側的面係為加以進行導電性提升處理的面。
  5. 一種功率模組,其特徵為具備:如申請專利範圍第1項乃至第4項任一項記載之附有Ag基材層之功率模 組用基板,和半導體元件,前述半導體元件係對於前述Ag基材層而言,藉由接合層而加以接合者。
TW104132185A 2014-09-30 2015-09-30 附有Ag基材層之功率模組用基板及功率模組 TWI651814B (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107634037A (zh) * 2017-03-02 2018-01-26 天津开发区天地信息技术有限公司 高导热封装基板

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JP2017135374A (ja) * 2016-01-22 2017-08-03 三菱マテリアル株式会社 接合体、パワーモジュール用基板、パワーモジュール、接合体の製造方法及びパワーモジュール用基板の製造方法
US10104759B2 (en) * 2016-11-29 2018-10-16 Nxp Usa, Inc. Microelectronic modules with sinter-bonded heat dissipation structures and methods for the fabrication thereof

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3922166B2 (ja) 2002-11-20 2007-05-30 三菱マテリアル株式会社 パワーモジュール用基板の製造方法並びにパワーモジュール用基板及びパワーモジュール
JP2006202938A (ja) 2005-01-20 2006-08-03 Kojiro Kobayashi 半導体装置及びその製造方法
JP4737116B2 (ja) 2007-02-28 2011-07-27 株式会社日立製作所 接合方法
US8513534B2 (en) 2008-03-31 2013-08-20 Hitachi, Ltd. Semiconductor device and bonding material
US8586860B2 (en) * 2008-08-08 2013-11-19 Kyosemi Corporation See-through type solar battery module
JP5212298B2 (ja) 2009-05-15 2013-06-19 三菱マテリアル株式会社 パワーモジュール用基板、冷却器付パワーモジュール用基板、パワーモジュール及びパワーモジュール用基板の製造方法
DE102009029577B3 (de) * 2009-09-18 2011-04-28 Infineon Technologies Ag Verfahren zur Herstellung eines hochtemperaturfesten Leistungshalbleitermoduls
CN102347426A (zh) * 2010-07-26 2012-02-08 旭硝子株式会社 发光元件搭载用基板、其制造方法及发光装置
JP5720454B2 (ja) 2010-07-26 2015-05-20 旭硝子株式会社 発光素子搭載用基板とその製造方法および発光装置
JP5707886B2 (ja) 2010-11-15 2015-04-30 三菱マテリアル株式会社 パワーモジュール用基板、冷却器付パワーモジュール用基板、パワーモジュールおよびパワーモジュール用基板の製造方法
JP5966379B2 (ja) 2011-05-31 2016-08-10 三菱マテリアル株式会社 パワーモジュール、及び、パワーモジュールの製造方法
JP5664625B2 (ja) * 2012-10-09 2015-02-04 三菱マテリアル株式会社 半導体装置、セラミックス回路基板及び半導体装置の製造方法
JP6085968B2 (ja) * 2012-12-27 2017-03-01 三菱マテリアル株式会社 金属部材付パワーモジュール用基板、金属部材付パワーモジュール、及び金属部材付パワーモジュール用基板の製造方法
JP6115215B2 (ja) * 2013-03-15 2017-04-19 三菱マテリアル株式会社 パワーモジュール用基板の製造方法及びパワーモジュールの製造方法
EP3089209B1 (en) * 2013-12-25 2019-12-04 Mitsubishi Materials Corporation Substrate for power module, method for manufacturing same, and power module

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107634037A (zh) * 2017-03-02 2018-01-26 天津开发区天地信息技术有限公司 高导热封装基板

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