CN106489198A - 具有Ag基底层的功率模块用基板及功率模块 - Google Patents

具有Ag基底层的功率模块用基板及功率模块 Download PDF

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Publication number
CN106489198A
CN106489198A CN201580035464.9A CN201580035464A CN106489198A CN 106489198 A CN106489198 A CN 106489198A CN 201580035464 A CN201580035464 A CN 201580035464A CN 106489198 A CN106489198 A CN 106489198A
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layer
basal layer
basal
module substrate
power module
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CN201580035464.9A
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CN106489198B (zh
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西元修司
长友义幸
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Mitsubishi Materials Corp
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Mitsubishi Materials Corp
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Priority claimed from PCT/JP2015/077290 external-priority patent/WO2016052392A1/ja
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Abstract

本发明的具有Ag基底层的功率模块用基板，其具备形成于绝缘层的一个表面的电路层及形成于所述电路层的Ag基底层，所述具有Ag基底层的功率模块用基板的特征在于，所述Ag基底层包括形成于所述电路层侧的玻璃层和层压形成于该玻璃层的Ag层，所述Ag基底层中，从所述Ag层的与所述玻璃层相反侧的表面射入入射光，通过拉曼光谱法得到的拉曼光谱中，将3000cm‑1至4000cm‑1的波数范围中的强度最高值设为IA，将450cm‑1至550cm‑1的波数范围中的强度最高值设为IB时，IA/IB为1.1以上。

Description

具有Ag基底层的功率模块用基板及功率模块
技术领域
该发明涉及一种在绝缘层的一个表面形成有电路层的具有Ag基底层的功率模块用基板及使用该基板的功率模块。
本申请主张基于2014年9月30日于日本申请的专利申请2014-200878号、及2015年9月18日于日本申请的专利申请2015-185296号的优先权，并将其内容援用于此。
背景技术
LED或功率模块等半导体装置具备在包括导电材料的电路层上接合有半导体元件的结构。
为了控制风力发电、电动汽车、混合动力汽车等而使用的大功率控制用的功率半导体元件的热值较多。因此，作为搭载这种功率半导体元件的基板，从以往就广泛使用例如具备包括AlN(氮化铝)、Al2O3(氧化铝)等陶瓷基板的绝缘层、及将导电性优异的金属配设于该绝缘层的一个表面而形成的电路层的功率模块用基板。
并且，这种功率模块用基板在其电路层上通过焊材搭载有作为功率元件的半导体元件(例如，参考专利文献1)。
作为构成电路层的金属，通常可使用铝或铝合金、或者铜或铜合金。
在此，包括铝或铝合金的电路层中，在表面形成有铝的自然氧化膜，因此难以通过焊材良好地接合半导体元件。
并且，包括铜或铜合金的电路层中，熔化的焊材与铜进行反应而在电路层的内部浸入焊材的成分，有可能使电路层的特性劣化。
为此，以往如专利文献1所示，在电路层的表面形成有Ni镀膜之后，通过焊材实施半导体元件。
另一方面，作为不使用焊材的接合方法，例如在专利文献2中提出有使用Ag纳米浆料来接合半导体元件的技术。
并且，在专利文献3、4中提出有使用含有金属氧化物粒子和包括有机物的还原剂的氧化物浆料来接合半导体元件的技术。
然而，如专利文献2中所公开，不使用焊材而是使用Ag纳米浆料来接合半导体元件的情况下，与焊材相比，包括Ag纳米浆料的接合层的厚度形成得较薄，因此热循环负荷时的应力容易作用于半导体元件而有可能导致半导体元件本身破损。
并且，如专利文献3、4中所公开，使用金属氧化物和还原剂来接合半导体元件的情况下，氧化物浆料的烧成层也依然形成得较薄，因此热循环负荷时的应力容易作用于半导体元件而有可能使功率模块的性能劣化。
于是，例如专利文献5～7中提出有如下技术：使用含玻璃的Ag浆料在包括铝或铜的电路层上形成Ag基底层之后，通过焊材或Ag浆料来接合电路层和半导体元件。在该技术中，在包括铝或铜的电路层的表面涂布含玻璃的Ag浆料并烧成，由此使形成于电路层的表面的氧化皮膜与玻璃进行反应并进行去除而形成Ag基底层，并在形成有该Ag基底层的电路层上通过焊材来接合半导体元件。
在此，Ag基底层具备通过玻璃与电路层的氧化皮膜进行反应来形成的玻璃层及形成于该玻璃层上的Ag层。该玻璃层中分散有导电性粒子，通过该导电性粒子可确保玻璃层的导通。
专利文献1：日本特开2004-172378号公报
专利文献2：日本特开2008-208442号公报
专利文献3：日本特开2009-267374号公报
专利文献4：日本特开2006-202938号公报
专利文献5：日本特开2010-287869号公报
专利文献6：日本特开2012-109315号公报
专利文献7：日本特开2013-012706号公报
但是，为了提高电路层与Ag基底层的接合可靠性，有效的是使含玻璃的Ag浆料中的玻璃的含量增加。
然而，若增加含玻璃的Ag浆料中的玻璃含量，则Ag基底层中玻璃层变厚。玻璃层中即使分散有导电性粒子，与Ag层等进行比较时电阻也较高。因此，随着玻璃层变厚，Ag基底层的电阻值也有变大的倾向，很难使接合可靠性与电阻值这两者平衡。如此，若Ag基底层的电阻值较高，则通过焊材等接合形成有Ag基底层的电路层与半导体元件时，有可能无法确保电路层与半导体元件等电子组件之间的导电性。
发明内容
该发明是鉴于前述的情况而完成的，其目的在于提供一种即使在电路层上形成具有玻璃层和Ag层的Ag基底层的情况下也充分降低Ag基底层中的电阻值的具有Ag基底层的功率模块用基板及功率模块。
为了解决这种课题并实现所述目的，本发明的一方式的具有Ag基底层的功率模块用基板，具备形成于绝缘层的一个表面的电路层、及形成于所述电路层的Ag基底层，所述Ag基底层包括形成于所述电路层侧的玻璃层和层压形成于该玻璃层的Ag层，所述Ag基底层中，从所述Ag层的与所述玻璃层相反侧的表面射入入射光，通过拉曼光谱法得到的拉曼光谱中，将3000cm-1至4000cm-1的波数范围中的强度最高值设为IA，将450cm-1至550cm-1的波数范围中的强度最高值设为IB时，IA/IB为1.1以上。
作为Ag基底层，基于拉曼光谱法的拉曼光谱的特性在上述范围时，Ag基底层中的Ag离子的迁移率得到提高，即使具有玻璃层也有可能大幅降低Ag基底层中的电阻值。从而，能够提供一种提高Ag基底层的导电性的具有Ag基底层的功率模块用基板。
所述Ag基底层中在其厚度方向上的电阻值为10mΩ以下。
此时，由于Ag基底层的厚度方向上的电阻值为10mΩ以下，因此确保该Ag基底层中的导电性，并通过在Ag基底层上搭载半导体元件，能够得到通电损耗较少的功率模块。
所述Ag基底层为含玻璃的Ag浆料的烧成物。
由此，能够由玻璃层和层压形成于该玻璃层的Ag层构成，能够通过Ag层提高玻璃层的导电性。
所述Ag基底层中与所述玻璃层相反侧的表面为进行了提高导电性处理的表面。
由此，能够实现提高Ag基底层的导电性并大幅降低电阻值的具有Ag基底层的功率模块用基板。
本发明的一方式的功率模块具备所述各项记载的具有Ag基底层的功率模块用基板和半导体元件，所述半导体元件通过接合层接合于所述Ag基底层。
根据该结构的功率模块，即使在Ag基底层具有玻璃层也能够大幅降低Ag基底层中的电阻值。从而，能够提供接合可靠性优异且可靠地电接合电路层与半导体元件的功率模块。
根据本发明，能够提供一种即使在电路层上形成具有玻璃层和Ag层的Ag基底层的情况下也能够充分降低Ag基底层中的电阻值的具有Ag基底层的功率模块及功率模块。
附图说明
图1是作为本发明的实施方式的功率模块的示意图。
图2是作为本发明的实施方式的具有Ag基底层的功率模块用基板的示意图。
图3是表示Ag基底层与电路层的接合部分的主要部分放大剖视图。
图4是表示具有Ag基底层的功率模块用基板的制造方法的一例的流程图。
图5是表示具有Ag基底层的功率模块用基板的制造方法的一例的示意图。
图6是表示Ag基底层的厚度方向的电阻值的测量方法的顶视说明图。
图7是表示Ag基底层的厚度方向的电阻值的测量方法的侧视说明图。
图8是观察实施例中进行了作为提高导电性处理的一例的喷砂处理的Ag基底层的上表面的照片。
图9是表示Ag基底层的基于拉曼光谱法的拉曼光谱的图表。
具体实施方式
以下，参考附图对本发明的实施方式进行说明。
图1表示作为本发明的实施方式的功率模块1。该功率模块1具备：具有Ag基底层的功率模块用基板10；半导体元件3，通过接合层2接合于该具有Ag基底层的功率模块用基板10的一个表面(图1中上表面)；及散热片41，配置于具有Ag基底层的功率模块用基板10的另一个表面(图1中下侧)。作为半导体元件3能够使用IGBT等功率半导体元件或LED等发光元件。
如图2所示，具有Ag基底层的功率模块用基板10具备：构成绝缘层的陶瓷基板11；配设于该陶瓷基板11的一个表面(图2中上表面)的电路层12；配设于陶瓷基板11的另一个表面(图2中下表面)的金属层13；及形成于电路层12的一个表面的Ag基底层30。
陶瓷基板11为防止电路层12与金属层13之间的电连接的基板，例如，由绝缘性较高的AlN(氮化铝)、Si3N4(氮化硅)、Al2O3(氧化铝)等构成。在本实施方式中，由散热性优异的AlN(氮化铝)构成。并且，陶瓷基板11的厚度设定在0.2～1.5mm的范围内，在本实施方式中设定为0.635mm。
如图5所示，电路层12通过在陶瓷基板11的一个表面接合具有导电性的金属板22来形成。在本实施方式中，电路层12通过将包括纯度为99.99mass％以上的铝(所谓的4N铝)的轧制板的铝板接合于陶瓷基板11来形成。另外，该电路层12形成有电路图案，该一个表面(图1中上表面)设为搭载半导体元件3的搭载面。在此，电路层12(金属板22)的厚度设定在0.2mm以上且3.0mm以下的范围内，在本实施方式中设定为0.6mm。
如图5所示，金属层13通过在陶瓷基板11的另一个表面接合金属板23来形成。在本实施方式中，金属层13通过将包括纯度为99.99mass％以上的铝(所谓的4N铝)的轧制板的铝板接合于陶瓷基板11来形成。在此，金属层13(金属板23)的厚度设定在0.2mm以上且3.0mm以下的范围内，在本实施方式中设定为1.6mm。
Ag基底层30例如设为包含玻璃成分的含玻璃的Ag浆料的烧成物。该Ag基底层30在接合半导体元件3之前的状态下，如图2及图3所示，具备形成于电路层12侧的玻璃层31和形成于该玻璃层31上的Ag层32。
玻璃层31内部分散有粒径为几纳米左右的微细的导电性粒子33。该导电性粒子33设为含有至少一个Ag或Al的结晶性粒子。另外，玻璃层31内的导电性粒子33通过使用例如透射电子显微镜(TEM)来观察。导电性粒子33被推测为在烧成时析出于玻璃层31内部。
并且，Ag层32的内部分散有粒径为几纳米左右的微细的玻璃粒子(省略图示)。
另外，认为玻璃层31及Ag层32是通过对含玻璃的Ag浆料进行烧结时，软化而具有流动性的玻璃因Ag的粒子成长移动至与电路层12的界面附近来形成。
并且，在本实施方式中，电路层12由纯度为99.99mass％以上的铝构成，因此电路层12的表面形成有在大气中自然产生的铝氧化皮膜12A。在此，形成有前述的Ag基底层30的部分中，去除该铝氧化皮膜12A，在电路层12上直接形成有Ag基底层30。即，如图3所示，构成电路层12的铝与玻璃层31直接接合。铝氧化皮膜12A通过与含玻璃的Ag浆料中的玻璃进行反应来去除。氧化皮膜作为铝氧化物溶解于玻璃中。一部分与Bi2O3和ZnO等玻璃成分一同作为复合氧化物晶体来析出。
如图3所示，在本实施方式中，在电路层12上自然产生的铝氧化皮膜12A的厚度to设为4nm≤to≤6nm。并且，构成为玻璃层31的厚度tg成为0.01μm≤tg≤5μm，后述的喷砂处理前的Ag层32的厚度ta成为1μm≤ta≤100μm，整个Ag基底层30的厚度t1成为1.01μm≤t1≤105μm。
这种结构的Ag基底层30中，使用拉曼光谱测量装置从Ag层32的与玻璃层31相反侧的表面30A射入入射光(光源光)，通过拉曼光谱法得到的拉曼光谱中，将3000cm-1至4000cm-1的波数范围中的强度最高值设为IA，将450cm-1至550cm-1的波数范围中的强度最高值设为IB时，IA/IB为1.1以上。该IA/IB优选为1.2以上，更优选为1.5以上。IA/IB越大越优选，但是极度增大IA/IB会导致成本的增加。为此，IA/IB可优选为1.9以下。
若对Ag基底层30射入例如单波长的入射光，则与构成Ag基底层30的分子产生碰撞而其中一部分被散射。该散射光的成分中其大部分为与入射光相同波数的瑞利散射光，但是一部分为与入射光不同的波数区域的光即拉曼散射光。入射光与拉曼散射光的能隙反映了Ag基底层30的分子结构。
构成Ag基底层30的Ag单体，不会通过拉曼光谱显现特定的波数峰值，因此认为通过拉曼光谱产生的Ag基底层30的特定的波数峰值是通过Ag基底层30中所含的氧化物而产生。拉曼光谱按照Ag基底层30中所含的Ag的量而发生变化。例如，以波数3500cm-1为中心的波数3000cm-1～4000cm-1的范围中，拉曼光谱发生变化而产生波数峰值。这种波数区域中的波数峰值中，Ag离子化而成为Ag+。因此以波数3500cm-1为中心的波数3000cm-1～4000cm-1的范围中的波数峰值与作为载波的离子的迁移率有关，波数峰值的强度越高表示Ag基底层30的导电性越高。
作为一例，图9中示出如下测量例：使用含有5wt％的玻璃成分的Ag基底层30，从Ag层32的表面30A射入入射光，通过拉曼光谱法得到的拉曼光谱的测量例。根据该图9所示的测量结果的一例，可观察以波数3500cm-1为中心的峰值。即，将3000cm-1至4000cm-1的波数范围中的强度最高值设为IA，将450cm-1至550cm-1的波数范围中的强度最高值设为IB时，IA/IB为1.1以上，则构成Ag基底层30的Ag离子化而成为Ag+，表示Ag基底层30的导电性较高。另外，图9中的(A)的光谱表示IA/IB为1.1以上的例，(B)的光谱表示IA/IB小于1.1的例。
在本实施方式中，Ag基底层30的表面(图3中上表面)30A设为提高导电性处理面。即，在Ag层32的与玻璃层31相反侧的表面通过进行提高导电性处理来促进Ag的离子化而成为Ag+，并提高Ag基底层30的导电性。通过进行这种提高导电性处理，可使通过上述的拉曼光谱法得到的拉曼光谱的IA/IB成为1.1以上。
作为提高导电性处理的具体例的一种可举出喷砂处理。即，在本实施方式中，提高导电性处理面为喷砂面30A。该喷砂面30A中，通过使喷砂磨粒与Ag层32碰撞而形成，具备与喷砂磨粒相应的形状的凹凸。
喷砂面30A中的表面粗糙度Ra设为0.35μm以上且1.50μm以下即可。若表面粗糙度Ra小于0.35μm，则有可能喷砂处理不充分而使电阻不下降。若表面粗糙度Ra超过1.50μm，则喷砂面30A变得过粗，通过焊料等接合半导体元件时，有可能产生空隙，使热阻力上升。表面粗糙度Ra更优选为0.40μm以上且1.0μm以下，但并不限于此。
通过形成该喷砂面30A的喷砂处理，压力负载于Ag层32而破坏Ag层32内部的气孔。并且，形成Ag层32的一部分与电路层12直接接触的部位。
作为提高导电性处理的一例，若在Ag层32的与玻璃层31相反侧的表面进行喷砂处理，则例如作为Ag基底层30的玻璃成分使用Bi2O3-ZnO-B2O3类玻璃时，B-O-B的交联结构变为非交联结构B-O-，并且，Ag变为Ag+。通过这种喷砂处理等提高导电性处理，Ag基底层30的厚度方向的电阻值P例如能够设为10mΩ以下。Ag基底层30的厚度方向的电阻值P优选为5mΩ以下，更优选为1mΩ以下，但并不限于此。Ag基底层30的厚度方向的电阻值P越小越优选，但是极度降低电阻值P会导致成本的增加。为此，Ag基底层30的厚度方向的电阻值P可以是0.4mΩ以上。
在此，在本实施方式中，Ag基底层30的厚度方向上的电阻值设为Ag基底层30的上表面与电路层12的上表面之间的电阻值。这是因为构成电路层12的4N铝的电阻与Ag基底层30的厚度方向的电阻相比非常小。另外，如图6及图7所示，测量该电阻时，测量Ag基底层30的上表面中央点与电路层12上的点之间的电阻，所述电路层12上的点是，从Ag基底层30端部远离与从Ag基底层30的所述上表面中央点至Ag基底层30端部为止的距离相同的距离量的点。
并且，作为本实施方式的功率模块1中，半导体元件3与Ag基底层30之间设置有接合层2。作为接合层2，例如可举出焊料层。作为形成焊料层的焊材例如可举出Sn-Ag类、Sn-In类、或者Sn-Ag-Cu类。
散热片41用于冷却前述的具有Ag基底层的功率模块用基板10，具备用于流通冷却介质(例如冷却水)的流路42。在本实施方式中，散热片41设为包括铝或铝合金的多孔管。在本实施方式中，金属层13与散热片41例如通过Al-Si等钎料来接合。
接着，对能够用于形成Ag基底层30的含玻璃的Ag浆料进行说明。
该含玻璃的Ag浆料含有Ag粉末、玻璃粉末、树脂、溶剂及分散剂，包括Ag粉末和玻璃粉末的粉末成分的含量设为含玻璃的Ag浆料整体的60质量％以上且90质量％以下，余量设为树脂、溶剂及分散剂。
另外，在本实施方式中，包括Ag粉末和玻璃粉末的粉末成分的含量设为含玻璃的Ag浆料整体的85质量％。
并且，该含玻璃的Ag浆料的粘度调节为10Pa·s以上且500Pa·s以下，更优选调节为50Pa·s以上且300Pa·s以下。
Ag粉末的粒径设为0.05μm以上且1.0μm以下，在本实施方式中使用平均粒径为0.8μm的粉末。
玻璃粉末例如含有氧化铅、氧化锌、氧化硅、氧化硼、氧化磷及氧化铋中的任意一种或两种以上，其软化温度设为600℃以下。在本实施方式中使用包括氧化铅、氧化锌及氧化硼，平均粒径为0.5μm的玻璃粉末。
并且，Ag粉末的重量A与玻璃粉末的重量G的重量比A/G调节在80/20至99/1的范围内，在本实施方式中设为A/G＝80/5。
溶剂适合沸点为200℃以上的溶剂，在本实施方式中使用二乙二醇二丁醚。
树脂为调节含玻璃的Ag浆料的粘度的树脂，适合在500℃以上可分解的树脂。在本实施方式中使用乙基纤维素。
并且，在本实施方式中添加有二羧酸类的分散剂。另外，也可不添加分散剂而构成含玻璃的Ag浆料。
该含玻璃的Ag浆料通过如下来制作：将混合有Ag粉末和玻璃粉末的混合粉末与混合有溶剂和树脂的有机混合物通过搅拌机与分散剂一同预混，并通过辊磨机将得到的预混物捏合的同时混合，之后通过浆料过滤机过滤所获得的混匀物。
接着，参考图4及图5，对本发明的具有Ag基底层的功率模块用基板10的制造方法的一例进行说明。
首先，准备成为电路层12的金属板22及成为金属层13的金属板23，将这些金属板22、23分别通过钎料26层压于陶瓷基板11的一个表面及另一个表面，并进行加压、加热后冷却，由此接合金属板22、23与陶瓷基板11(电路层及金属层形成工序S01)。
另外，该电路层及金属层形成工序S01中，作为钎料26使用Al-7.5mass％Si钎料箔，将钎焊温度设定为640℃～650℃。
接着，在电路层12的一个表面形成Ag基底层30(Ag基底层形成工序S02)。
在该Ag基底层形成工序S02中，首先，在电路层12的一个表面涂布含玻璃的Ag浆料(涂布工序S21)。另外，涂布含玻璃的Ag浆料时能够采用网版印刷法、胶版印刷法、感光性工艺等各种方法。在本实施方式中通过网版印刷法将含玻璃的Ag浆料形成为图案状。
在电路层12的一个表面涂布含玻璃的Ag浆料的状态下，装入加热炉内进行含玻璃的Ag浆料的烧成(烧成工序S22)。另外，此时的烧成温度例如设定为350℃～645℃。
通过该烧成工序S22，形成有具备玻璃层31和Ag层32的Ag基底层30。此时，通过玻璃层31在电路层12的表面自然产生的铝氧化皮膜12A被熔化去除，在电路层12上直接形成玻璃层31。并且，玻璃层31的内部分散有粒径为几纳米左右的微细的导电性粒子33。该导电性粒子33设为含有至少一个Ag或Al的结晶性粒子，推测为烧成时析出于玻璃层31内部。
接着，对Ag基底层30(Ag层32)中与电路层12相反侧的表面进行提高导电性处理、例如喷砂处理，并设为喷砂面30A(喷砂处理工序S23)。
在该喷砂处理工序S23中，作为喷砂粒能够使用新莫氏硬度2～7的二氧化硅等玻璃粒子、陶瓷粒子、金属粒子或者树脂制珠等。在本实施方式中使用玻璃粒子。并且，喷砂粒的粒径设为20μm以上且150μm以下的范围内。
并且，喷砂压力设为0.05MPa以上且0.8MPa以下的范围内，将加工时间设为1秒以上且10秒以下的范围内。
如此，若对Ag基底层30进行喷砂处理(提高导电性处理)，则形成如下Ag基底层30，即，使用拉曼光谱测量装置，从Ag层32的与玻璃层31相反侧的表面30A射入入射光(光源光)，通过拉曼光谱法得到的拉曼光谱的3000cm-1至4000cm-1的波数范围中的强度最高值设为IA，450cm-1至550cm-1的波数范围中的强度最高值设为IB时，IA/IB为1.1以上，Ag离子化而提高导电性的Ag基底层30。
如以上制造作为本实施方式的具有Ag基底层的功率模块用基板10。
接着，在金属层13的另一个表面侧通过钎料层压散热片41，加压、加热后进行冷却，由此接合散热片41和金属层13(散热片接合工序S03)。
另外，在该散热片接合工序S03中，作为钎料，使用Al-10mass％Si钎料箔，将钎焊温度设定为590℃～610℃。
并且，在Ag基底层30的喷砂面30A通过焊材载置IGBT等功率半导体元件和LED等发光元件等半导体元件3，在还原炉内进行焊料接合(半导体元件接合工序S04)。
此时，在通过焊材形成的接合层2中，构成Ag基底层30的Ag层32的一部分或全部熔化。
由此，制造出半导体元件3通过接合层2接合于电路层12上的功率模块1。
根据如以上构成的本实施方式所涉及的功率模块1及具有Ag基底层的功率模块用基板10，在电路层12的一个表面形成有包括玻璃层31和层压形成于该玻璃层31的Ag层32的Ag基底层30，在该Ag基底层30中与电路层12相反侧的表面进行提高导电性处理、例如喷砂处理而形成喷砂面30A，因此促进Ag的离子化而成为Ag+，提高Ag基底层30的导电性。实施提高导电性处理的Ag基底层30中，从Ag层32的与玻璃层31相反侧的表面30A射入入射光(光源光)，通过拉曼光谱法得到的拉曼光谱的3000cm-1至4000cm-1的波数范围中的强度最高值设为IA，450cm-1至550cm-1的波数范围中的强度最高值设为IB时，显示IA/IB为1.1以上的特性。
并且，在形成该喷砂面30A的喷砂处理工序S03中，能够对Ag层32施加压力，并破坏Ag层32内部的气孔，而且在Ag层32的局部形成与电路层12直接接触的部分，可大幅降低Ag基底层30中的电阻值。
在此，在本实施方式中，喷砂处理工序S03中，作为喷砂磨粒使用新莫氏硬度为2以上且7以下的范围的玻璃粒子，因此通过喷砂处理来未去除Ag层32，而是能够对Ag层32提供可靠的压力，可大幅降低Ag基底层30中的电阻值。
并且，Ag基底层30的厚度方向上的电阻值设为10mΩ以下，因此确保该Ag基底层30中的导电性，在Ag基底层30通过接合层2接合半导体元件3，由此能够得到导电损耗较少的功率模块1。
以上，对本发明的实施方式进行了说明，但是本发明并不限定于此，在不脱离该发明的技术思想的范围内可进行适当变更。
例如，在本实施方式中，作为提高导电性处理，在Ag层32的与玻璃层31相反侧的表面30A进行喷砂处理，但是除了喷砂处理以外，只要是促进Ag基底层30的Ag的离子化来提高导电性的处理即可，对特定的处理方法并无限定。
并且，在本实施方式中，将构成电路层及金属层的金属板设为纯度为99.99mass％的纯铝(4N铝)的轧制板来进行了说明，但并不限定于此，也可由其他铝或铝合金构成。并且，将构成电路层及金属层的金属板也可由铜或铜合金构成。另外，也可以为固相扩散接合铜板和铝板的结构。
并且，通过钎焊而接合铝板和陶瓷基板进行了说明，但并不限定于此，可适用瞬间液相连接法(Transient Liquid Phase Bonding)、铸造法等。
另外，将构成电路层及金属层的金属板由铜或铜合金构成的情况下，将包括铜或铜合金的金属板接合于陶瓷基板时，能够适用直接接合法(DBC法)、活性金属钎焊法、铸造法等。
并且，作为绝缘层使用包括AlN的陶瓷基板进行了说明，但并不限定于此，可使用包括Si3N4或Al2O3等的陶瓷基板，也可由绝缘树脂构成绝缘层。
另外，在本实施方式中，在Ag基底层上通过焊材接合半导体元件来进行了说明，但并不限定于此，也可使用氧化银浆料、包含银粒子的浆料、包含Ag粉末的导电性粘合剂等在Ag基底层上接合半导体元件。此时，成为Ag彼此接合，因此能够提高半导体元件与Ag基底层的接合可靠性。
另外，作为氧化银浆料能够使用含有氧化银粉末、还原剂、树脂、溶剂、有机金属化合物粉末的浆料。优选氧化银粉末的含量设为氧化银浆料整体的60质量％以上且80质量％以下、还原剂的含量设为氧化银浆料整体的5质量％以上且15质量％以下、有机金属化合物粉末的含量设为氧化银浆料整体的0质量％以上且10质量％以下、余量设为溶剂。其中，为了抑制烧结后残留未反应的有机物，优选在氧化银浆料中不添加分散剂或树脂。
并且，散热片并不限定于本实施方式中的例示，散热片的结构并不特别限定。
另外，可在散热片与金属层之间设置缓冲层。作为缓冲层能够使用包括铝或铝合金或者包含铝的复合材(例如AlSiC等)的板材。
实施例
对为了确认本发明的有效性而进行的确认实验进行说明。
在陶瓷基板的一个表面接合金属板来形成电路层。在此，陶瓷基板设为AlN，尺寸设为27mm×17mm×0.6mm。成为电路层的金属板设为表1所示的材质，尺寸设为25mm×15mm×0.3mm。
另外，金属板为铝板的情况下，作为接合材使用Al-Si类钎料。并且，金属板为铜板的情况下，作为接合材使用活性金属钎料(Ag-Cu-Ti钎料)。
在电路层的表面涂布实施方式中说明的含玻璃的Ag浆料并进行加热处理，由此形成Ag基底层。
另外，作为含玻璃的Ag浆料的玻璃粉末使用包含90.6质量％的Bi2O3、2.6质量％的ZnO、6.8质量％的B2O3的无铅玻璃粉末。并且，作为树脂使用乙基纤维素，作为溶剂使用二乙二醇二丁醚。另外，添加二羧酸类的分散剂。
在此，调节含玻璃的Ag浆料中的Ag粉末的重量A与玻璃粉末的重量G的重量比A/G及涂布量，如表1所示那样调节玻璃层与Ag层的厚度。
并且，作为提高导电性处理，对烧成的Ag基底层在表1所示的条件下实施喷砂处理来形成喷砂面。将所形成的喷砂面的观察结果示于图8。在此，图8的(a)是喷砂处理前的Ag基底层，图8的(b)是在本发明例7的条件下进行喷砂处理的Ag基底层，图8的(c)是在本发明例1的条件下进行喷砂处理的Ag基底层。
另外，比较例1～3中未实施喷砂处理。
关于得到的本发明例1～12及比较例1～3的具有Ag基底层的功率模块用基板，通过图6及图7中记载的方法，使用测试仪(KEITHLEY公司制：2010MULTIMETER)，测量Ag基底层的厚度方向的电阻值。电阻的测量是在Ag基底层的上表面中央点与电路层上的点之间进行的，所述电路层上的点是指，将从Ag基底层的上表面中央点至Ag基底层端部为止的距离设为H的情况下，从Ag基底层端部远离H量的点。
并且，测量喷砂处理后的Ag基底层表面(喷砂面)的表面粗糙度Ra。测量时使用激光显微镜VK-X200(KEYENCE公司制及装置附属软件的VK-Analyzer)，接物镜倍率设为20倍，测量三个视场，将其平均值设为表面粗糙度Ra。另外，未实施喷砂处理的比较例1～3中，未进行表面粗糙度Ra的测量。
并且，使用显微激光拉曼光谱分析装置(HORIBA,Ltd.制：型号XploRA)，将入射光(光源光)的波长设为532nm，测量本发明例1～12及比较例1～3的Ag基底层的拉曼光谱。并且，从得到的拉曼光谱的3000cm-1至4000cm-1的波数范围中的强度最高值(IA)及450cm-1至550cm-1的波数范围中的强度最高值(IB)计算出IA/IB。另外，测量部位设为Ag基底层上的玻璃区域，积算次数设为3次。
将以上的各评价结果示于表1。
[表1]
※4N铝：纯度为99.99mass％以上的铝
※IA：拉曼光谱中，3000cm-1至4000cm-1的波数范围中的强度最高值
※IB：拉曼光谱中，450cm-1至550cm-1的波数范围中的强度最高值
在Ag基底层进行喷砂处理来形成喷砂面的本发明例1～12中，相对于具有相同的厚度的玻璃层及Ag层的比较例1～3，电阻值变低。
本发明例1～12中，拉曼光谱的3000cm-1至4000cm-1的波数范围中的强度最高值设为IA，450cm-1至550cm-1的波数范围中的强度的最高值设为IB时，IA/IB为1.1以上。另一方面，比较例1～3中，IA/IB小于1.0。
从以上可确认，根据本发明，能够提供一种具备电阻较低的Ag基底层的具有Ag基底层的功率模块用基板。
产业上的可利用性
根据本发明的功率模块，即使在Ag基底层具有玻璃层也能够大幅降低Ag基底层中的电阻值。因此，本发明的功率模块适合为了控制风力发电、电动车、混合动力汽车等而使用的大功率控制用功率半导体元件中。
符号说明
1-功率模块，10-具有Ag基底层的功率模块用基板，11-陶瓷基板(绝缘层)，12-电路层，30-Ag基底层，30A-喷砂面(提高导电性处理面)，31-玻璃层，32-Ag层。

Claims (5)

1.一种具有Ag基底层的功率模块用基板，其具备：
电路层，形成于绝缘层的一个表面；及
Ag基底层，形成于所述电路层，
所述具有Ag基底层的功率模块用基板的特征在于，
所述Ag基底层包括形成于所述电路层侧的玻璃层和层压形成于该玻璃层的Ag层，
所述Ag基底层中，从所述Ag层的与所述玻璃层相反侧的表面射入入射光，通过拉曼光谱法得到的拉曼光谱中，将3000cm-1至4000cm-1的波数范围中的强度最高值设为IA，将450cm-1至550cm-1的波数范围中的强度最高值设为IB时，IA/IB为1.1以上。
2.根据权利要求1所述的具有Ag基底层的功率模块用基板，其中，
所述Ag基底层在其厚度方向上的电阻值为10mΩ以下。
3.根据权利要求1或2所述的具有Ag基底层的功率模块用基板，其中，
所述Ag基底层为含玻璃的Ag浆料的烧成物。
4.根据权利要求1至3中任一项所述的具有Ag基底层的功率模块用基板，其中，
所述Ag基底层中与所述玻璃层相反侧的表面为进行了提高导电性处理的表面。
5.一种功率模块，其具备：
根据权利要求1至4中任一项所述的具有Ag基底层的功率模块用基板；及
半导体元件，
所述半导体元件通过接合层接合于所述Ag基底层。
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JP2017135374A (ja) * 2016-01-22 2017-08-03 三菱マテリアル株式会社 接合体、パワーモジュール用基板、パワーモジュール、接合体の製造方法及びパワーモジュール用基板の製造方法
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102347426A (zh) * 2010-07-26 2012-02-08 旭硝子株式会社 发光元件搭载用基板、其制造方法及发光装置
JP2014179564A (ja) * 2013-03-15 2014-09-25 Mitsubishi Materials Corp パワーモジュール用基板の製造方法及びパワーモジュールの製造方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3922166B2 (ja) 2002-11-20 2007-05-30 三菱マテリアル株式会社 パワーモジュール用基板の製造方法並びにパワーモジュール用基板及びパワーモジュール
JP2006202938A (ja) 2005-01-20 2006-08-03 Kojiro Kobayashi 半導体装置及びその製造方法
JP4737116B2 (ja) 2007-02-28 2011-07-27 株式会社日立製作所 接合方法
US8513534B2 (en) 2008-03-31 2013-08-20 Hitachi, Ltd. Semiconductor device and bonding material
JP5180307B2 (ja) * 2008-08-08 2013-04-10 京セミ株式会社 採光型太陽電池モジュール
JP5212298B2 (ja) 2009-05-15 2013-06-19 三菱マテリアル株式会社 パワーモジュール用基板、冷却器付パワーモジュール用基板、パワーモジュール及びパワーモジュール用基板の製造方法
DE102009029577B3 (de) * 2009-09-18 2011-04-28 Infineon Technologies Ag Verfahren zur Herstellung eines hochtemperaturfesten Leistungshalbleitermoduls
JP5720454B2 (ja) 2010-07-26 2015-05-20 旭硝子株式会社 発光素子搭載用基板とその製造方法および発光装置
JP5707886B2 (ja) 2010-11-15 2015-04-30 三菱マテリアル株式会社 パワーモジュール用基板、冷却器付パワーモジュール用基板、パワーモジュールおよびパワーモジュール用基板の製造方法
JP5966379B2 (ja) 2011-05-31 2016-08-10 三菱マテリアル株式会社 パワーモジュール、及び、パワーモジュールの製造方法
JP5664625B2 (ja) * 2012-10-09 2015-02-04 三菱マテリアル株式会社 半導体装置、セラミックス回路基板及び半導体装置の製造方法
JP6085968B2 (ja) * 2012-12-27 2017-03-01 三菱マテリアル株式会社 金属部材付パワーモジュール用基板、金属部材付パワーモジュール、及び金属部材付パワーモジュール用基板の製造方法
TWI642154B (zh) * 2013-12-25 2018-11-21 日商三菱綜合材料股份有限公司 電源模組用基板及其製造方法、電源模組

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102347426A (zh) * 2010-07-26 2012-02-08 旭硝子株式会社 发光元件搭载用基板、其制造方法及发光装置
JP2014179564A (ja) * 2013-03-15 2014-09-25 Mitsubishi Materials Corp パワーモジュール用基板の製造方法及びパワーモジュールの製造方法

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