CN109075081A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN109075081A
CN109075081A CN201780021547.1A CN201780021547A CN109075081A CN 109075081 A CN109075081 A CN 109075081A CN 201780021547 A CN201780021547 A CN 201780021547A CN 109075081 A CN109075081 A CN 109075081A
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Prior art keywords
layer
circuit layer
semiconductor element
semiconductor device
semiconductor
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CN201780021547.1A
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CN109075081B (zh
Inventor
西元修司
长友义幸
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Mitsubishi Materials Corp
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Mitsubishi Materials Corp
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Abstract

本发明的半导体装置具备：电路层，由导电性材料构成；半导体元件，搭载在电路层的一面；和陶瓷基板，配设在电路层的另一面，在电路层的一面形成有Ag基底层，该Ag基底层具有玻璃层和层压在该玻璃层上的Ag层，该Ag基底层的Ag层和半导体元件直接接合。

Description

半导体装置
技术领域
本发明涉及一种具备由导电性材料构成的电路层和搭载在该电路层上的半导体元件的半导体装置。
本申请基于2016年2月29日在日本申请的专利申请2016-037085号要求优先权，并且在此援引其内容。
背景技术
LED或功率模块等的半导体装置具备在由导电材料构成的电路层上接合有半导体元件的结构。
为了控制风力发电、电动汽车或混合动力汽车等而使用的大功率控制用功率半导体元件由于发热量较多，因此作为搭载该功率半导体元件的基板，一直以来广泛使用陶瓷电路基板(功率模块用基板)，该陶瓷电路基板具备：绝缘层，由例如AlN(氮化铝)或Al2O3(氧化铝)等的陶瓷基板构成；和电路层，通过在该绝缘层的一面配设导电性优异的金属而形成。
例如，专利文献1所示的功率模块(半导体装置)具有如下结构：具备在陶瓷基板的一面上形成有由Al或Cu等的金属构成的电路层的功率模块用基板(陶瓷电路基板)和接合在该电路层上的半导体元件。并且，该功率模块构成为在功率模块用基板的另一侧接合有散热板，将由半导体元件发生的热传递到功率模块用基板侧，并且通过散热板将该热扩散至外部。
在将半导体元件等的电子部件接合在电路层上时，例如如专利文献1所示，广泛使用利用焊锡材的方法。近年来，从环保观点来看，例如Sn-Ag类、Sn-In类或Sn-Ag-Cu类等的无铅焊材成为主流。
在此，由铝或铝合金构成的电路层，由于在表面上形成铝的自然氧化膜，因此难以利用焊锡材良好地进行电路层与半导体元件的接合。
另外，由铜或铜合金构成的电路层，由于已熔化的焊锡材与铜反应而焊锡材的成分侵入电路层的内部，从而电路层的特性有可能会变差。
为此，如专利文献1所述，以往在电路层的表面上形成Ni镀膜之后，利用焊锡材来接合半导体元件。
另一方面，作为未使用焊锡材的接合方法，例如在专利文献2中提出了使用纳米Ag膏来接合半导体元件的技术。
另外，例如在专利文献3、4中提出了使用包含金属氧化物粒子和由有机物构成的还原剂的氧化物膏来接合半导体元件的技术。
另外，例如在专利文献5～7中提出了使用含玻璃Ag膏在由铝或铜构成的电路层上形成Ag基底层之后，通过焊锡或Ag膏来接合电路层和半导体元件的技术。在该技术中，通过在由铝或铜构成的电路层的表面上涂布含玻璃Ag膏并进行烧成，从而使形成于电路层的表面上的氧化被膜与玻璃反应而去除该氧化被膜以形成Ag基底层，并且在形成有该Ag基底层的电路层上通过焊锡或由Ag膏的烧成体构成的Ag接合层来接合半导体元件。
在此，Ag基底层具备：玻璃层，通过玻璃与电路层的氧化被膜反应而形成；和Ag层，形成在该玻璃层上。在该玻璃层中分散有导电性粒子，通过该导电性粒子来确保玻璃层的导电性。
专利文献1：日本专利公开2004-172378号公报
专利文献2：日本专利公开2006-202938号公报
专利文献3：日本专利公开2008-208442号公报
专利文献4：日本专利公开2009-267374号公报
专利文献5：日本专利公开2010-287869号公报
专利文献6：日本专利公开2012-109315号公报
专利文献7：日本专利公开2013-012706号公报
但是，如专利文献1及专利文献5、6所记载的那样，在利用焊锡材来接合半导体元件和电路层的情况下，高温环境下使用焊锡材时一部分焊锡熔化，从而有可能会降低半导体元件与电路层的接合可靠性。
特别是，最近期待从硅半导体到SiC或GaN等化合物半导体元件的实用化，希望提高半导体自身的耐热性，因此有半导体装置的使用温度变高的趋势，变得难以如以往那样利用由焊锡材接合而成的结构来进行应对。
另外，如专利文献2～4及专利文献7所记载的那样，在作为接合材使用金属膏及金属氧化物膏，并且通过由金属膏及金属氧化物膏的烧成体构成的接合层来接合半导体元件的情况下，例如在200℃以上的高温保持时，或者例如在施加达到200℃以上的高温的冷热循环负载时，在接合层中进行金属的烧结，从而Ag结晶(金属结晶)发生粒生长，形成局部稀疏部分和局部致密部分，有可能在接合层上生成空隙而降低接合性。
发明内容
本发明是鉴于前述情况而提出的，其目的是提供一种半导体装置，即使在较高温环境下使用该半导体装置的情况下，电路层与半导体的接合可靠性也优异，能够稳定地使用该半导体装置。
为了解决这种问题并实现上述目的，作为本发明的一方式的半导体装置具备：电路层，由导电性材料构成；半导体元件，搭载在所述电路层的一面；以及陶瓷基板，配设在所述电路层的另一面，所述半导体装置的特征在于，在所述电路层的一面形成有Ag基底层，所述Ag基底层具有玻璃层和层压在该玻璃层上的Ag层，该Ag基底层的所述Ag层和所述半导体元件直接接合。
根据该结构的半导体装置，在电路层的一面形成有Ag基底层，该Ag基底层具有玻璃层和层压在该玻璃层上的Ag层，该Ag基底层和半导体元件直接接合，因此不会存在焊锡材或由金属膏构成的接合材，即使在高温环境下使用该半导体装置的情况下，也不会在电路层与半导体之间发生熔化，或者不会因烧结的进行而生成空隙，能够切实地接合电路层和半导体元件。因此，作为本发明的一方式的半导体装置即使在高温环境下也能够稳定地使用。
在此，在作为本发明的一方式的半导体装置中，优选在所述半导体元件的与所述Ag层接合的面形成有由Au或Au合金构成的Au膜及由Ag或Ag合金构成的Ag膜中的任一种。
在所述半导体元件的与所述Ag层接合的面形成有Ag膜的情况下，Ag基底层(Ag层)和半导体元件(Ag膜)成为相同种类的金属彼此的接合，能够良好地接合电路层和半导体元件。在所述半导体元件的与所述Ag层接合的面使用Au膜的情况下，能够在较低温下进行半导体元件(Au膜)和Ag基底层(Ag层)的固相扩散接合。
另外，在作为本发明的一方式的半导体装置中，所述半导体元件也可以是功率半导体元件。
根据该结构的半导体装置，即使在使用发热量多的功率半导体元件的情况下，也能够有效地向电路层传递热。此外，作为功率半导体，可列举IGBT(Insulated GateBipolar Transistor，绝缘栅双极型晶体管)或MOSFET(金属-氧化物半导体场效应晶体管)等。
根据本发明，提供一种半导体装置，即使为在较高温环境下使用该半导体装置的情况，电路层与半导体元件的接合可靠性也优异，能够稳定地使用该半导体装置。
附图说明
图1是作为本发明的一实施方式的半导体装置(功率模块)的概略说明图。
图2是图1所示的半导体装置(功率模块)的电路层与半导体元件的接合界面的放大说明图。
图3是表示Ag基底层与电路层的接合部分的主要部分放大剖面图。
图4是表示图1所示的半导体装置(功率模块)的制造方法的流程图。
图5是图1所示的半导体装置(功率模块)的制造方法的概略说明图。
图6是作为本发明的另一实施方式的半导体装置的(LED装置)的概略说明图。
具体实施方式
下面，参照附图对本发明的实施方式进行说明。此外，作为本实施方式的半导体装置为搭载有为了控制风力发电或电动汽车等电动车辆等而使用的大功率控制用功率半导体元件的功率模块。图1示出作为本发明的实施方式的功率模块(半导体装置)。
该功率模块1具备：功率模块用基板(陶瓷电路基板)10，配设有电路层12；半导体元件3，接合在电路层12的一面(在图1中为上表面)；和冷却器50，配设在功率模块用基板10的另一侧。
如图1所示，功率模块用基板10具备：陶瓷基板11，用于构成绝缘层；电路层12，配设在该陶瓷基板11的一面(在图1中为上表面)；和金属层13，配设在陶瓷基板11的另一面(在图1中为下表面)。
陶瓷基板11用于防止电路层12与金属层13之间的电连接，该陶瓷基板11由绝缘性高的AlN(氮化铝)、Si3N4(氮化硅)或Al2O3(氧化铝)等构成。在本实施方式中，陶瓷基板11由散热性优异的AlN(氮化铝)构成。另外，陶瓷基板11的厚度被设定在0.2～1.5mm的范围内，在本实施方式中，陶瓷基板11的厚度被设定为0.635mm。
电路层12通过在陶瓷基板11的一面接合具有导电性的铝或铝合金、铜或铜合金等的金属板而形成。在本实施方式中，电路层12通过接合纯度为99.99质量％以上的铝(所谓4N铝)的轧制板而形成。此外，电路层12的厚度被设定在0.1mm以上且1.0mm以下的范围内，在本实施方式中，电路层12的厚度被设定为0.6mm。另外，在该电路层12上形成有电路图案，该电路层12的一面(在图1中为上表面)为接合半导体元件3的接合面。
金属层13通过在陶瓷基板11的另一面接合铝或铝合金、铜或铜合金等的金属板而形成。在本实施方式中，该金属板(金属层13)为纯度99.99质量％以上的铝(所谓4N铝)的轧制板。在此，金属层13的厚度被设定在0.2mm以上且3.0mm以下的范围内，在本实施方式中，金属层13的厚度被设定为1.6mm。
冷却器50用于冷却前述的功率模块用基板10，在本实施方式中，冷却器50具备用于供冷却介质(例如，冷却水)流通的流路51。该冷却器50优选由传热性良好的材质构成，在本实施方式中，该冷却器50由A6063(铝合金)构成。
半导体元件3由Si、SiC、GaN等的半导体材料构成，在半导体元件3与电路层12接合的面上，作为表面处理膜3a形成有由Au或Au合金构成的Au膜及由Ag或Ag合金构成的Ag膜。在本实施方式中，表面处理膜3a为Ag膜。
在此，在本实施方式中，利用溅射法等以20nm～300nm的厚度进行表面处理膜3a的成膜。表面处理膜3a的厚度优选为50nm～200nm，但并不限定于此。
并且，在图1所示的功率模块1中，如图2所示，在电路层12的表面形成有Ag基底层30。此外，如图1所示，Ag基底层30未形成在电路层12的整个表面上，而是形成在待配设半导体元件3的部分，即，选择性地形成在仅与半导体元件3接合的面。
在此，如后述，Ag基底层30为包含玻璃成分的含玻璃Ag膏的烧成体。如图3所示，在接合半导体元件3之前的状态下，该Ag基底层30具备形成于电路层12侧的玻璃层31和形成在该玻璃层31上的Ag层32。
在玻璃层31的内部分散有粒径为数纳米程度的微细的导电性粒子33。该导电性粒子33为含有Ag或Al中的至少一种的结晶性粒子。此外，例如利用透射型电子显微镜(TEM)来观察玻璃层31内的导电性粒子33。
另外，在Ag层32的内部分散有粒径为数纳米程度的微细的玻璃粒子(未图示)。
另外，在本实施方式中，电路层12由纯度为99.99质量％以上的铝构成，因此在电路层12的表面形成有在大气中自然发生的铝氧化被膜12A。在此，在形成有前述的Ag基底层30的部分去除该铝氧化被膜12A，并且在电路层12上直接形成有Ag基底层30。即，如图3所示，直接接合构成电路层12的铝和玻璃层31。
在本实施方式中，如图3所示，自然发生在电路层12上的铝氧化被膜12A的厚度to在4nm≤to≤6nm的范围内。另外，玻璃层31的厚度tg在0.01μm≤tg≤5μm的范围内，Ag层32的厚度ta在1μm≤ta≤100μm的范围内。
此外，该Ag基底层30在厚度方向上的电阻值P为0.5Ω以下。在此，在本实施方式中，Ag基底层30在厚度方向上的电阻值P为Ag基底层30的上表面与电路层12的上表面之间的电阻值。这是因为，构成电路层12的铝(4N铝)的电阻与Ag基底层30在厚度方向上的电阻相比非常小。此外，在测量该电阻时，测量Ag基底层30的上表面中央点和从Ag基底层30的端部隔开规定距离的点之间的电阻，其中，该规定距离与从Ag基底层30的所述上表面中央点至Ag基底层30的端部的距离相同。
接着，对形成Ag基底层30的含玻璃Ag膏进行说明。
该含玻璃Ag膏具有Ag粉末、玻璃粉末、树脂、溶剂和分散剂，由Ag粉末和玻璃粉末构成的粉末成分的含量为含玻璃Ag膏总体的60质量％以上且90质量％以下，余量为树脂、溶剂和分散剂。
此外，在本实施方式中，由Ag粉末和玻璃粉末构成的粉末成分的含量为含玻璃Ag膏总体的85质量％。
另外，该含玻璃Ag膏的粘度被调整在10Pa·s以上且500Pa·s以下，更优选为50Pa·s以上且300Pa·s以下。
Ag粉末的粒径为0.05μm以上且1.0μm以下，在本实施方式中，使用平均粒径为0.8μm的Ag粉末。
玻璃粉末例如含有氧化铅、氧化锌、氧化硅、氧化硼、氧化磷及氧化铋中的任一种或两种以上，该玻璃粉末的玻璃化转变温度为300℃以上且450℃以下，软化温度为600℃以下，结晶温度为450℃以上。
在本实施方式中，玻璃粉末以氧化铅、氧化锌和氧化硼为主成分，使用平均粒径为0.05μm的玻璃粉末。
另外，Ag粉末的重量A与玻璃粉末的重量G的重量比A/G被调整在80/20至90/1的范围内，在本实施方式中，A/G＝80/5。
溶剂适合沸点为200℃以上的溶剂，在本实施方式中，使用二乙二醇二丁醚。
树脂用于调整含玻璃Ag膏的粘度，适合能够在400℃以上时分解的树脂。在本实施方式中，使用乙基纤维素。
另外，在本实施方式中，添加二羧酸系的分散剂。此外，也可以在不添加分散剂的情况下构成含玻璃Ag膏。
该含玻璃Ag膏通过如下的方法来制备：即，将混合Ag粉末和玻璃粉末而成的混合粉末和混合溶剂和树脂而成的有机混合物与分散剂一同利用搅拌器进行预混合，利用辊磨机边混入所得到的预混合物边进行混合之后，利用膏过滤器过滤所得到的混匀物。
下面，参照图4及图5对作为本实施方式的功率模块1的制造方法进行说明。
首先，准备功率模块用基板10，该功率模块用基板10在陶瓷基板11的一面上形成有电路层12，并且在陶瓷基板的另一面上形成有金属层13，在该功率模块用基板10的电路层12上涂布含玻璃Ag膏40(含玻璃Ag膏涂布工序S01)。在此，当涂布含玻璃Ag膏40时，可采用网版印刷法、胶片印刷法或感光性工艺等各种手段。在本实施方式中，利用网版印刷法将含玻璃Ag膏40形成为图案状。
在电路层12的一面涂布有含玻璃Ag膏40的状态下，将其装入到加热炉61内进行加热处理，进行含玻璃Ag膏40的烧成(第一加热处理工序S02)。通过该第一加热处理工序S02，形成具备玻璃层31和Ag层32的Ag基底层30。
当在该第一加热处理工序S02中，进行含玻璃Ag膏40的烧成时，自然发生在电路层12的表面上的铝氧化被膜12A通过玻璃层31被熔化去除，在电路层12上直接形成玻璃层31。另外，在玻璃层31的内部分散有粒径为数纳米程度的微细的导电性粒子33。该导电性粒子33为含有Ag或Al中的至少一个的结晶性粒子，推测为在烧成时析出到玻璃层31内部的粒子。
此外，在Ag层32的内部分散有粒径为数微米程度的玻璃粒子。推测该玻璃粒子为在进行Ag粒子的烧结的过程中凝集残留的玻璃成分而成的粒子。
在本实施方式中，第一加热处理工序S02中的加热温度被设定在350℃以上且645℃以下的范围内，加热温度下的保持时间被设定在1分钟以上且60分钟以下的范围内。并且，通过在这种条件下进行加热处理，第一加热处理工序S02之后形成的Ag基底层30中的Ag层32的平均结晶粒径被调整在0.5μm以上且3.0μm以下的范围内。
在此，当第一加热处理工序S02中的加热温度小于350℃以及加热温度下的保持时间小于1分钟时，有可能烧成不够充分，无法充分形成Ag基底层30。另一方面，当第一加热处理工序S02中的加热温度大于645℃以及加热温度下的保持时间大于60分钟时，有可能烧成过度进行，第一加热处理工序S02之后形成的Ag基底层30中的Ag层32的平均结晶粒径未在0.5μm以上且3.0μm以下的范围内。
基于上述，在本实施方式中，第一加热处理工序S02中的加热温度被设定在350℃以上且645℃以下的范围内，加热温度下的保持时间被设定在1分钟以上且60分钟以下的范围内。
此外，为了切实地形成Ag基底层30，优选将第一加热处理工序S02中的加热温度的下限设为400℃以上，更优选设为450℃以上。另外，优选将加热温度下的保持时间的下限设为5分钟以上，更优选设为10分钟以上。
另一方面，为了切实地控制第一加热处理工序S02中的烧成的进行，优选将第一加热处理工序S02中的加热温度的上限设为600℃以下，更优选设为575℃以下。另外，优选将加热温度下的保持时间的上限设为45分钟以下，更优选设为30分钟以下。而且，通过在这种条件下进行加热处理，从而第一加热处理工序S02后的Ag基底层30中的Ag层32的平均结晶粒径被调整在0.5μm以上且3.0μm以下的范围内。
接着，如图5所示，在Ag基底层30的Ag层32上层压半导体元件3(半导体元件层压工序S03)。此时，以半导体元件3的表面处理膜3a朝向Ag基底层30侧的方式配置。
并且，如图5所示，在沿层压方向加压层压后的半导体元件3和功率模块10的状态下配置在加热炉62内进行加热处理，从而接合半导体元件3和功率模块用基板10(第二加热处理工序S04)。此时，进一步进行Ag基底层30的Ag层32的烧成，并且接合半导体元件3。即，在本实施方式中，通过进行第一加热处理工序S02和第二加热处理工序S04这两个步骤的加热工序，从而进行Ag基底层30的Ag层32的烧成。
在此，在第二加热处理工序S04中，层压方向的加压压力被设定在5MPa以上且40MPa以下的范围内，加热温度被设定在200℃以上且400℃以下的范围内，加热温度下的保持时间被设定在1分钟以上且60分钟以下的范围内。
此外，在第二加热处理工序S04之后，Ag层32的平均结晶粒径未发生变化。
这是因为，第二加热处理工序S04中的加热温度低于第一加热工序S02中的加热温度。
在此，当第二加热处理构成S04中的层压方向的加压压力小于5Mpa时，有可能半导体元件3与电路层12的接合强度不够充分。另一方面，当第二加热处理构成S04中的层压方向的加压压力大于40MPa时，有可能陶瓷基板11发生裂纹。
基于上述，在本实施方式中，将第二加热处理构成S04中的层压方向的加压压力设定在5MPa以上且40MPa以下的范围内。
此外，为了进一步提高半导体元件3与电路层12的接合强度，优选将第二加热处理构成S04中的层压方向的加压压力的下限设为10MPa以上。另外，为了切实地抑制陶瓷基板11发生裂纹，将第二加热处理构成S04中的层压方向的加压压力的上限设为35MPa以下。
另外，当第二加热处理工序S04中的加热温度小于200℃以及加热温度下的保持时间小于1分钟时，有可能半导体元件3与电路层12的接合强度不够充分。另一方面，当第二加热处理工序S04中的加热温度大于400℃以及加热温度下的保持时间大于60分钟时，有可能半导体元件3的特性因热而变差。
基于上述，在本实施方式中，第二加热处理工序S04中的加热温度被设定在200℃以上且400℃以下的范围内，加热温度下的保持时间被设定在1分钟以上且60分钟以下的范围内。优选第二加热处理工序S04中的加热温度被设定在250℃以上且350℃以下的范围内，并且加热温度下的保持时间被设定在2分钟以上且10分钟以下的范围内，但并不限定于此。
根据上述制造方法，可制造出形成在电路层12上的Ag基底层30的Ag层32和半导体元件3直接接合的本实施方式的功率模块1。
根据如上述结构的本实施方式所涉及的功率模块(半导体装置)1，在电路层12的一面形成有Ag基底层30，该Ag基底层30具有玻璃层31和层压在该玻璃层31上的Ag层32，并且该Ag基底层30的Ag层32和半导体元件3直接接合，因此即使在高温环境下使用的情况下，电路层12与半导体元件3的接合可靠性也优异。因此，即使在高温环境下也能够稳定地使用本实施方式所涉及的功率模块1。
另外，在本实施方式中，在半导体元件3中的与Ag基底层30接合的面上形成有由Ag膜构成的表面处理膜3a，因此Ag基底层30(Ag层32)和半导体元件3(表面处理膜3a)为相同种类的金属彼此的接合，能够良好地接合电路层12和半导体元件3。
此外，在本实施方式中，通过进行第一加热处理工序S02和第二加热处理工序S04这两个步骤的加热处理，从而进行Ag基底层30的Ag层32的烧成，因此能够良好地接合Ag基底层30的Ag层32和半导体元件3。
以上，对本发明的实施方式进行了说明，但本发明并不限定于此，在不脱离本发明的技术思想的范围内可适当进行变更。
例如，在本实施方式中，将构成电路层及金属层的金属板设为纯度99.99质量％的纯铝(4N铝)轧制板来进行了说明，但并不限定于此，也可以由其他铝或铝合金构成电路层及金属层。另外，也可以将构成电路层及金属层的金属板由铜或铜合金构成。此外，也可以设为经固相扩散接合铜板和铝板而成的结构。
另外，对作为绝缘层使用由AlN构成的陶瓷基板的情况进行了说明，但并不限定于此，也可以使用由Si3N4或Al2O3等构成的陶瓷基板，还可以利用绝缘树脂来构成绝缘层。
另外，散热器并不限定于本实施方式中举例说明的结构，对于散热器的结构没有特别的限定。
此外，也可以在散热器与金属层之间设置缓冲层。作为缓冲层，可使用由铝、铝合金或包含铝的复合材料(例如，AlSiC等)构成的板材。
另外，在本实施方式中，作为半导体装置举例说明了搭载有功率半导体元件的功率模块，但并不限定于此，只要是在由导电性材料构成的电路层上搭载有半导体元件的半导体装置即可。
例如，半导体装置也可以是作为半导体元件使用热电转换元件的热电转换模块。
另外，例如，如图6所示，半导体装置也可以搭载有LED元件(半导体元件)的LED装置(半导体装置)。
图6所示的LED装置101具备LED元件103和由导电性材料构成的电路层112。此外，LED元件103通过接合线107与电路层112电连接，具备由封装材108封装LED元件103及接合线107而成的结构。在电路层112的一面设置有由含玻璃Ag膏的烧成体构成的Ag基底层130，在LED元件103的背面设置有导电性反射膜116及保护膜115。并且，LED元件103被直接接合在Ag基底层130上。
由于在这种LED装置101中，也在电路层112的一面形成有Ag基底层130，并且该Ag基底层130和LED元件103被直接接合，因此即使在高温环境下使用的情况下，电路层112与LED元件103的接合可靠性也优异。
实施例
对为了确认本发明的有效性而进行的确认实验进行说明。
在陶瓷基板的一面上接合金属板而形成电路层。在此，陶瓷基板为AlN，尺寸为27mm×17mm×0.6mm。作为电路层的金属板为表1所示的材质的板，尺寸为25mm×15mm×0.3mm。
此外，在金属板为铝板的情况下，作为接合材使用Al-Si类钎料。另外，在金属板为铜板的情况下，作为接合材使用活性金属钎料(Ag-Cu-Ti钎料)。
通过在电路层的表面上涂布实施方式中说明的含玻璃Ag膏，并且在表1所示的条件下进行加热处理，从而形成Ag基底层(第一加热处理工序)。
此外，作为含玻璃Ag膏的玻璃粉末，使用包含90.6质量％的Bi2O3、2.6质量％的ZnO及6.8质量％的B2O3的无铅玻璃粉末。另外，作为树脂使用乙基纤维素，作为溶剂使用二乙二醇二丁醚。此外，添加二羧酸类的分散剂。
在此，调整含玻璃Ag膏中的Ag粉末的重量A和玻璃粉末的重量G的重量比A/G及分布量，如表1所示调整玻璃层和Ag层的厚度。
并且，在本发明例中，通过在Ag基底层上层压半导体元件，并且在表1所示的条件下进行加热处理，从而将半导体元件接合在电路层(第二加热处理工序)。半导体元件的尺寸为5mm×5mm×0.2mm。
在此，在本发明例1～23及比较例1～2中，利用溅射法以厚度为100nm的方式在半导体元件与电路层的接合面上形成由表1所示的材质构成的表面处理膜。
此外，在比较例1中，在未形成Ag基底层的情况下在电路层上形成厚度为2μm的Ag镀层，并且在该镀层上接合半导体元件。
在比较例2中，通过在Ag基底层上涂布氧化银膏并层压半导体元件，并进行氧化银膏的烧成，从而形成接合层来接合半导体元件。
作为氧化银膏，使用如下的氧化银膏：即，该氧化银膏通过使用市场上销售的氧化银粉末(和光纯药工业株式会社制)、作为还原剂的豆蔻醇、以及作为溶剂的2,2,4-三甲基-1,3-戊二醇单异丁酸酯，以氧化银粉末：80质量％、还原剂(豆蔻醇)：10质量％、溶剂(2,2,4-三甲基-1,3-戊二醇单异丁酸酯)：余量的比例混合而成。
另外，将氧化银膏的涂布厚度设为50μm，将烧成温度设为300℃，将烧成时间设为10分钟。此外，将半导体元件在层压方向上的加压压力设为30MPa。
(元件的平均Ag结晶粒径)
在上述本发明例及比较例的半导体装置中，利用EBSD来测量半导体元件接合后的Ag层的平均结晶粒径。
利用EBSD测量装置(FEI公司制的Quanta FEG 450，EDAX/TSL公司制的OIM DataCollection)和解析软件(EDAX/TSL公司制的OIM Data Abakysis ver.5.3)，在电子射线的加速电压：20Kv、测量步长：0.05μm下实施EBSD测量。
(冷热循环前后的接合率)
关于上述的本发明例及比较例的半导体装置，使用超声波探伤装置，由以下式求出半导体元件与电路层的接合率。在此，将初始接合面积设为接合前应接合的面积，即设为半导体元件面积。由于在超声波探伤图像中接合部内的白色部表示剥离，因此将该白色部的面积设为剥离面积。
(接合率)＝{(初始接合面积)-(剥离面积)}/(初始接合面积)×100
此外，对半导体装置进行冷热循环试验，并且比较初始接合率和冷热循环试验后的接合率。冷热循环是以-40℃、五分钟和200℃、15分钟作为一次循环来进行，并实施3000次循环。将评价结果示于表1。
[表1]
※4N铝：纯度为99.99质量％以上的铝
在Ag镀层上接合有半导体元件的比较例1及使用氧化银膏在Ag基底层上接合有半导体元件的比较例2中，冷热循环后的接合率大幅下降。当在比较例2中，施加达到200℃的高温的冷热循环负载时，推测为在由氧化银膏的烧结体构成的接合层中进行Ag结晶粒的生长，在Ag接合层内发生纵向龟裂并生成空隙，因此发生剥离。
相对于此，在Ag基底层上直接接合有半导体元件的本发明例中，即使在冷热循环之后接合率也不会发生较大的变化。认为这是因为，没有因冷热循环负载而发生Ag的晶粒生长。
由上述可知，根据本发明例，可提供一种半导体装置，即使在较高温环境下使用的情况下，也能够切实地接合电路层和半导体元件，能够稳定地使用该半导体装置。
产业上的可利用性
根据本发明的半导体装置，即使在较高温环境下使用的情况下，电路层与半导体元件的接合可靠性也优异，能够稳定地使用该半导体装置。
符号说明
1 功率模块(半导体装置)
3 半导体元件
3a 表面处理膜
10 功率模块用基板
11 陶瓷基板
12 电路层
30 Ag基底层
31 玻璃层
32 Ag层

Claims (3)

1.一种半导体装置，具备：电路层，由导电性材料构成；半导体元件，搭载在所述电路层的一面；以及陶瓷基板，配设在所述电路层的另一面，所述半导体装置的特征在于，
在所述电路层的一面形成有Ag基底层，所述Ag基底层具有玻璃层和层压在该玻璃层上的Ag层，
该Ag基底层的所述Ag层和所述半导体元件直接接合。
2.根据权利要求1所述的半导体装置，其特征在于，
在所述半导体元件的与所述Ag层接合的面形成有由Au或Au合金构成的Au膜及由Ag或Ag合金构成的Ag膜中的任一种。
3.根据权利要求1或2所述的半导体装置，其特征在于，
所述半导体元件为功率半导体元件。
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010287869A (ja) * 2009-05-15 2010-12-24 Mitsubishi Materials Corp パワーモジュール用基板、冷却器付パワーモジュール用基板、パワーモジュール及びパワーモジュール用基板の製造方法
US20130328204A1 (en) * 2012-06-07 2013-12-12 Ixys Corporation Solderless Die Attach to a Direct Bonded Aluminum Substrate

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1297046A (zh) 1969-08-25 1972-11-22
JP3922166B2 (ja) 2002-11-20 2007-05-30 三菱マテリアル株式会社 パワーモジュール用基板の製造方法並びにパワーモジュール用基板及びパワーモジュール
JP2006202938A (ja) 2005-01-20 2006-08-03 Kojiro Kobayashi 半導体装置及びその製造方法
JP4737116B2 (ja) 2007-02-28 2011-07-27 株式会社日立製作所 接合方法
US8018047B2 (en) * 2007-08-06 2011-09-13 Infineon Technologies Ag Power semiconductor module including a multilayer substrate
US8513534B2 (en) 2008-03-31 2013-08-20 Hitachi, Ltd. Semiconductor device and bonding material
JP5707886B2 (ja) 2010-11-15 2015-04-30 三菱マテリアル株式会社 パワーモジュール用基板、冷却器付パワーモジュール用基板、パワーモジュールおよびパワーモジュール用基板の製造方法
JP5966379B2 (ja) 2011-05-31 2016-08-10 三菱マテリアル株式会社 パワーモジュール、及び、パワーモジュールの製造方法
CN102810524B (zh) * 2011-05-31 2016-12-14 三菱综合材料株式会社 功率模块及功率模块的制造方法
JP5982954B2 (ja) * 2012-03-30 2016-08-31 三菱マテリアル株式会社 パワーモジュール、及び、パワーモジュールの製造方法
JP5664625B2 (ja) * 2012-10-09 2015-02-04 三菱マテリアル株式会社 半導体装置、セラミックス回路基板及び半導体装置の製造方法
JP5844299B2 (ja) 2013-03-25 2016-01-13 株式会社日立製作所 接合材、接合構造体
JP2015109434A (ja) * 2013-10-23 2015-06-11 日立化成株式会社 ダイボンド層付き半導体素子搭載用支持部材、ダイボンド層付き半導体素子及びダイボンド層付き接合板
WO2015060346A1 (ja) * 2013-10-23 2015-04-30 日立化成株式会社 ダイボンドシート及び半導体装置の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010287869A (ja) * 2009-05-15 2010-12-24 Mitsubishi Materials Corp パワーモジュール用基板、冷却器付パワーモジュール用基板、パワーモジュール及びパワーモジュール用基板の製造方法
US20130328204A1 (en) * 2012-06-07 2013-12-12 Ixys Corporation Solderless Die Attach to a Direct Bonded Aluminum Substrate

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