TW201616652A - 鰭式場效電晶體裝置結構與其形成方法 - Google Patents

鰭式場效電晶體裝置結構與其形成方法 Download PDF

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TW201616652A
TW201616652A TW104123375A TW104123375A TW201616652A TW 201616652 A TW201616652 A TW 201616652A TW 104123375 A TW104123375 A TW 104123375A TW 104123375 A TW104123375 A TW 104123375A TW 201616652 A TW201616652 A TW 201616652A
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fin
field effect
effect transistor
epitaxial
substrate
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張哲豪
程潼文
陳建穎
張哲誠
張永融
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台灣積體電路製造股份有限公司
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Abstract

本揭露提供一種鰭式場效電晶體裝置結構與其形成方法。鰭式場效電晶體裝置結構包括一基板與一隔離結構形成於基板之上。該鰭式場效電晶體裝置結構包括一鰭式結構延伸高於該基板，且該鰭式結構埋設於該基板之中。該鰭式場效電晶體裝置結構包括一磊晶結構形成於該鰭式結構之上，其中該磊晶結構具有類五邊形形狀，且其中該磊晶結構與該鰭式結構之間的一介面低於該隔離結構之一上表面。

Description

鰭式場效電晶體裝置結構與其形成方法
本揭露係有關於一種半導體結構，且特別有關於一種鰭式場效電晶體裝置結構與其形成方法。
半導體裝置使用於各種電子應用中，舉例而言，諸如個人電腦、手機、數位相機以及其他電子設備。半導體裝置的製造通常是藉由在半導體基板上依序沉積絕緣層或介電層材料、導電層材料以及半導體層材料，接著使用微影製程圖案化所形成的各種材料層，藉以在此半導體基板之上形成電路零件及組件。通常在單一個半導體晶圓上製造許多積體電路，並且藉由沿著切割線在積體電路之間進行切割，以切割位在晶圓上的各個晶粒。舉例而言，接著將個別的晶粒分別封裝在多晶片模組中或其它類型的封裝結構中。
隨著半導體工業進展到奈米技術製程節點，以追求高裝置密度、高性能與低成本。因為製造與設計方面的問題所帶來的挑戰，因此三維設計開始發展，例如鰭式場效電晶體(FinFET)。鰭式場效電晶體(FinFET)具有從基板延伸出來的薄的垂直”鰭”。鰭式場效電晶體的通道形成於垂直鰭之中。閘極位於鰭之上。鰭式場效電晶體之優點可包括降低短通道效應與 高電流流通。
雖然現有的鰭式場效電晶體元件及其製造方法已普遍足以達成預期的目標，然而卻無法完全滿足所有需求。
本揭露提供一種鰭式場效電晶體裝置結構(FinFET device structure)包括：一基板與一隔離結構形成於基板之上。該鰭式場效電晶體裝置結構包括一鰭式結構延伸高於該基板，且該鰭式結構埋設於該基板之中。該鰭式場效電晶體裝置結構包括一磊晶結構形成於該鰭式結構之上，其中該磊晶結構具有類五邊形形狀，且其中該磊晶結構與該鰭式結構之間的一介面低於該隔離結構之一上表面。
本揭露亦提供一種鰭式場效電晶體裝置結構，包括：一基板與一隔離結構形成於該基板之上。該鰭式場效電晶體裝置結構包括一鰭式結構沿伸高於該基板，其中該鰭式結構突出該隔離結構。該鰭式場效電晶體裝置結構包括一磊晶結構形成於該鰭式結構之上，其中該磊晶結構包括一底表面與一第一表面相連於該底表面，且其中該底表面與該第一表面之間的一角度為約90度至約175度。
本揭露又提供一種鰭式場效電晶體裝置結構之形成方法，包括：提供一基板與形成一隔離結構於該基板之上。方法包括形成一鰭式結構於該基板之上，其中該鰭式結構埋設於該隔離結構之中。方法包括形成複數個鰭式間隙壁於該鰭式結構之一上表面與複數個側壁上；以及移除該些鰭式間隙壁，以暴露該鰭式結構。方法包括凹陷該鰭式結構之一部份與該隔 離結構之一部份，以形成一溝槽於該隔離結溝之中。方法包括從該溝槽中磊晶成長一磊晶結構，其中該磊晶結構形成於該鰭式結構之上，且其中該磊晶結構與該鰭式結構之一介面低於該隔離結構之一上表面。
10‧‧‧鰭式場效電晶體裝置結構
15‧‧‧n型鰭式場效電晶體裝置結構(NMOS)
25‧‧‧p型鰭式場效電晶體裝置結構(PMOS)
102‧‧‧基板
104‧‧‧鰭式結構
105‧‧‧鰭式間隙壁
108‧‧‧隔離結構
110‧‧‧閘極電極
112‧‧‧第一硬罩幕層
114‧‧‧第二硬罩幕層
115‧‧‧閘極間隙壁
202‧‧‧底部抗反射塗層(BARC)
204‧‧‧溝槽
210‧‧‧磊晶結構
210A‧‧‧第一表面
210B‧‧‧第二表面
210C‧‧‧第三表面
210D‧‧‧第四表面
210E‧‧‧第五表面
H1‧‧‧高度
H2‧‧‧高度
H3‧‧‧高度
W1‧‧‧寬度
W2‧‧‧寬度
D1‧‧‧深度
θ1‧‧‧角度
θ2‧‧‧角度
P1‧‧‧第一交叉點
P2‧‧‧第二交叉點
根據以下的詳細說明並配合所附圖式做完整揭露。應注意的是，根據本產業的一般作業，圖示並未必按照比例繪製。事實上，可能任意的放大或縮小元件的尺寸，以做清楚的說明。
第1圖顯示依據本揭露之一些實施例之鰭式場效電晶體裝置結構之示意圖。
第2A-2F圖顯示依據本揭露之一些實施例之形成鰭式場效電晶體結構(FinFET device structure)之各個製程階段之剖面圖。
第3圖顯示依據本揭露之一些實施例之第2F圖之區域A之放大圖。
以下的揭露內容提供許多不同的實施例或範例以實施本案的不同特徵。以下的揭露內容敘述各個構件及其排列方式的特定範例，以簡化說明。當然，這些特定的範例並非用以限定。例如，若是本揭露書敘述了一第一特徵形成於一第二特徵之上或上方，即表示其可能包含上述第一特徵與上述第二特徵是直接接觸的實施例，亦可能包含了有附加特徵形成於上述第一特徵與上述第二特徵之間，而使上述第一特徵與第二特 徵可能未直接接觸的實施例。另外，以下揭露書不同範例可能重複使用相同的參考符號及/或標記。這些重複係為了簡化與清晰的目的，並非用以限定所討論的不同實施例及/或結構之間有特定的關係。
下文描述實施例的各種變化。藉由各種視圖與所 繪示之實施例，類似的元件標號用於標示類似的元件。應可理解的是，額外的操作步驟可實施於所述方法之前、之間或之後，且在所述方法的其他實施例中，可以取代或省略部分的操作步驟。
本揭露提供形成鰭式場效電晶體(FinFET)裝置結 構之實施例。第1圖顯示依據本揭露之一些實施例之鰭式場效電晶體結構10之示意圖。鰭式場效電晶體結構10包括n型鰭式場效電晶體結構(NMOS)15與p型鰭式場效電晶體結構(PMOS)25。
鰭式場效電晶體結構10包括基板102。基板102可 以由矽或其他半導體材料所組成。另外且額外的，基板102可包括其他元素半導體，例如，鍺。在一些實施例中，基板102由化合物半導體所組成，例如，碳化矽(silicon carbide,SiC)、砷化鎵(gallium arsenic,GaAs)、砷化銦(indium arsenide,InAs)或磷化銦(indium phosphide,InP)。在一些實施例中，基板102由合金半導體所組成，例如矽鍺(Silicon germanium,SiGe)、矽碳化鍺(silicon germanium carbide,SiGeC)、砷磷化鎵(gallium arsenic phosphide,GaAsP)或磷化鎵銦(gallium indium phosphide,GaInP)。在一些實施例中，基板102包括磊晶層。舉 例而言，基板102是磊晶層位於塊狀半導體之上。
鰭式場效電晶體結構10尚包括一或多個鰭式結構 104(例如矽鰭)從基板102延伸。鰭式結構104可任意包括鍺(Ge)。鰭式結構104可藉由合適製程而形成，例如微影製程與蝕刻製程。在一些實施例中，使用乾式蝕刻或電漿製程從蝕刻基板102而得到鰭式結構104。
在一些實施例中，鰭式結構104由雙重圖案微影製 程(double-patterning lithography,DPL)而得。雙重圖案微影製程(DPL)是一種將圖案構成於基板之上的方法，其中藉由將圖案分成兩種交叉圖案。雙重圖案微影製程(DPL)能提高特徵(例如鰭)的密度。
形成隔離結構108，例如淺溝隔離結構，以環繞該 鰭式結構104。在一些實施例中，鰭式結構104之一底部份被隔離結構108所圍繞，以及鰭式結構104之一上部份突出於隔離結構108，如第1圖所示。另言之，鰭式結構104之一部份埋設於隔離結構108之中。隔離結構108用於避免電性干擾或串音(crosstalk)。
鰭式場效電晶體結構10尚包括一閘極堆疊結構， 閘極堆疊結構包括閘極電極110與閘極介電層(未顯示)。閘極堆疊結構形成於該鰭式結構104之中心部份之上。在一些其他實施例中，多個閘極堆疊結構形成於鰭式結構之上。
在一些實施例中，閘極堆疊結構是虛設閘極堆疊 且被金屬閘極所取代，在進行高熱預算製程(high thermal budget processes)之後。
閘極介電層(未顯示)可包括介電材料，例如氧化 矽、氮化矽、氮氧化矽、具有高介電係數(high-k)之介電材料，或上述之組合。高介電係數(high-k)之介電材料之例子包括氧化鉿(hafnium oxide)、氧化鋯(zirconium oxide)、氧化鋁(aluminum oxide)、二氧化鉿-氧化鋁合金(hafnium dioxide-alumina alloy)、矽氧化鉿(hafnium silicon oxide)、氮矽氧化鉿(hafnium silicon oxynitride)、氧化鉭鉿(hafnium tantalum oxide)、氧化鈦鉿(hafnium titanium oxide)、氧化鋯鉿(hafnium zirconium oxide)、類似之材料或上述之組合。
閘極電極110可包括多晶矽或金屬。金屬包括氮化 鉭(tantalum nitride,TaN)、矽化鎳(nickel silicon,NiSi)、矽化鈷(cobalt silicon,CoSi)、鉬(molybdenum,Mo)、銅(copper,Cu)、鎢(tungsten,W)、鋁(aluminum,Al)、鈷(cobalt,Co)、鋯(zirconium,Zr)、鉑(platinum,Pt)或其他合適的材料。閘極電極110可由閘極後製程(或閘極取代製程)所形成。在一些實施例中，閘極堆疊結構包括其他層，例如介面層、蓋層、擴散/阻障層或其他合適的層。
閘極堆疊結構由沉積製程、微影製程與蝕刻製程 所形成。沉積製程包括化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積製程(ALD)、高密度電漿化學氣相沉積(high density plasma CVD,HDPCVD)、金屬有機物化學氣相沉積(metal organic CVD,MOCVD)、遠端電漿化學氣相沉積(remote plasma CVD,RPCVD)、電漿增強化學氣相沉積(plasma enhanced CVD,PECVD)、電鍍(plating)、其他合適的方法及/ 或上述之組合。微影製程包括光阻塗佈(photoresist coating)(例如旋轉塗佈)、軟烘烤(soft baking)、光罩對準(mask aligning)、曝光(exposure)、曝光後烘烤(post-exposure)、光阻顯影(developing photoresist)、潤洗(rising)、乾燥(例如硬烘烤(hard baking))。蝕刻製程包括乾式蝕刻製程、濕式蝕刻製程或上述之組合。另外的，微影製程可以被其他適合的方法執行或取代，例如無光罩微影(maskless photolithography)、電子束寫入(electron-beam writing)與離子束寫入(ion-beam writing)。
第2A-2F圖顯示依據本揭露之一些實施例之形成 鰭式場效電晶體結構(FinFET device structure)之各個製程階段之剖面圖。第2A-2F圖顯示沿著第1圖之箭頭1之側視圖，且箭頭1平行於X軸。
請參見第2A圖，第一硬罩幕層112形成於閘極電極110之上，且第二硬罩幕層114形成於第一硬罩幕層112之上。在一些實施例中，第一硬罩幕層112由氧化矽、氮化矽、氮氧化矽或其他合適的材料所組成。在一些實施例中，第二硬罩幕層114由氧化矽、氮化矽、氮氧化矽或其他合適的材料所組成。
閘極間隙壁115形成於閘極電極110之相對側壁上，鰭式間隙壁105形成於鰭式結構104之相對側壁上。閘極間隙壁115與鰭式間隙壁105各自包括介電材料，例如氧化矽、氮化矽、碳化矽、氮氧化矽或上述之組合。
之後，底部抗反射塗層(bottom anti-reflective coating,BARC)202形成於閘極間隙壁115之上。底部抗反射塗層202位於光阻層之下，於圖案化製程期間，以幫助圖案化轉 移至硬罩幕層112、114。在一些實施例中，當佈植製程執行於N型場效電晶體(NMOS)裝置結構15時，底部抗反射塗層202與形成於底部抗反射塗層202之上的光阻(未顯示)形成於閘極電極110之上，以覆蓋P型場效電晶體(PMOS)裝置結構25中的閘極電極110。
依據本揭露之實施例，如第2B圖所示，之後，藉 由蝕刻製程移除光阻(未顯示)與底部抗反射塗層202。蝕刻製程可以是乾式蝕刻製程或濕式蝕刻製程。在一些實施例中，第一乾式蝕刻製程操作於壓力範圍為約3mtorr至約50mtorr。在一些實施例中，使用於第一乾式蝕刻製程之氣體包括甲烷(CH4)、氮氣(N2)、氦氣(He)、氧氣(O2)或上述之組合。在一些實施例中，第一乾式蝕刻製程操作於電源範圍為約50W至約1000W。在一些實施例中，第一乾式蝕刻製程操作於溫度範圍為約20度至約80度。
依據本揭露之實施例，如第2C圖所示，在移除底 部抗反射塗層202之後，移除一部份的閘極間隙壁115與一部份之鰭式間隙壁105。更特定而言，移除閘極間隙壁115之上部份，以暴露第二硬罩幕層114。移除鰭式間隙壁105之上部份，以暴露鰭式結構104。
在一些實施例中，當閘極間隙壁115與鰭式間隙壁105由氮化矽所組成時，執行第二蝕刻製程，以移除氮化矽。在一些實施例中，第二蝕刻製程是第二乾式蝕刻製程且操作於壓力範圍為約3mtorr至約50mtorr。在一些實施例中，使用於第二乾式蝕刻製程之氣體包括氟甲烷(CH3F)、二氟甲烷 (CH2F2)、甲烷(CH4)、氬氣(Ar)、溴化氫(HBr)、氮氣(N2)、氦氣(He)、氧氣(O2)或上述之組合。在一些實施例中，第二乾式蝕刻製程操作於電源範圍為約50W至約1000W。在一些實施例中，第二乾式蝕刻製程操作於溫度範圍為約20度至約70度。
在第二乾式蝕刻製程之後，各自的鰭式間隙壁105 具有第一高度H1。在一些實施例中，第一高度H1範圍為約0.1奈米至約50奈米。
依據本揭露之實施例，如第2D圖所示，在移除一 部份之閘極間隙壁115與一部份之鰭式間隙壁105之後，移除殘餘的鰭式間隙壁105。鰭式間隙壁105藉由第三蝕刻製程而移除。第三蝕刻製程可以是乾式蝕刻製程或濕式蝕刻製程。
在一些實施例中，第三蝕刻製程是第三乾式蝕刻 製程且操作於壓力範圍為約3mtorr至約50mtorr。在一些實施例中，使用於第三乾式蝕刻製程之氣體包括氟甲烷(CH3F)、二氟甲烷(CH2F2)、甲烷(CH4)、氬氣(Ar)、溴化氫(HBr)、氮氣(N2)、氦氣(He)、氧氣(O2)或上述之組合。在一些實施例中，第三乾式蝕刻製程操作於電源範圍為約50W至約1000W。在一些實施例中，第三乾式蝕刻製程操作於溫度範圍為約20度至約70度。
鰭式場效電晶體裝置結構之性能表現與磊晶結構 (例如第2F圖之標號210)之體積相關。如果鰭式間隙壁105殘留於隔離結構之上，磊晶結構(例如第2F圖之標號210)之體積會受限於鰭式間隙壁105。為了獲得較大的磊晶結構體積，需注意的是要移除全部的鰭式間隙壁105。另言之，無任何鰭式間隙壁形成相鄰於鰭式結構104。
依據本揭露之實施例，如第2E圖所示，在第三乾 式蝕刻製程之後，移除一部份之鰭式結構104。之後，移除一部份之隔離結構108。鰭式結構104與隔離結構108獨立地被蝕刻製程所移除，例如乾式蝕刻製程或濕式蝕刻製程。
如第2E圖所示，殘留的鰭式結構104之頂表面低於 隔離結構108之頂表面。藉由凹陷一部份的鰭式結構104與一部份之隔離結構108以形成溝槽204。凹陷製程可以是乾式蝕刻製程、濕式蝕刻製程或上述之組合。使用於濕式蝕刻製程之濕式蝕刻溶液包括氫氧化四甲基銨(tetraamethylammonium hydroxide,NH4OH)、氫氧化鉀(potassium hydroxide,KOH)、氟化氫(hydrofluoric acid,HF)、氫氧化四甲基銨(tetramethylammonium hydroxide,TMAH)、其他合適的溶液或上述之組合。乾式蝕刻製程包括偏壓電漿蝕刻製程。在一些實施例中，使用於偏壓電漿蝕刻製程中的氣體包括四氟甲烷(tetrafluoromethane,CF4)、三氟化氮(Nitrogen trifluoride,NF3)、六氟化硫(sulfur hexafluoride,SF6)或氦(helium,He)。
需注意的是，磊晶結構(顯示於第2F圖，例如標號 210)之後會形成於溝槽204中，因此，溝槽204之尺寸應該被適當地控制。溝槽204具有底表面與斜側壁相連於底表面。溝槽204具有深度D1與介於底表面與側壁之角度θ1。在一些實施例中，深度D1為約0.1奈米至約50奈米。在一些實施例中，介於溝槽204之底表面與側壁之間角度θ1為約90度至約175度。如果角度θ1太大，磊晶結構(顯示於第2F圖，例如標號210)可能有過大的成長空間。如果角度θ1太小，磊晶結構(顯示於第2F 圖，例如標號210)的體積將會被限制於小空間內，且磊晶結構將會更小。磊晶結構之裝置遷移率將會被體積所影響。
依據本揭露之實施例，如第2F圖所示，在移除一 部份之鰭式結構104與一部份之隔離結構108之後，形成磊晶結構210於鰭式結構104之上。
磊晶結構210包括源極/汲極結構。在一些實施例 中，當需要N型場效電晶體裝置時，源極/汲極磊晶結構包括磊晶成長的矽。另外地，當需要P型場效電晶體裝置時，源極/汲極磊晶結構包括磊晶成長的矽鍺(SiGe)。磊晶結構210可以是單一層或多層。
需注意的是介於磊晶結構210與鰭式結構104之間 的表面低於隔離結構108之上表面。磊晶結構210形成於溝槽204之中且連續向上延伸，以形成似五邊形形狀(pentagon-like shape)。
第3圖顯示依據本揭露之一些實施例之第2F圖之 區域A之放大圖。如第3圖所示，磊晶結構210具有似五邊形形狀(pentagon-like shape)。磊晶結構210具有第一表面210A、第二表面210B、第三表面210C、第四表面210D與第五表面210E。 每一個第一表面210A、第二表面210B、第三表面210C、第四表面210D具有(111)晶向方位(crystallographic orientation)。
介於第一表面210A與第二表面210B之間的第一交 叉點(intersection)P1高於隔離結構之上表面。介於第三表面210C與第四表面210D之間的第二交叉點(intersection)P2高於隔離結構之上表面。第一交叉點P1與第二交叉點P2大致上等 高。第一交叉點P1從隔離結構108之上表面延伸至高度H2。在一些實施例中，高度H2為約0.1奈米至約50奈米。介於第五表面210E與第一表面210A之間的角度θ1為約90度至約175度。介於第一表面210A與第二表面210B之間的角度θ2為約10度至約175度。
如第3圖所示，磊晶結構210具有高度H3與寬度 W1。在一些實施例中，高度H3為約1奈米至約100奈米。如果高度H3太大，電阻會變低。如果高度H3太小，電阻會變得太高而影響裝置速度。在一些實施例中，寬度W1為約1奈米至約100奈米。如果寬度W1太大，磊晶結構210可能會與相鄰的結構合併而造成短路效應。如果寬度W1太小，用於接觸磊晶結構210之接觸視窗(contact window)將會太窄，且因此破壞電路效應。 鰭式結構104具有寬度W2。在一些實施例中，鰭式結構104之寬度W2小於磊晶結構210之寬度W1。
此外，磊晶結構210之高度H3比寬度W1之比率 (H3/W1)為約1至約100。如果比率太大，則磊晶高度將會太短而影響電阻值。如果比率太小，則磊晶體積將會太小而縮短裝置之張力(tension)。上述兩者將會影響裝置之遷移率。
磊晶結構210包括單一元素半導體材料，例如鍺或 矽；或化合物半導體材料，例如砷化鎵(gallium arsenide,GaAs)、砷化鋁鎵(aluminum gallium arsenide,AlGaAs)；或半導體合金，例如矽鍺、磷砷化鎵(gallium arsenide phosphide,GaAsP)。
磊晶結構210由磊晶製程所形成。磊晶製程包括選 擇性磊晶成長製程(selective epitaxial growth,SEG)、化學氣相沉積製程(例如氣相磊晶(vapor-phase epitaxy,VPE)、低壓化學氣相沉積(low pressure chemical vapor deposition(LPCVD)及/或超高真空化學氣相沉積(ultra-high vacuum CVD(UHV-CVD))、分子束磊晶(molecular beam epitaxy)、其他合適的磊晶製程或上述之組合。磊晶結構210之形成方法可使用氣相及/或液相前驅物，其之後可與鰭式結構104之成份反應。
在磊晶製程期間，可以原處摻雜或未摻雜磊晶結 構210。舉例而言，可以摻雜硼至磊晶成長矽鍺磊晶結構；且可以摻雜碳至磊晶成長矽磊晶結構以形成矽：碳(Si：C)磊晶結構；摻雜磷以形成矽：磷(Si：P)磊晶結構或摻雜碳與磷以形成矽碳磷(SiCP)磊晶結構。可藉由離子佈植製程、電漿浸入離子佈植製程(plasma immersion ion implantation(PIII)process)、氣體及/或固體擴散源製程(gas and/or solid source diffusion process)、其他合適的製程或上述之組合以達成摻雜。磊晶結構210後續可暴露於退火製程，例如快速熱退火製程。退火製程可用於活化摻雜質。退火製程包括快速熱退火製程(RTA)及/或雷射退火製程。
如果快速熱退火製程並未原處進行摻雜，進行第 二摻雜製程(例如接面佈值製程(junction implant process))以摻雜磊晶結構210。
鰭式結構104包括通道區域(未顯示)被閘極電極 110包圍或圍繞。磊晶結構210之晶格常數不同於基板102之晶格常數，通道區域可以被伸張或是壓縮，使鰭式場效電晶體裝 置結構之載子遷移率之提升變成可行，且增強鰭式場效電晶體裝置結構之性能。
之後，鰭式場效電晶體裝置結構可繼續進行其他 製程，以形成其他結構或裝置。在一些實施例中，金屬化結構包括垂直內連線，例如導通孔或接觸插塞，與水平內連線，例如金屬線。各種內連線結構可使用各種導電材料，包括銅、鎢及/或矽化物。
鰭式場效電晶體結構之性能表現與磊晶結構210 之體積相關。如果磊晶結構210之體積太小，鰭式場效電晶體結構之操作速度會太低而不符合需求。
如上所述，如果鰭式間隙壁105殘留於隔離結構 108之上，磊晶結構之成長體積會受限於鰭式間隙壁105。為了獲得較大體積之磊晶結構，完全移除鰭式間隙壁105。此外，移除一部份之隔離結構108，以擴大溝槽204之寬度。需注意的是，溝槽204設計成具有深度D1與角度θ1，且因此磊晶結構210具有較多空間成長或沿伸。
需注意的是，藉由控制溝槽204之深度D1與角度θ 1，以控制磊晶結構210的體積與高度H1。只要能充分地控制磊晶結構210的體積與高度H1，鰭式場效電晶體結構之性能能更增進。更特定而言，鰭式場效電晶體結構之操作速度能更提升。此外，閘極電極110之電阻可被降低。
本揭露提供形成鰭式場效電晶體結構之實施例。 鰭式場效電晶體結構包括隔離結構形成於基板之上，鰭式結構延伸高於基板。藉由凹陷一部份之鰭式結構與一部份之隔離結 構，以形成溝槽。磊晶結構形成於鰭式結構之上與溝槽之中。 磊晶結構相鄰於閘極堆疊結構。藉由調整溝槽之深度與角度，以控制磊晶結構之體積與高度。只要能有效地控制磊晶結構的體積，鰭式場效電晶體結構之性能夠更增進。更特定而言，鰭式場效電晶體結構之操作速度能夠更加提升。
在一些實施例中，本揭露提供一種鰭式場效電晶 體裝置結構(FinFET device structure)包括：一基板與一隔離結構形成於基板之上。該鰭式場效電晶體裝置結構包括一鰭式結構延伸高於該基板，且該鰭式結構埋設於該基板之中。該鰭式場效電晶體裝置結構包括一磊晶結構形成於該鰭式結構之上，其中該磊晶結構具有類五邊形形狀，且其中該磊晶結構與該鰭式結構之間的一介面低於該隔離結構之一上表面。
在一些實施例中，本揭露提供一種鰭式場效電晶 體裝置結構，包括：一基板與一隔離結構形成於該基板之上。 該鰭式場效電晶體裝置結構包括一鰭式結構沿伸高於該基板，其中該鰭式結構突出該隔離結構。該鰭式場效電晶體裝置結構包括一磊晶結構形成於該鰭式結構之上，其中該磊晶結構包括一底表面與一第一表面相連於該底表面，且其中該底表面與該第一表面之間的一角度為約90度至約175度。
在另一些實施例中，本揭露有關於一種鰭式場效 電晶體裝置結構之形成方法，包括：提供一基板與形成一隔離結構於該基板之上。方法包括形成一鰭式結構於該基板之上，其中該鰭式結構埋設於該隔離結構之中。方法包括形成複數個鰭式間隙壁於該鰭式結構之一上表面與複數個側壁上；以及移 除該些鰭式間隙壁，以暴露該鰭式結構。方法包括凹陷該鰭式結構之一部份與該隔離結構之一部份，以形成一溝槽於該隔離結溝之中。方法包括從該溝槽中磊晶成長一磊晶結構，其中該磊晶結構形成於該鰭式結構之上，且其中該磊晶結構與該鰭式結構之一介面低於該隔離結構之一上表面。
前述內文概述了許多實施例的特徵，使本技術領 域中具有通常知識者可以從各個方面更佳地了解本揭露。本技術領域中具有通常知識者應可理解，且可輕易地以本揭露為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本揭露的發明精神與範圍。在不背離本揭露的發明精神與範圍之前提下，可對本揭露進行各種改變、置換或修改。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
102‧‧‧基板
104‧‧‧鰭式結構
108‧‧‧隔離結構
115‧‧‧閘極間隙壁
210‧‧‧磊晶結構

Claims (16)

  1. 一種鰭式場效電晶體裝置結構(FinFET device structure)，包括：一基板；一隔離結構形成於基板之上；一鰭式結構延伸高於該基板，其中該鰭式結構埋設於該基板之中；以及一磊晶結構形成於該鰭式結構之上，其中該磊晶結構具有類五邊形形狀，且其中該磊晶結構與該鰭式結構之間的一介面低於該隔離結構之一上表面。
  2. 如申請專利範圍第1項所述之鰭式場效電晶體裝置結構，尚包括：一閘極堆疊結構形成於該鰭式結構之一中心部份；以及複數個閘極間隙壁相鄰於該閘極堆疊結構。
  3. 如申請專利範圍第1項所述之鰭式場效電晶體裝置結構，其中該磊晶結構形成於一溝槽中，且該溝槽在該隔離結構中具有一深度為約0.1奈米至約50奈米。
  4. 如申請專利範圍第1項所述之鰭式場效電晶體裝置結構，其中該磊晶結構包括一底表面與一第一表面相連於該底表面，且其中該底表面與該第一表面之間的一角度為約90度至約175度。
  5. 如申請專利範圍第4項所述之鰭式場效電晶體裝置結構，其中該磊晶結構尚包括一第二表面相連於該第一表面，且該第一表面與該第二表面之間的一交叉點高於該隔離結構 之一上表面。
  6. 如申請專利範圍第1項所述之鰭式場效電晶體裝置結構，其中該磊晶結構包括一第一寬度，該鰭式結構具有一第二寬度，且該第一寬度大於該第二寬度。
  7. 如申請專利範圍第6項所述之鰭式場效電晶體裝置結構，其中該磊晶結構包括一第一高度，該第一高度比該第一寬度之一比率為約1至100。
  8. 一種鰭式場效電晶體裝置結構，包括：一基板；一隔離結構形成於該基板之上；一鰭式結構沿伸高於該基板，其中該鰭式結構突出該隔離結構；以及一磊晶結構形成於該鰭式結構之上，其中該磊晶結構包括一底表面與一第一表面相連於該底表面，且其中該底表面與該第一表面之間的一角度為約90度至約175度。
  9. 如申請專利範圍第8項所述之鰭式場效電晶體裝置結構，其中該該磊晶結構尚包括一第二表面相連於該第一表面，且該第一表面與該第二表面之間的一交叉點高於該隔離結構之一上表面。
  10. 如申請專利範圍第8項所述之鰭式場效電晶體裝置結構，其中該磊晶結構具有一第一寬度與一第一高度，且該高度比該第一寬度之比率為約1至約100。
  11. 如申請專利範圍第10項所述之鰭式場效電晶體裝置結構，其中該鰭式結構具有一第二寬度，且該第一寬度大於該第 二寬度。
  12. 如申請專利範圍第8項所述之鰭式場效電晶體裝置結構，尚包括：一閘極堆疊結構形成於該鰭式結構之一中心部份；以及該磊晶結構相鄰於該閘極堆疊結構。
  13. 如申請專利範圍第11項所述之鰭式場效電晶體裝置結構，其中該磊晶結構形成於一溝槽中，且該溝槽在該隔離結構中具有一深度為約0.1奈米至約50奈米。
  14. 一種鰭式場效電晶體裝置結構之形成方法，包括：提供一基板；形成一隔離結構於該基板之上；形成一鰭式結構於該基板之上，其中該鰭式結構埋設於該隔離結構之中；形成複數個鰭式間隙壁於該鰭式結構之一上表面與複數個側壁上；移除該些鰭式間隙壁，以暴露該鰭式結構；凹陷該鰭式結構之一部份與該隔離結構之一部份，以形成一溝槽於該隔離結溝之中；以及從該溝槽中磊晶成長一磊晶結構，其中該磊晶結構形成於該鰭式結構之上，且其中該磊晶結構與該鰭式結構之一介面低於該隔離結構之一上表面。
  15. 如申請專利範圍第14項所述之鰭式場效電晶體裝置結構之形成方法，尚包括：形成一閘極堆疊結構於該鰭式結構之一中心部份；以及 形成複數個閘極間隙壁於該鰭式結構之上。
  16. 如申請專利範圍第14項所述之鰭式場效電晶體裝置結構之形成方法，其中凹陷該鰭式結構之一部份以形成該溝槽包括：對該鰭式結構進行一乾式蝕刻或一濕式蝕刻。
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