TW201608719A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TW201608719A
TW201608719A TW104107077A TW104107077A TW201608719A TW 201608719 A TW201608719 A TW 201608719A TW 104107077 A TW104107077 A TW 104107077A TW 104107077 A TW104107077 A TW 104107077A TW 201608719 A TW201608719 A TW 201608719A
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semiconductor layer
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layer
semiconductor
semiconductor device
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Yukie Nishikawa
Yasuhiko Akaike
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Toshiba Kk
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66946—Charge transfer devices
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

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Abstract

本發明之實施形態提供一種可提高耐壓及降低損失之半導體裝置。 實施形態之半導體裝置包括：第2導電型之第2半導體層，其選擇性地設置於第1導電型之第1半導體層上；第1導電型之第3半導體層，其設置於上述第2半導體層上；第2導電型之第4半導體層，其選擇性地設置於上述第1半導體層上；及控制電極，其介隔絕緣膜而與上述第2半導體層及上述第3半導體層相鄰，且位於上述第2半導體層與上述第4半導體層之間。而且，進而包括半導體區域，上述半導體區域介隔上述絕緣膜而與上述控制電極之底部相鄰，並設置於上述第1半導體層中或上述第4半導體層中之至少任一者中，且包含至少一種電氣惰性之元素。

Description

半導體裝置
[相關申請案]
本申請案享受以日本專利申請2014-165984號(申請日：2014年8月18日)為基礎申請案之優先權。本申請案以參考該基礎申請案之方式包含基礎申請案之所有內容。
實施形態係關於一種半導體裝置。
用於開關之半導體裝置亦被稱為功率半導體裝置等，被利用於車載或智慧電網(smart grid)等各種用途。而且，要求功率半導體裝置具有高耐壓特性及低損失性(低正向電壓Vf)或高速性(開關速度之高速化)等。例如，具有溝槽閘極構造之IEGT(Injection Enhanced Gate Transistor，電子注入增強閘極電晶體)適於要求高耐壓及高速性之用途。IEGT中有包含P型浮動層者，該P型浮動層配置於溝槽間，使電洞電流密度提高。浮動層促進載子之積存，實現低損失性。因此，浮動層較佳為較閘極電極更深地形成。然而，若使浮動層之P型雜質較深地擴散，則有浮動層越過閘極電極而與基極層相連，使IEGT之特性劣化之情況。
本發明之實施形態提供一種可提高耐壓及降低損失之半導體裝置。
實施形態之半導體裝置包括：第1導電型之第1半導體層；第2導電型之第2半導體層，其選擇性地設置於上述第1半導體層上；第1導電型之第3半導體層，其設置於上述第2半導體層上；第2導電型之第4半導體層，其選擇性地設置於上述第1半導體層上；及控制電極，其自上述第3半導體層側到達上述第1半導體層中，介隔絕緣膜而與上述第2半導體層及上述第3半導體層相鄰，且位於上述第2半導體層與上述第4半導體層之間。而且，進而包括半導體區域，該半導體區域設置介隔上述絕緣膜而與上述控制電極之底部相鄰，並設置於上述第1半導體層中或上述第4半導體層中之至少任一者中，且包含至少一種電氣惰性之元素。
1‧‧‧半導體裝置
2‧‧‧半導體裝置
10‧‧‧N型基極層
10a‧‧‧表面
20‧‧‧P型基極層
30‧‧‧N型射極層
40‧‧‧閘極電極
40e‧‧‧介隔絕緣膜而與閘極電極之底部相接之N型基極層端
41‧‧‧閘極溝槽
43‧‧‧絕緣膜
45‧‧‧層間絕緣膜
47‧‧‧開口
50‧‧‧P型浮動層
50a~50d‧‧‧區域
50e‧‧‧P型浮動層50之底部
55‧‧‧P型浮動層
55a‧‧‧下表面
60‧‧‧半導體區域
70‧‧‧P型集極層
80‧‧‧射極電極
90‧‧‧集極電極
103‧‧‧X方向上相鄰之兩個閘極電極40之中央之區域
105‧‧‧閘極電極40之區域與區域103之間之區域
d1‧‧‧距離
d2‧‧‧距離
IC‧‧‧集極電流
ISB‧‧‧負阻區域
VC‧‧‧集極-射極間之電壓
X、Y、Z‧‧‧軸
圖1係表示實施形態之半導體裝置之模式剖面圖。
圖2(a)~(c)係表示實施形態之半導體裝置之製造過程之模式剖面圖。
圖3(a)、(b)係表示繼圖2之後的製造過程之模式剖面圖。
圖4(a)、(b)係表示實施形態之半導體裝置之特性之模式圖。
圖5係表示比較例之半導體裝置之模式剖面圖。
圖6(a)、(b)係表示比較例之半導體裝置之特性之模式圖。
以下，一面參照圖式一面對實施形態進行說明。對於圖式中之相同部分標註相同編號並適當省略其詳細說明，而對不同部分進行說明。再者，圖式為模式性或概念性，各部分之厚度與寬度之關係、部分間之大小之比率等未必與現實相同。又，即便於表示相同部分之情形時，亦有根據圖式而將彼此之尺寸或比率不同地表示之情況。
進而，使用各圖中所示之X軸、Y軸及Z軸對各部分之配置及構成進行說明。X軸、Y軸、Z軸相互正交，分別表示X方向、Y方向、Z方 向。又，有以Z方向為上方、其相反方向為下方而進行說明之情況。
圖1係表示實施形態之半導體裝置1之模式剖面圖。半導體裝置1例如為IEGT。以下，將第1導電型設為N型、第2導電型設為P型而進行說明，但並不限定於此。亦可將第1導電型設為P型、第2導電型設為N型。
半導體裝置1包括第1半導體層(以下，稱為N型基極層10)、第2半導體層(以下，稱為P型基極層20)、及第3半導體層(以下，稱為N型射極層30)。P型基極層20選擇性地設置於N型基極層10上。N型射極層30設置於P型基極層20上。
半導體裝置1進而包括至少一個控制電極(以下，稱為閘極電極40)及絕緣膜43。閘極電極40自N型射極層30側延伸至N型基極層10中。閘極電極40介隔絕緣膜43而與P型基極層20及N型射極層相鄰。又，閘極電極40介隔絕緣膜43而與N型基極層10相鄰。
此例中，複數個閘極電極40沿X方向排列配置。又，閘極電極40分別沿Y方向延伸。複數個閘極電極40亦可利用未圖示之部分相連。又，複數個閘極電極40亦可利用未圖示之閘極配線而電性連接。P型基極層20及N型射極層30設置於X方向上相鄰之兩個閘極電極40之間。
半導體裝置1進而包括第4半導體層(以下，稱為P型浮動層50)及半導體區域60。P型浮動層50設置於閘極電極40之與P型基極層20相反之側。即，於沿X方向排列之複數個閘極電極40之間，P型基極層20及p型浮動層50沿X方向交替配置。P型浮動層50於相鄰之閘極電極40之間設置於N型基極層10上。
半導體區域60設置於介隔絕緣膜43而與閘極電極40之底部相接之N型基極層10中之區域40e與P型浮動層50之間。半導體區域60於N型基極層10或P型浮動層50之至少任一者中包含至少一種電氣惰性之 元素。半導體區域60亦可跨及N型基極層10中與P型浮動層50中之兩者之區域而形成。半導體區域60包含例如碳、氮、氟中之至少一種元素。
半導體裝置1進而包括第5半導體層(以下，稱為P型集極層70)、層間絕緣膜45、第1電極(以下，稱為射極電極80)、及第2電極(以下，稱為集極電極90)。
P型集極層70設置於N型基極層10之與P型基極層20相反之側。P型集極層70例如與N型基極層10相接。
層間絕緣膜45以覆蓋閘極電極40及P型浮動層50之方式形成。層間絕緣膜45於N型射極層30之正上方具有開口47。
射極電極80介隔層間絕緣膜45而覆蓋閘極電極40與P型浮動層50。又，射極電極80覆蓋N型射極層30，且經由開口47而電性連接於N型射極層30。
集極電極90設置於P型集極層70之與N型基極層10相反之側。集極電極90電性連接於P型集極層70。
此處，P型浮動層50較閘極電極40更深地形成。即，P型浮動層50之底部50e與P型集極層70之距離d1短於閘極電極40之底部與P型集極層70之距離d2。又，P型浮動層50未電性連接於射極電極80、集極電極90及閘極電極40之任一者。
其次，參照圖2(a)~圖2(c)、圖3(a)及圖3(b)對半導體裝置1之製造方法進行說明。圖2(a)~圖3(b)係表示半導體裝置1之製造過程之模式剖面圖。
如圖2(a)所示，準備N型基極層10。N型基極層10例如既可為設置於矽基板上之N型矽層，亦可為N型矽基板。
其次，於N型基極層10之表面10a側，分別注入P型雜質，例如硼(B11)及中性雜質，例如碳(C12)。此處，所謂中性雜質係指例如於N型 基極層10中電氣惰性之雜質元素。即，中性雜質係不產生電子或電洞，而為電中性之雜質元素。於N型基極層10為矽層之情形時，中性雜質例如為碳、氮、氟等。
P型雜質例如離子注入至於後續步驟(參照圖2(c))中形成之X方向上相鄰之兩個閘極電極40之中央之區域103。關於P型雜質(B11)之離子注入條件，例如注入能量為130keV，劑量為7×1014cm-2。
中性雜質例如離子注入至於後續步驟(參照圖2(c))中形成閘極電極40之區域與區域103之間之區域105。區域105較佳為形成於形成閘極電極40之附近。區域105例如形成於距後續步驟中形成之閘極溝槽41之側面為1μm之位置。區域105之X方向之寬度例如為1μm。
區域105例如形成於較區域103更深之位置。例如，若將閘極溝槽41之深度設為5.5μm，則中性雜質以其濃度分佈之峰值位於4~6μm之深度之方式進行離子注入。例如，將碳C12於注入能量為1200keV、劑量為1×1013cm-2之條件下進行離子注入。
然後，藉由對N型基極層10進行熱處理，而使P型雜質活化且擴散。熱處理例如於1150℃、750分鐘之條件下進行。藉此，如圖2(b)所示，可於N型基極層10上形成P型浮動層50。P型浮動層50之Z方向之厚度(深度)例如為11μm。
與P型浮動層50同時地，形成半導體區域60。半導體區域60係包含中性雜質、即電氣惰性之雜質之區域。半導體區域60例如形成於N型基極層10之區域40e與P型浮動層50之間，上述N型基極層10之區域40e經由後續步驟中形成之絕緣膜而與後續步驟中形成之閘極電極40之底部相接。又，半導體區域60形成於N型基極層10之區域40e之附近。半導體區域60形成於N型基極層10中或P型浮動層50中之至少任一者中。又，半導體區域60亦可跨及N型基極層10中與P型浮動層50中之兩者之區域而形成。
其次，如圖2(c)所示，於N型基極層10之表面10a側形成閘極溝槽41。閘極溝槽形成於區域105之間且介隔區域105而與區域103相鄰之區域。然後，形成覆蓋閘極溝槽41之內面之絕緣膜43。進而，形成填埋閘極溝槽41之內部之閘極電極40。絕緣膜43例如為氧化矽膜，作為閘極絕緣膜而發揮功能。閘極電極40例如為導電性之多晶矽。
如圖3(a)所示，形成P型基極層20。P型基極層20於閘極電極40之與P型浮動層50相反之側，形成於相鄰之閘極電極40之間。P型基極層20藉由將P型雜質，例如硼(B)選擇性地離子注入而形成。
如圖3(b)所示，將N型射極層30形成於P型基極層20上。N型射極層30藉由將N型雜質，例如磷(P)選擇性地離子注入而形成。然後，形成層間絕緣膜45、P型集極層70、射極電極80、及集極電極90而完成半導體裝置1。
圖5及圖6係表示比較例之半導體裝置2之模式剖面圖及表示其特性之模式圖。
如圖5所示，半導體裝置2包括P型浮動層55，且不具有半導體區域60。P型浮動層55越過閘極電極40而擴展至P型基極層20側。換言之，P型浮動層55之下表面55a越過閘極電極40而到達P型基極層20。
圖6(a)係表示半導體裝置2之閘極電極40之附近之載子之流動之模式圖。圖6(b)係表示半導體裝置2之集極-射極間之電流電壓特性之曲線圖。縱軸為集極電流IC，橫軸為集極-射極間之電壓VC。圖6(b)中所示之兩個特性表示晶圓中之不同兩點處之電流電壓特性。
如圖6(a)所示，半導體裝置2中，因P型浮動層55而電洞不會積存，電洞電流自P型浮動層55越過閘極電極40而流動至P型基極層20。因此，於P型基極層20之正下方之N型基極層10中，電洞電流密度之上升被抑制。藉此，如圖6(b)所示，電流電壓特性產生出現負阻區域ISB之所謂驟回(snapback)不良。此種特性不僅會產生於元件之整個 面，於其一部分區域中亦會產生P型浮動層55與P型基極層20相連。
例如，若欲抑制P型浮動層55之橫方向(X方向)之擴展，以使得不產生驟回不良，則有P型浮動層55之有效載子量減少之虞。具體而言，考慮有使注入P型雜質之區域103之X方向之寬度變窄，而抑制P型雜質向閘極電極40側擴展之方法，但會導致閘極電極40之附近之P型雜質之濃度下降。此種半導體裝置中，經由N型基極層10而流動之電洞電流之密度變動變大，正向電壓Vf不穩定。
相對於此，圖4(a)所示之模式圖表示半導體裝置1之閘極電極40之附近之P型載子之分佈。又，圖4(b)係表示半導體裝置1之集極-射極間之電流電壓特性之曲線圖。縱軸為集極電流IC，橫軸為集極-射極間之電壓VC。
圖4(a)中之區域50a~50d表示P型浮動層50中之雜質分佈之模擬結果。例如，區域50a中，P型雜質之濃度為1×1018cm-3左右，區域50d中，P型雜質之濃度為1×1014cm-3左右。區域50b及50c為其等中間之濃度。P型雜質之濃度沿自區域50a至區域50d之方向下降。此例中，P型浮動層50未越過閘極電極40而擴展至P型基極層20側。即，半導體裝置1中，P型雜質之擴散被半導體區域60抑制，從而P型浮動層向橫方向(X方向)之擴展被抑制。
藉此，藉由P型浮動層55而促進電洞之積存，電洞電流不會直接自P型浮動層50流動至P型基極層20。而且，電洞被效率良好地注入至相鄰之閘極電極40間之N型基極層10，使電洞電流之密度上升。藉此，如圖4(b)所示，可獲得不會產生驟回不良之良好之電流電壓特性。
本實施形態中，藉由設置半導體區域60，而可抑制P型浮動層50向閘極電極40側之擴展。藉此，可抑制驟回不良之產生，而獲得高耐壓、低損失之半導體裝置1。
進而，藉由設置半導體區域60，可靠性提高。例如，使注入P型雜質之區域103之X方向之寬度變窄而抑制P型雜質向閘極電極40側擴展，藉此抑制驟回不良之半導體裝置中，於高溫之偏壓試驗(例如，150℃下2000小時之通電試驗)中確認到電流電壓特性劣化，產生驟回不良。其原因在於，於高溫下之試驗中硼自P型浮動層向橫方向(X方向)緩緩擴散，而引發驟回不良。如上所述，先前之半導體裝置中，可知雖可改善初始特性，但可靠性仍有問題。另一方面，本實施形態中，即便於高溫下之偏壓試驗中，電流電壓特性亦不會劣化，可實現高可靠性。
又，藉由設置半導體區域60，而可增大P型浮動層50之形成條件、即離子注入條件及熱處理條件之容限。其結果為，例如可將P型浮動層50與設置於終端部之保護環同時地形成，亦可實現製造步驟之縮短及成本削減。
進而，本實施形態並不限定於上述例，亦可應用於其他器件或步驟。例如，於其他功率半導體裝置中，當為獲得高耐壓而形成較深之擴散層時，可抑制橫方向之雜質擴散之擴展。具體而言，在形成於終端部之保護環擴散層與閘極電極之間，形成包含中性雜質之半導體區域，可一面保持保護環擴散層之深度一面抑制橫方向之擴展。藉此，可縮短終端部之長度，從而可實現晶片尺寸之縮小或導通電阻之降低。
已對本發明之若干實施形態進行了說明，但該等實施形態係作為例而提出，並不意圖限定發明之範圍。該等新穎之實施形態可以其他各種形態實施，於不脫離發明之主旨之範圍內，可進行各種省略、替換、變更。該等實施形態及其變化包含於發明之範圍或主旨內，並且包含於申請專利範圍所記載之發明及其均等之範圍內。
1‧‧‧半導體裝置
10‧‧‧N型基極層
20‧‧‧P型基極層
30‧‧‧N型射極層
40‧‧‧閘極電極
40e‧‧‧介隔絕緣膜而與閘極電極之底部相接之N型基極層端
43‧‧‧絕緣膜
45‧‧‧層間絕緣膜
47‧‧‧開口
50‧‧‧P型浮動層
50e‧‧‧P型浮動層50之底部
60‧‧‧半導體區域
70‧‧‧P型集極層
80‧‧‧射極電極
90‧‧‧集極電極
d1‧‧‧距離
d2‧‧‧距離
X、Y、Z‧‧‧軸

Claims (5)

  1. 一種半導體裝置，其包括：第1導電型之第1半導體層；第2導電型之第2半導體層，其選擇性地設置於上述第1半導體層上；第1導電型之第3半導體層，其設置於上述第2半導體層上；第2導電型之第4半導體層，其選擇性地設置於上述第1半導體層上；控制電極，其自上述第3半導體層側到達上述第1半導體層中，介隔絕緣膜而與上述第2半導體層及上述第3半導體層相鄰，且位於上述第2半導體層與上述第4半導體層之間；及半導體區域，其介隔上述絕緣膜而與上述控制電極之底部相鄰，並設置於上述第1半導體層中或上述第4半導體層中之至少任一者中，且包含至少一種電氣惰性之元素。
  2. 如請求項1之半導體裝置，其中上述半導體區域包含碳、氮、氟中之至少一種元素。
  3. 如請求項1或2之半導體裝置，其進而包括：第2導電型之第5半導體層，其係設置於上述第1半導體層之與上述第2半導體層相反之側；上述第4半導體層與上述第5半導體層之距離短於上述控制電極與上述第5半導體層之距離。
  4. 如請求項1或2之半導體裝置，其包括複數個上述控制電極；上述第2半導體層及上述第3半導體層設置於上述複數個控制電極中之相鄰之兩個控制電極之間。
  5. 如請求項1或2之半導體裝置，其進而包括： 第1電極，其覆蓋上述第3半導體層、上述第4半導體層及上述控制電極，且電性連接於上述第3半導體層；及第2電極，其電性連接於上述第5半導體層；且上述第4半導體層未電性連接於上述第1電極、上述第2電極及上述控制電極中之任一者。
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