TW201515174A - 半導體裝置 - Google Patents
半導體裝置 Download PDFInfo
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- TW201515174A TW201515174A TW103121241A TW103121241A TW201515174A TW 201515174 A TW201515174 A TW 201515174A TW 103121241 A TW103121241 A TW 103121241A TW 103121241 A TW103121241 A TW 103121241A TW 201515174 A TW201515174 A TW 201515174A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
本發明係一種半導體裝置,其課題為提升加以配置於貫通電極設置範圍(或凸塊電極設置範圍)與內部電路之間的電路之面積利用效率,而實現半導體裝置之小型化。
其解決手段為半導體裝置係具備:於半導體基板上,配置成3×3之矩陣狀的9個表面微凸塊(MFB1~MFB9),和包含加以形成於半導體基板之第1及第2擴散層的電晶體(621),配置於半導體基板上之電源配線(81),第1擴散層係加以連接於表面微凸塊(MFB1),第2擴散層係加以連接於電源配線(81),電晶體(621)係加以配置於位置於X方向之一端的表面微凸塊(MFB4~MFB6)與位置於X方向之另一端的表面微凸塊(MFB7~MFB9)之間的範圍。
Description
本發明係有關半導體裝置,特別是有關具備貫通電極設置範圍(或凸塊電極設置範圍)之半導體裝置。
經由近年來的電子機器等之小型化,對於搭載於電子機器等之半導體裝置,亦強烈期望其小型化。從如此之背景,並非平面地排列半導體晶片,而3次元地層積複數之半導體晶片之技術則倍受注目。其中,使用貫通半導體晶片之貫通電極(Through Substrate Via)而連接晶片間之技術係因無須為了引繞接合導線之範圍之故,作為可降低半導體封裝之安裝面積的技術而被加以期待(例如,參照專利文獻2)。
另外,一般而言,對於半導體晶片,係加以設置有為了防止經由通過外部端子所輸入之靜電而加以破壞內部電路之靜電放電保護電路。如此之靜電放電保護電路係例如,如專利文獻1所示地,亦加以設置於具有上述貫通電極之半導體晶片。此情況,靜電放電保護電路係加以配置於貫通電極設置範圍與內部電路之間。然而,貫通
電極設置範圍係亦為與貫通電極同時,或取代貫通電極而加以設置之凸塊電極的設置範圍之故,靜電放電保護電路係亦可說是加以配置於凸塊電極設置範圍與內部電路之間者。
[專利文獻1]日本特開2010-135192號公報
[專利文獻2]日本特開2012-243253號公報
但在記載於上述專利文獻1之配置中,於貫通電極設置範圍(或者凸塊電極設置範圍)與內部電路之間,有著靜電放電保護電路之故,而面積的利用效率為差,在小型化的面上有著困難。此係對於配置於貫通電極設置範圍(或者凸塊電極設置範圍)與內部電路之間的其他電路,例如為了輸出讀取資料的輸出電路等,亦為共通的課題。
經由本發明之一側面的半導體裝置係其特徵為具備:半導體基板,和形成於前述半導體基板上,沿著第1方向而以第1間距加以配置之第1乃至第3凸塊電
極,和形成於前述半導體基板上,沿著前述第1方向而以前述第1間距加以配置之第4乃至第6凸塊電極,和形成於前述半導體基板上,沿著前述第1方向而以前述第1間距加以配置之第7乃至第9凸塊電極,和包含各形成於前述半導體基板之第1及第2擴散層之第1電晶體,和配置於前述半導體基板上之電源線,前述第1,第4,第7凸塊電極係沿著交叉於前述第1方向之第2方向,前述第1凸塊電極則呈位置於前述第4及第7凸塊電極之間,以第2間距加以配置,前述第2,第5,第8凸塊電極係沿著前述第2方向,前述第2凸塊電極則呈位置於前述第5及第8凸塊電極之間,以前述第2間距加以配置,前述第3,第6,第9凸塊電極係沿著前述第2方向,前述第3凸塊電極則呈位置於前述第6及第9凸塊電極之間,以前述第2間距加以配置,前述第1擴散層係連接於前述第1凸塊電極,前述第2擴散層係連接於前述電源線,前述第1電晶體係配置於前述第4乃至第6凸塊電極與前述第7乃至第9凸塊電極之間的範圍者。
如根據本發明,於第4乃至第6凸塊電極與第7乃至第9凸塊電極之間的範圍,配置有第1電晶體。即,因於凸塊電極設置範圍之內部,加以配置有第1電晶體之故,無須將為了設置第1電晶體之範圍,設置於凸塊電極設置範圍外。隨之,成為可提升面積的利用效率,而
實現半導體裝置之小型化者。
2,3,60,90‧‧‧內部電路
10,10a‧‧‧半導體裝置
10A,10aA‧‧‧半製品
21~24‧‧‧記憶體晶片
30‧‧‧控制晶片
40‧‧‧電路基板
41‧‧‧基板電極
42‧‧‧外部端子
43‧‧‧封閉樹脂
50a,50b,52a,52b,51,53,54,55a,55b,56,57a,57b,58,63,64,71,73,75,80,84,85‧‧‧配線
81,82‧‧‧電源配線
61‧‧‧靜電放電保護電路
62,621~629,94,95‧‧‧電晶體
62D1,62D2,94D1,94D2,96,95D1,95D2,97‧‧‧擴散層
62G,94G‧‧‧閘極電極
62I,94I‧‧‧閘極絕緣膜
72,74,76,77,TH1~TH6,TH11~TH14,TH16~TH19,TH20a,TH20b,TH21,TH22a,TH22b,TH23,TH25a,TH25b,TH26,TH27a,TH27b,TH28‧‧‧貫穿孔導體
91‧‧‧NOR電路
92‧‧‧NAND電路
93‧‧‧輸出電路
BA‧‧‧凸塊電極設置範圍
CBB‧‧‧背面微凸塊
CFB‧‧‧表面微凸塊
ChA~ChD‧‧‧通道
I1~I5‧‧‧絕緣層
IS‧‧‧元件分離用絕緣膜
K1~K4‧‧‧活性範圍
MBB‧‧‧背面微凸塊
MFB,MFBa~MFBd,MFB1~MFB9‧‧‧表面微凸塊
SS‧‧‧半導體基板
TP‧‧‧測試墊
TSV,TSV1,TSV2‧‧‧貫通電極
圖1(a)係為了說明經由本發明之理想的第1實施形態之半導體裝置10的半製品10A之構造的模式性的剖面圖,(b)係為了說明半導體裝置10之構造的模式性的剖面圖。
圖2係圖1(a)所示之記憶體晶片21的主面21F之平面圖。
圖3(a),(b)係各為了說明貫通電極TSV1,TSV2之連接狀態的模式圖。
圖4係顯示內藏於圖1(b)所示之記憶體晶片21~24之靜電放電保護電路61的構成的圖。
圖5係圖1(b)所示之記憶體晶片21之模式性的剖面圖,對應於圖7之C-C線。
圖6(a)係關於圖4所示之靜電放電保護電路61,顯示埋入於圖5所示之半導體基板SS之主面SSa的構成之平面圖,(b)係將形成於主面SSa之構成,追記於(a)之平面圖,(c)係將形成於圖5所示之絕緣層I1上面之構成,追記於(b)之平面圖。
圖7係擴大顯示圖2所示之範圍B之平面圖。
圖8係從圖7之平面圖,拔出形成於圖5所示之絕緣層I1上面之構成而顯示之平面圖。
圖9係於圖8之平面圖,追記形成於圖5所示之絕緣層I2上面之構成之平面圖。
圖10係於圖9之平面圖,追記形成於圖5所示之絕緣層I3上面之構成之平面圖。
圖11係顯示內藏於包含在經由本發明之理想的第2實施形態之半導體裝置10之記憶體晶片21~24的輸出電路93及其周邊電路的構成的圖。
圖12係包含在經由本發明之理想的第2實施形態之半導體裝置10之記憶體晶片21之模式性的剖面圖,對應於圖18之E-E線。
圖13係顯示在經由本發明之理想的第2實施形態之半導體裝置10之表面微凸塊MFB附近之構成之中,埋入於圖12所示之半導體基板SS之主面Ssa的構成之平面圖。
圖14係於圖13之平面圖,追記形成於圖12所示之半導體基板SS之主面SSa之構成的平面圖。
圖15係於圖14之平面圖,追記形成於圖12所示之絕緣層I1上面之構成之平面圖。
圖16係對應於圖2所示之範圍B,擴大顯示經由本發明之理想的第2實施形態之半導體裝置10之範圍的平面圖。
圖17係於圖16之平面圖,追記形成於圖12所示之絕緣層I2上面之構成之平面圖。
圖18係於圖17之平面圖,追記形成於圖12所示之
絕緣層I3上面之構成之平面圖。
圖19(a)係為了說明經由本發明之理想的實施形態的變形例之半導體裝置10a的半製品10aA之構造的模式性的剖面圖,(b)係為了說明半導體裝置10a之構造的模式性的剖面圖。
以下,參照附加圖面的同時,對於本發明之理想的實施形態加以詳細說明。
如圖1(b)所示,有關本發明之第1實施形態之半導體裝置10係具有:層積有1片之控制晶片30,和4片的記憶體晶片21~24之構成。記憶體晶片21~24均為所謂寬IO型之DRAM(Dynamic Random Access Memory),各具有主面21F~24F與背面21B~24B。然而,主面21F~24F係加以形成有電晶體等之各種電路元件(不圖示)側的面。記憶體晶片21~24係將主面21F~24F朝向於控制晶片30的狀態,即以面朝下方式,加以層積於控制晶片30上。
記憶體晶片21~23係具有相互相同之構成。當著眼於記憶體晶片21而說明時,對於記憶體晶片21之主面21F,係加以設置有複數之表面微凸塊MFB(凸塊電極)及複數之測試墊TP。另外,對於記憶體晶片21之背面21B,係加以設置有複數之背面微凸塊MBB。詳細係後述,但表面微凸塊MFB與背面微凸塊MBB係經由貫通含
於記憶體晶片21之半導體基板(在圖1(b)中係未明示)之貫通電極TSV,而加以相互連接。
背面微凸塊MBB係與鄰接於背面側之其他的記憶體晶片的表面微凸塊MFB加以接合,經由此,加以確保鄰接之記憶體晶片間的電性的連接。位置於最下層之記憶體晶片21之表面微凸塊MFB係加以接合於控制晶片30之背面微凸塊CBB(後述)。在控制晶片30與各記憶體晶片21~24之間中,通過此等接合而將各種信號加以收送信。
位置於最上層之記憶體晶片24係在未具有背面微凸塊MBB及貫通電極TSV的點,與記憶體晶片21~23不同,而在其他的點係具有與記憶體晶片21~23同樣的構成。以下,對於相異點加以詳細說明。
如上述,記憶體晶片21~24係各以面朝下方式而加以層積於控制晶片30上。隨之,貫通電極TSV及背面微凸塊MBB係專門為了中繼有關更上層之記憶體晶片之信號所使用,對於位置於最上層之記憶體晶片24,係無須設置貫通電極TSV及背面微凸塊MBB。在另一方面,由作為呈未設置貫通電極TSV者,成為比較於其他的記憶體晶片21~23而可加厚記憶體晶片24者。如加厚記憶體晶片24,在半導體裝置10之製造時,因可抑制經由熱應力(主要在層積記憶體晶片21~24時產生的熱應力)之晶片的變形之故,在經由本實施形態之半導體裝置10中,雖在記憶體晶片21~23與記憶體晶片24而對於
晶片製造工程產生有不同,但如上述,對於記憶體晶片24係作為未設置背面微凸塊MBB及貫通電極TSV者。但作為記憶體晶片24,與記憶體晶片21~23同樣地,亦可使用具有貫通電極TSV及背面微凸塊MBB之晶片者。
控制晶片30係控制記憶體晶片21~24之動作的半導體晶片(SOC),以面朝下方式加以搭載於電路基板40上。也就是,控制晶片30係形成有各種電路元件側的面之主面30F則朝向電路基板40側,背面30B則呈朝向記憶體晶片21~24側地,加以搭載於電路基板40上。
對於控制晶片30之主面30F係加以形成有複數之表面微凸塊CFB,而對於控制晶片30之背面30B係加以形成有複數之背面微凸塊CBB。表面微凸塊CFB係加以接合於設置於電路基板40之基板電極41。另一方面,背面微凸塊CBB係如上述,加以接合於設置於最下層之記憶體晶片21之表面微凸塊MFB。設置於控制晶片30之內部電路係通過未圖示之配線而加以連接於表面微凸塊CFB之同時,藉由通過控制晶片30而加以設置之貫通電極TSV,亦加以連接於背面微凸塊CBB。
電路基板40係具有:於上面加以設置有基板電極41,而於下面加以設置有外部端子42之構造。對於電路基板40上面係如上述,加以搭載有控制晶片30。基板電極41與外部端子42係藉由貫通電路基板40之未圖示之貫穿孔導體,而加以相互加以連接。另外,對於基板電極41之上面,係加以設置有被覆記憶體晶片21~24及
控制晶片30之封閉樹脂43。
外部端子42係控制晶片30,但與在未圖示之其他的裝置等之間,輸出入各種信號(位址信號,指令信號,時脈信號,資料等)時加以使用。具體而言,當將半導體裝置10安裝於母基板時,加以連接於非揮發性記憶體,感測器等之各種類比晶片,及各種輸出入介面電路。控制晶片30係將因應來自此等其他的裝置之各種信號而以本身生成之資料信號,藉由背面微凸塊CBB及表面微凸塊MFB等而記憶於記憶體晶片21~24。另外,控制晶片30係從記憶體晶片21~24,因應藉由背面微凸塊CBB及表面微凸塊MFB等所供給之資料,生成供給至上述其他的裝置等之信號。
在半導體裝置10之製造工程中,準備圖1(a)所示之半製品10A,作為呈將此等連接於控制晶片30及電路基板40者為最佳。半製品10A係如圖1(a)所示,自記憶體晶片21~24,和被覆除了記憶體晶片21之主面21F之各面的封閉樹脂43而加以構成。但半製品10A之利用係並非必須,例如,於電路基板40上,搭載控制晶片30及記憶體晶片21~24之後,作為經由封閉樹脂43而封閉此等之記憶體晶片21~24,30者亦可。使用半製品10A之情況,可經由規範或用途而改變連接端之控制晶片30之故,而成為可提高泛用性者。
對於各記憶體晶片21~24之主面21F~24F,係如圖2所例示地,於X方向及Y方向,加以設置有配
置成矩陣狀之4個通道ChA~ChD。各通道ChA~ChD係各自可作為單獨之DRAM而動作之電路元件,隨之,記憶體晶片21~24係各自具有將4個獨立之DRAM作為1晶片化之構成。
如上述,對於主面21F~24F係加以設置有複數之表面微凸塊MFB。此等表面微凸塊MFB係各對應於通道ChA~ChD之任一,在圖2中,將對應於通道ChA~ChD之表面微凸塊MFB,各表記為表面微凸塊MFBa~MFBd。分配於各通道ChA~ChD之資料用之表面微凸塊MFB的數量係各例如為非常多之128個,另外,電源用之表面微凸塊MFB等,亦從對於各通道需要多數之情況,於各通道ChA~ChD,例如加以設置有300個程度之表面微凸塊MFB。因此,在晶片全體中,成為使用有超過1000個之表面微凸塊MFB之情況。
對於此等表面微凸塊MFB之中,包含有稱作直接存取端子之測試用的端子。但從表面微凸塊MFB之尺寸係非常微小之情況,使測試器之探針,接觸於直接存取端子之情況係為困難。因此,對於各直接存取端子,係各分配有為了使測試器之探針接觸的測試墊TP。測試墊TP係具有較表面微凸塊MFB為大之平面尺寸,經由此,作為可使測試器之探針接觸者。對於在圖1(a)的階段(層積前)或晶圓狀態之階段,進行記憶體晶片21~24之動作測試時,通過測試墊TP,在測試器與記憶體晶片21~24之間,進行各種信號的收送信。另一方面,對於在圖1(b)
的階段(層積後),進行記憶體晶片21~24之動作測試時,經由控制晶片30,在測試器與記憶體晶片21~24之間,進行各種信號的收送信。
形成於記憶體晶片21~23之貫通電極TSV係經由與內部電路及鄰接之其他的記憶體晶片之貫通電極TSV的連接之形態,可分類成幾個種類。圖3(a)(b)所示之貫通電極TSV1,TSV2係各為貫通電極TSV之種類的一例。
圖3(a)所示之貫通電極TSV1係在自層積方向而視之平面視,即從圖1所示之箭頭A而示之情況,與設置於相同平面位置之其他層之貫通電極TSV1作為短路。也就是如圖3(a)所示,在平面視設置於相同位置之上下的貫通電極TSV1則被短路,經由此等貫通電極TSV1而加以構成1條信號通道。此信號通道係加以連接於各記憶體晶片21~24之內部電路2。隨之,對於此信號通道而言,自控制晶片30所供給之輸入信號(指令信號,位址信號,時脈信號,寫入資料等)係共通地加以輸入至各記憶體晶片21~24之內部電路2。另外,從各記憶體晶片21~24之內部電路2供給至此信號通道之輸出信號(讀取資料等)係作為線或,而加以輸出至控制晶片30。
另一方面,圖3(b)所示之貫通電極TSV2係與以平面視加以設置於不同位置之其他的記憶體晶片之貫通電極TSV2加以短路。當具體說明時,對於各記憶體晶片21~23係加以設置以平面視各加以設置4個貫通電極
TSV2於相同位置,加以設置於下層之記憶體晶片之第N(N=1~3)之貫通電極TSV2係加以連接於加以設置於上層之記憶體晶片之第N+1之貫通電極TSV2。在加以設置於下層之記憶體晶片之第4之貫通電極TSV2(在圖3(b)中最右側之貫通電極TSV2),係加以連接於加以設置於上層之記憶體晶片之第1之貫通電極TSV2(在圖3(b)中最左側之貫通電極TSV2)。經由如此之循環的連接,形成有4個獨立之信號通道。
並且,此等4個貫通電極TSV2之中,以平面視加以設置於特定位置之貫通電極TSV2(在圖3(b)中最左側之貫通電極TSV2)係加以連接於該記憶體晶片21~23內之內部電路3。另外,含於最上層之記憶體晶片24之內部電路3,係加以連接於含於記憶體晶片23之最右側之貫通電極TSV2。
經由有關之構成,圖3(b)所示之信號S1~S4係成為各對於記憶體晶片21~24之內部電路3而言,選擇性地加以輸入者。作為如此之信號,可舉出晶片選擇信號CS或時脈賦能信號CLK等。
那麼,記憶體晶片21~24係於各內部,具有圖4所例示之靜電放電保護電路61。靜電放電保護電路61係為擔負將通過表面微凸塊MFB而加以供給至晶片內之靜電,引導至電源配線之作用的構成,加以設置於各表面微凸塊MFB。在本實施形態中,係由將如此之靜電放電保護電路61,配置於凸塊電極設置範圍內者,實現記
憶體晶片21~24之小型化。以下,著眼於記憶體晶片21,詳細說明有關靜電放電保護電路61之構成,對於記憶體晶片22~24亦為同樣。
靜電放電保護電路61係如圖4所示,經由加以二極體連接之N通道型之MOS電晶體62(第1電晶體)而加以構成。電晶體62之一端係加以連接於連接內部電路60,和表面微凸塊MFB之記憶體晶片側端部的節點n之間的配線80。另一方面,電晶體62之另一端係加以連接於接地電位VSS之所供給之電源配線81(第1電源線)。電晶體62之順方向係從電源配線81朝向於配線80之方向。通常,配線80之電位位準係因位與電源配線81之電位位準均等或稍微高之程度之故,未有通過電晶體62而流動有電流之情況。另一方面,對於因靜電放電等引起而對於配線80供給有大電流之情況,係配線80之電位位準則比較於電源配線81之電位位準而大幅度變高之故,於電晶體62流動有擊穿電流。經由此,因成為可將供給至配線80之大電流引導至電源配線81之故,如根據靜電放電保護電路61,可實現從靜電放電保護內部電路60者。
然而,在圖4中,較節點n位於上側之構成(貫通電極TSV及背面微凸塊MBB)係為未加以設置於記憶體晶片24之構成。在其他的點中,記憶體晶片24亦具有與記憶體晶片21同樣的構成。
經由本實施形態之記憶體晶片21係如圖5所
示,具有半導體基板SS,和依序加以層積於其主面SSa之絕緣層I1~I4而加以構成。半導體基板SS係為P通道型之矽基板。對於主面SSa係埋入有元件分離用絕緣膜IS,經由此而對於主面SSa,係加以區劃有形成有電晶體62之活性範圍K1,和形成有貫通電極TSV之活性範圍K2。活性範圍K1,K2係均為P通道型的範圍。
貫通電極TSV係如圖5所示,貫通半導體基板SS及絕緣層I1而加以設置。對於貫通電極TSV之半導體基板SS的背面側,即記憶體晶片21之背面21B側的端部,係加以設置有背面微凸塊MBB。對於各貫通電極TSV及背面微凸塊MBB與半導體基板SS之間,係加以配置有絕緣膜70,經由此,確保有各貫通電極TSV及背面微凸塊MBB與半導體基板SS之絕緣。
貫通電極TSV之主面SSa側的端部係加以連接於形成於絕緣層I1之表面的配線71。配線71係加以設置於各貫通電極TSV,各藉由貫通絕緣層I2之貫穿孔導體72,加以連接於形成於絕緣層I2表面之配線73。配線73亦加以設置於各貫通電極TSV,各藉由貫通絕緣層I3之複數之貫穿孔導體74,加以連接於形成於絕緣層I3表面之配線75。配線75亦加以設置於各貫通電極TSV,各藉由貫通絕緣層I4之複數之貫穿孔導體76,加以連接於絕緣層I4表面,即形成於記憶體晶片21之主面21F之表面微凸塊MFB。如此作為,背面微凸塊MBB與表面微凸塊MFB,係藉由貫通電極TSV而加以電性連接。
然而,圖5所示的例係貫通電極TSV為圖3(a)所示之貫通電極TSV1之情況的例,但對於其他種類之貫通電極TSV,基本的構造係亦為相同。關於圖3(b)所示之貫通電極TSV2而言,經由延設配線71,73之任一或雙方,實現有如圖3(b)所示之連接。
另外,對於圖5係顯示記憶體晶片21的例,但在未具有貫通電極TSV之記憶體晶片24中,係省略從貫穿孔導體72至背面微凸塊MBB為止之構成。此情況,亦無須設置活性範圍K2,隨之,於平面而視,與表面微凸塊MFB重疊之範圍,成為可配置包含電晶體62之各種的電晶體者。
形成有電晶體62之活性範圍K1係如圖5所示,加以配置於形成有貫通電極TSV之活性範圍K2之間。以下,對於電晶體62之構造,加上於圖5,亦參照圖6(a)~(c)同時,加以詳細說明。
對於活性範圍K1之內側係如圖6(a)所示,加以形成有構成各電晶體62之源極/汲極之一方及另一方的擴散層62D1,62D2(第1及第2擴散層)。擴散層62D1,62D2,係經由將N通道型的不純物離子注入至半導體基板SS而加以形成之N通道型之不純物擴散層。擴散層62D2係各一個加以設置於擴散層62D1之兩側。對於擴散層62D1與擴散層62D2之間(2處),係露出有半導體基板SS之表面,對於此露出部分之上面,係如圖6(b)所示,藉由閘極絕緣膜62I(參照圖5),加以形成有電晶體62之
閘極電極62G(第1閘極電極)。閘極電極62G係加以延設至活性範圍K1之外側為止。
對於電晶體62上方係如圖6(c)所示,更加以形成有配線63,64。配線63,64係同時加以形成於圖5所示之絕緣層I1上面的配線。配線63係如從圖6(b)(c)理解到,平面而視,呈重疊於擴散層62D2,和閘極電極62G之中加以形成於活性範圍K1外側之部分地加以延設。並且,經由貫通絕緣層I1之貫穿孔導體TH1而與擴散層62D2加以電性連接之同時,經由貫通絕緣層I1之貫穿孔導體TH2而與閘極電極62G加以電性連接。隨之,擴散層62D2與閘極電極62G係藉由配線63而加以短路,經由此,實現圖4所示之二極體連接。另一方面,配線64係平面而視加以延設於與擴散層62D1重疊之位置,經由貫通絕緣層I1之貫穿孔導體TH3,而與擴散層62D1加以連接。
接著,對於表面微凸塊MFB與電晶體62之平面的位置關係加以說明。以下,著眼於圖2所示之範圍B而加以說明,但對於其他的範圍亦為同樣。
圖7~圖10係將配置於範圍B內之構成,在從主面21F側的視點,透過性地顯示的構成。如圖7所示,形成於主面21F之複數之表面微凸塊MFB係於鄰接於通道ChA而加以配置之凸塊電極設置範圍BA,配置成矩陣狀。表面微凸塊MFB間之Y方向的間距(第1間距)及X方向之間距(第1間距)係各呈從圖8理解到為P1,
P2。以下,著眼於同圖所示之9個表面微凸塊MFB1~MFB9(第1乃至第9之凸塊電極),進行說明。
如圖7所示,表面微凸塊MFB1~MFB9係加以配置成3×3之矩陣狀。對於3×3之矩陣之中央,係加以配置有表面微凸塊MFB1。對於表面微凸塊MFB1之Y方向(第1方向)的兩側,係加以配置有表面微凸塊MFB2,MFB3。隨之,表面微凸塊MFB1~MFB3係沿著Y方向而配置成一列。對於表面微凸塊MFB1之X方向(交叉於第1方向之第2方向)的兩側,係加以配置有表面微凸塊MFB4,MFB7。隨之,表面微凸塊MFB1,MFB4,MFB7係沿著X方向而配置成一列。
對於表面微凸塊MFB2之X方向的兩側,係加以配置有表面微凸塊MFB5,MFB8。另外,對於表面微凸塊MFB3之X方向的兩側,係加以配置有表面微凸塊MFB6,MFB9。表面微凸塊MFB5,MFB6係與對於表面微凸塊MFB4同時,沿著Y方向而配置成一列。另外,表面微凸塊MFB8,MFB9係與對於表面微凸塊MFB7同時,沿著Y方向而配置成一列。
呈在上方亦接觸地,電晶體62係加以設置於各表面微凸塊MFB。對於圖7係雖無電晶體62本身之描繪,但如從圖6(c)理解到地,電晶體62係存在於配線63,64之正下方的範圍。在圖7中,將對應於各表面微凸塊MFB1~MFB9之電晶體62,作為電晶體621~629(第1乃至第9之電晶體),僅顯示符號。
如從圖8所理解地,各電晶體62係各從對應之表面微凸塊MFB之平面的中心而視,於Y方向遠離L1(第1距離),且於X方向遠離L2(第2距離)之位置,呈位置著平面的中心地加以配置。但,L1係較P1為小,L2係較P2為小。其結果,例如配置有電晶體621之範圍係如圖8所示,成為表面微凸塊MFB4~MFB6與表面微凸塊MFB7~MFB9之間的範圍。
配線64係如從圖8及圖9所理解地,藉由貫穿孔導體TH4,加以連接於亦於圖4所示之配線80。貫穿孔導體TH4係貫通圖5所示之絕緣層I2之柱狀的導體。配線80係加以設置於各表面微凸塊MFB,各加以形成於圖5所示之絕緣層I2之上面。如圖4所示,配線80之一端係加以連接於通道ChA內之內部電路60,另一端係加以連接於連接於對應之表面微凸塊MFB之配線73。如圖5所示,配線73係藉由貫通絕緣層I3之貫穿孔導體74,而加以連接於對應之表面微凸塊MFB。隨之,配線64,與對應之表面微凸塊MFB係藉由配線80,73及貫穿孔導體74,加以相互連接。另外,配線64係如參照圖6(b)(c)而說明地,藉由貫穿孔導體TH3而加以連接於電晶體62之擴散層62D1。隨之,擴散層62D1係與對應之表面微凸塊MFB加以電性連接。
配線63係如從圖8乃至圖10所理解地,貫穿孔導體TH5,電源配線82,及貫穿孔導體TH6,而加以連接於電源配線81。貫穿孔導體TH5,TH6係各為貫
通圖5所示之絕緣層I2,I3之柱狀的導體,電源配線82係加以形成於絕緣層I2之上面的配線。電源配線81係如圖4所示,加以供給接地電位VSS之電源配線,加以形成於圖5所示之絕緣層I3之上面。另外,配線63係如參照圖6(b)(c)而說明地,藉由貫穿孔導體TH1,TH2而加以連接於電晶體62之擴散層62D2及閘極電極62G。隨之,擴散層62D2及閘極電極62G係與電源配線81加以電性連接。
將以上的連接關係,關於圖7所示之電晶體62k(k係1至9之整數)而說明時,各電晶體62k之擴散層62D1(第2k-1之擴散層)係各加以連接於對應之表面微凸塊MFBk。表面微凸塊MFBk係各加以連接於外部端子42之同時,通過貫通電極TSV(第k之貫通電極),加以連接於設置於更上層之記憶體晶片之表面微凸塊MFB。另外,各電晶體62k之擴散層62D2(第2k之擴散層)及閘極電極62G(第k之閘極電極)係加以共通地連接於電源配線81。
如以上說明,如根據經由本實施形態之半導體裝置10,成為可將圖4所示之各表面微凸塊MFB的靜電放電保護電路61(電晶體62),設置於凸塊電極設置範圍BA內者。隨之,因無需將為了設置靜電放電保護電路61之範圍,設置於凸塊電極設置範圍BA外之故,成為可提升面積的利用效率,而實現半導體裝置之小型化者。
接著,對於經由本發明之第2實施形態之半
導體裝置10而加以說明。經由本實施形態之半導體裝置10係在取代靜電放電保護電路61,而將讀取資料的輸出電路配置於凸塊電極設置範圍BA內的點,與經由第1實施形態之半導體裝置10不同。在其他的點中,因與經由第1實施形態之半導體裝置10同樣之故,在以下中係著眼於不同點而加以說明。在以下中,與第1實施形態同樣,著眼於記憶體晶片21而進行說明,但對於記憶體晶片22~24亦為同樣。
讀取資料之輸出電路93係如圖11所示,經由N通道型(第1導電型)之MOS電晶體94(第1電晶體),和P通道型(第2導電型)之MOS電晶體95(第2電晶體)加以構成。電晶體94,95係加以串聯連接於接地電路VSS之所供給之電源配線81(第1電源線),和電源電位VDD之所供給之電源配線82(第2電源線)之間。電晶體94,95之連接點係構成輸出電路93之輸出端,加以連接於表面微凸塊MFB之記憶體晶片側端部的節點n。節點n係藉由配線83而亦加以連接於內部電路90之輸入端。另外,侷限於記憶體晶片21~23之節點n,如圖11所示,亦加以連接於貫通電極TSV。
電晶體94之閘極電極(第1閘極電極)係構成輸出電路93之一方輸入端,加以連接於含於內部電路90之NOR電路91之輸出端。另外,電晶體95之閘極電極(第2閘極電極)係構成輸出電路93之另一方輸入端,加以連接於含於內部電路90之NAND電路92之輸出端。對
於各電晶體94,95之閘極電極,係各從NOR電路91及NAND電路92,加以供給顯示應通過對應之表面微凸塊MFB(第1凸塊電極)所輸出之讀取資料RD(輸出資料)的電位。
當具體說明時,讀取資料RD係從未圖示之讀取關連電路,加以供給至各NOR電路91及NAND電路92之一方輸入端。此讀取關連電路係對於其他亦生成控制信號S,對於各NOR電路91之另一方輸入端子係加以輸入有控制信號S之反轉信號,而對於NAND電路92之另一方輸入端子係加以輸入有控制信號S。控制信號S係在未輸出讀取資料RD時而為加以活性化為低位準之低活性之信號。控制信號S為低位準之情況,NOR電路91及NAND電路92之輸出則因各加以固定為低位準及高位準之故,電晶體94,95係同時成為關閉。隨之,輸出電路93係成為高阻抗狀態。另一方面,對於控制信號S為高位準之情況,於輸出電路93之輸出端,出現有對應於讀取資料RD之電位位準的電位。具體而言,讀取資料RD為高位準之情況,經由電晶體95成為開啟之時,輸出電路93之輸出端的電位位準係成為電源電位VDD,而讀取資料RD為低位準之情況,經由電晶體94成為開啟之時,輸出電路93之輸出端的電位位準係成為接地電位VSS。如此作為所得到之輸出電路93之輸出係作為記憶體晶片21的輸出資料,經由表面微凸塊MFB而從外部端子42加以輸出。
然而,連接有輸出電路93之表面微凸塊MFB及外部端子42係亦加以使用於寫入資料WD的輸入。寫入資料WD係在從外部的控制器加以供給至外部端子42之後,經由表面微凸塊MFB及配線83,而加以供給至內部電路90。
經由本實施形態之記憶體晶片21係如圖12所示,具有半導體基板SS,和依序加以層積於其主面SSa之絕緣層I1~I5而加以構成。絕緣層I5係加以設置於絕緣層I1與半導體基板SS之間。基本的層構造係與經由第1實施形態之記憶體晶片21同樣,但絕緣層則在成為5層構造的點(經由第1實施形態之記憶體晶片21係4層構造),與經由第1實施形態之記憶體晶片21不同。但在經由第1實施形態之記憶體晶片21中,亦設置絕緣層I5而作為5層構造亦可。
對於半導體基板SS之主面SSa係經由埋入至主面SSa之元件分離用絕緣膜IS,區劃有形成有電晶體94之活性範圍K3(第1活性範圍),和形成有電晶體95之活性範圍K4(第2活性範圍),和形成有貫通電極TSV之活性範圍K2。活性範圍K2,K3係P通道型之範圍,而活性範圍K4係經由離子注入N通道型之不純物於P通道型之矽基板的半導體基板SS而加以形成之N通道型之範圍(N阱型)。
有關貫通電極TSV之構成係與參照圖5所說明之構成做比較時,關連於絕緣層I5之部分則不同。以
下,對於不同點加以說明時,貫通電極TSV之主面SSa側的端部係加以連接於形成於絕緣層I1之表面的配線54。配線54各藉由貫通絕緣層I5之複數之貫穿孔導體77,加以連接於形成於絕緣層I5表面之配線71。配線71係如參照圖5所說明地,藉由貫穿孔導體72,74等而加以連接於表面微凸塊MFB。
活性範圍K3,K4係如圖13所示,各夾持活性範圍K2而加以設置於X方向之一方側與另一方側。然而,以圖13~圖18所示之一點虛線D所區隔之範圍係顯示對應於1個表面微凸塊MFB之範圍。活性範圍K3,K4係各具有長於Y方向,且Y方向之兩端部則朝向活性範圍K2側而膨脹之形狀。採用如此之形狀的情況係為了確保活性範圍K3,K4與活性範圍K2之間的距離之另一方面,儘可能確保寬闊活性範圍K3,K4之面積。
對於活性範圍K3之內側,係各加以形成有複數之擴散層94D1,94D2,96。擴散層94D1,94D2,96係均經由將N通道型的不純物離子注入至半導體基板SS而加以形成之N通道型之不純物擴散層。擴散層94D1,94D2係各構成電晶體94之源極/汲極的一方及另一方。另一方面,擴散層96係為了供給接地電位VSS於活性範圍K3而加以設置之構成。
同樣地,對於活性範圍K4之內側係如圖13所示,各加以形成有複數之擴散層95D1,95D2,97。擴散層95D1,95D2,97係均經由將P通道型的不純物離子
注入至N阱型而加以形成之P通道型之不純物擴散層。擴散層95D1,95D2係各構成電晶體95之源極/汲極的一方及另一方。另一方面,擴散層97係為了供給電源電位VDD於活性範圍K4而加以設置之構成。
擴散層94D1,94D2,96,95D1,95D2,97係各如圖13所示,於X方向作為細長之長方形。擴散層96係各1個加以設置於活性範圍K3之兩端。另一方面,擴散層94D1,94D2(第1及第2擴散層)係將擴散層94D2作為兩端,於Y方向加以交互地複數個配置。同樣地,擴散層97係各1個加以設置於活性範圍K4之兩端。另一方面,擴散層95D1,95D2(第3及第4擴散層)係將擴散層95D2作為兩端,於Y方向加以交互地複數個配置。
對於活性範圍K3之上方,係如圖14所示,藉由閘極絕緣膜94I(參照圖12)而加以配置有梳形之閘極電極94G。此閘極電極94G係構成電晶體94之閘極電極(第1閘極電極)。對於擴散層94D1與擴散層94D2之間係露出有半導體基板SS之表面,閘極電極94G之中相當於梳齒之部分,係呈被覆此露出部分地加以配置。閘極電極94G之中相當於梳軸之部分係加以配置於活性範圍K3與活性範圍K2之間。同樣地,對於活性範圍K4之上方係加以配置有梳形之閘極電極95G。此閘極電極95G係構成電晶體95之閘極電極(第2閘極電極)。對於擴散層95D1與擴散層95D2之間係露出有半導體基板SS之表面,閘極電極95G之中相當於梳齒之部分,係呈被覆此露出部分
地加以配置。閘極電極95G之中相當於梳軸之部分係加以配置於活性範圍K4與活性範圍K2之間。
閘極電極94G係藉由貫通圖12所示之絕緣層I1之貫穿孔導體TH13,如圖15所示。各加以連接於形成在絕緣層I1上面之配線50a,50b。配線50a,50b係各加以設置於閘極電極94G之Y方向的一端及另一端。另外,配線50a,50b係各藉由貫通絕緣層I5之貫穿孔導體TH20a,TH20b而加以連接於形成在絕緣層I5上面之配線55a,55b(圖16),更且此等配線55a,55b係各藉由各貫通絕緣層I2之貫穿孔導體TH25a,TH25b而加以連接於形成在絕緣層I2上面之配線84(圖17)。配線84係如圖11所示,加以連接於內部電路90內之NOR電路91的輸出之配線。隨之,對於閘極電極94G係加以供給NOR電路91之輸出。
閘極電極95G係藉由貫通圖12所示之絕緣層I1之貫穿孔導體TH18,如圖15所示。各加以連接於形成在絕緣層I1上面之配線52a,52b。配線52a,52b係各加以設置於閘極電極95G之Y方向的一端及另一端。配線52a,52b係藉由貫通絕緣層I5之貫穿孔導體TH22a,TH22b而加以連接於形成在絕緣層I5上面之配線57a,57b(圖16),更且此等配線57a,57b係各藉由各貫通絕緣層I2之貫穿孔導體TH27a,TH27b而加以連接於形成在絕緣層I2上面之配線85(圖17)。配線85係如圖11所示,加以連接於內部電路90內之NAND電路92的輸出之
配線。隨之,對於閘極電極95G係加以供給NAND電路92之輸出。
對於活性範圍K3上方係如圖15所示,更加以配置有配線51,54。配線54係亦加以配置於活性範圍K2,K4之上方。對於活性範圍K4上方,係亦加以配置有配線53。
配線51係各藉由圖12所示之貫通絕緣層I1之貫穿孔導體TH11,TH14而加以連接於擴散層94D2,96(圖15)之同時,藉由貫通絕緣層I5之貫穿孔導體TH21,而加以連接於形成在絕緣層I5上面的配線56(圖16)。配線56係更藉由貫通絕緣層I2之貫穿孔導體TH26,而加以連接於形成在絕緣層I2上面的電源配線81(圖17)。對於電源配線81,係如圖11所示,加以供給有接地電位VSS。隨之,對於擴散層94D2,96,係成為加以供給有接地電位VSS者。
配線53係各藉由圖12所示之貫通絕緣層I1之貫穿孔導體TH16,TH19而加以連接於擴散層95D2,97(圖15)之同時,藉由貫通絕緣層I5之貫穿孔導體TH23,而加以連接於形成在絕緣層I5上面的配線58(圖16)。配線58係更藉由貫通絕緣層I2之貫穿孔導體TH28,而加以連接於形成在絕緣層I2上面的電源配線82(圖17)。對於電源配線82,係如圖11所示,加以供給有電源電位VDD。隨之,對於擴散層95D2,97,係成為加以供給有電源電位VDD。
配線54係如圖15所示,藉由圖12所示之貫通絕緣層I1之貫穿孔導體TH12而加以連接於擴散層94D1之同時,藉由貫通絕緣層I1之貫穿孔導體TH17,而加以連接於擴散層95D1。另外,配線54係如上述,加以連接於貫通電極TSV及表面微凸塊MFB(圖12)。隨之,擴散層94D1,95D1係同時如圖11所示,成為加以連接於表面微凸塊MFB者。
其他,圖11所示之寫入資料WD用之配線83係如圖12及圖18所示,加以形成於絕緣層I3之上面,藉由配線75,而加以連接於對應之表面微凸塊MFB。隨之,成為可將供給至表面微凸塊MFB之寫入資料WD,由配線83經由而放入至內部電路90者。
接著,對於對應於各複數之表面微凸塊MFB的電晶體94,95之平面的配置加以說明。在以下中,著眼於圖16所示之表面微凸塊MFB1~MFB9(第1乃至第9之凸塊電極),進行說明。然而,圖16所示之此等符號係指位於對應之配線71的正上方之表面微凸塊MFB。表面微凸塊MFB1~MFB9係與在第1實施形態所說明之表面微凸塊MFB1~MFB9(圖7)相同者。
表面微凸塊MFB1~MFB9之相對的位置關係,係如在第1實施形態所說明。在本實施形態中,表面微凸塊MFBk(k係1~9的整數),係對應於電晶體94k(第2k-1之電晶體)及電晶體95k(第2k之電晶體)。
如圖16所示,電晶體951,954係加以配置於
表面微凸塊MFB1,MFB4之間的範圍。同樣地,電晶體952,955係加以配置於表面微凸塊MFB2,MFB5之間的範圍,電晶體953,956係加以配置於表面微凸塊MFB3,MFB6之間的範圍,電晶體941,947係加以配置於表面微凸塊MFB1,MFB7之間的範圍,電晶體942,948係加以配置於表面微凸塊MFB2,MFB8之間的範圍,電晶體943,949係加以配置於表面微凸塊MFB3,MFB9之間的範圍。更且,電晶體944係對於表面微凸塊MFB4而言,加以配置於電晶體954之相反側,電晶體945係對於表面微凸塊MFB5而言,加以配置於電晶體955之相反側,電晶體946係對於表面微凸塊MFB6而言,加以配置於電晶體956之相反側,電晶體957係對於表面微凸塊MFB7而言,加以配置於電晶體947之相反側,電晶體958係對於表面微凸塊MFB8而言,加以配置於電晶體948之相反側,電晶體959係對於表面微凸塊MFB9而言,加以配置於電晶體949之相反側。
如從以上之配置所理解地,在鄰接於Y方向之表面微凸塊MFB間,電晶體94,95之配置則成為左右相反。由如此作為,在鄰接於X方向之表面微凸塊MFB間,成為可共有為了供給接地電位VSS之電源配線81(圖17)及配線56(圖16),以及為了供給電源電位VDD之電源配線82(圖17)及配線58(圖16)者。然而,從圖16及圖17所理解地,此等配線56,58,81,82係各加以共通地連接於鄰接於Y方向之表面微凸塊MFB間。
將上述之連接關係,對於表面微凸塊MFB1~MFB9而加以說明時,電晶體94k之擴散層94D1(第4k-3之擴散層),和電晶體95k之擴散層95D1(第4k-1之擴散層)係加以連接於對應之表面微凸塊MFBk。另外,各電晶體94k之擴散層94D2(第4k-2之擴散層)係與擴散層96同時,加以連接於供給有接地電位VSS之電源配線81(圖17),而各電晶體95k之擴散層95D2(第4k之擴散層)係與擴散層97同時,加以連接於供給有電源電位VDD之電源配線82(圖17)。
如以上說明,如根據經由本實施形態之半導體裝置10之構成,成為可將圖11所示之各表面微凸塊MFB的輸出電路93(電晶體94,95),設置於凸塊電極設置範圍BA內者。隨之,因無需將為了設置輸出電路93之範圍,設置於凸塊電極設置範圍BA外之故,成為可提升面積的利用效率,而實現半導體裝置之小型化者。
以上,對於本發明之理想實施形態已說明過,但本發明係並不限定於上述實施形態,而在不脫離本發明之內容的範圍可做種種變更,當然此等亦包含於本發明之範圍內者。
例如,本發明係亦可適合適用於未使用具有貫通電極TSV之記憶體晶片的半導體裝置。對於圖19(b)係例示如此之半導體裝置10a的例。半導體裝置10a係如同圖所示,具有從在第1及第2實施形態所說明之半導體裝置10除去記憶體晶片21~23,將未具有貫通電極TSV
之記憶體晶片24,直接層積於控制晶片30上之構成。對於內藏於包含在半導體裝置10a之記憶體晶片24的靜電放電保護電路或讀取資料的輸出電路,本發明係亦可適當地適用。然而,半導體裝置10a亦與半導體裝置10同樣,準備圖19(a)之半製品10aA,經由連接於控制晶片30及電路基板40而製造者為最佳。
63,64,80‧‧‧配線
81‧‧‧電源配線
621~629‧‧‧電晶體
TH4~TH6‧‧‧貫穿孔導體
BA‧‧‧凸塊電極設置範圍
MFB,MFB1~MFB9‧‧‧表面微凸塊
ChA‧‧‧通道
Claims (9)
- 一種半導體裝置,其特徵為具有:半導體基板,和加以形成於前述半導體基板上,沿著第1方向而以第1間距加以配置之第1乃至第3凸塊電極,和加以形成於前述半導體基板上,沿著前述第1方向而以前述第1間距加以配置之第4乃至第6凸塊電極,和加以形成於前述半導體基板上,沿著前述第1方向而以前述第1間距加以配置之第7乃至第9凸塊電極,和包含各加以形成於前述半導體基板之第1及第2擴散層的第1電晶體,和加以配置於前述半導體基板上之第1電源線,前述第1,第4,第7凸塊電極係沿著交叉於前述第1方向之第2方向,前述第1凸塊電極則呈位置於前述第4及第7凸塊電極之間,以第2間距加以配置,前述第2,第5,第8凸塊電極係沿著前述第2方向,前述第2凸塊電極則呈位置於前述第5及第8凸塊電極之間,以前述第2間距加以配置,前述第3,第6,第9凸塊電極係沿著前述第2方向,前述第3凸塊電極則呈位置於前述第6及第9凸塊電極之間,以前述第2間距加以配置,前述第1擴散層係加以連接於前述第1凸塊電極,前述第2擴散層係加以連接於前述第1電源線,前述第1電晶體係加以配置於前述第4乃至第6凸塊電極與前述第7乃至第9凸塊電極之間的範圍者。
- 如申請專利範圍第1項記載之半導體裝置,其中,前述第1乃至第9之凸塊電極係各加以連接於貫通前述半導體基板之第1乃至第9之貫通電極者。
- 如申請專利範圍第1項或第2項記載之半導體裝置,其中,前述第1電晶體係更含有加以形成於前述半導體基板上之第1閘極電極,前述第1閘極電極係加以連接於前述第1電源線者。
- 如申請專利範圍第3項記載之半導體裝置,其中,更具備:包含各加以形成於前述半導體基板之第3及第4擴散層以及第2閘極電極的第2電晶體,和包含各加以形成於前述半導體基板之第5及第6擴散層以及第3閘極電極的第3電晶體,和包含各加以形成於前述半導體基板之第7及第8擴散層以及第4閘極電極的第4電晶體,和包含各加以形成於前述半導體基板之第9及第10擴散層以及第5閘極電極的第5電晶體,和包含各加以形成於前述半導體基板之第11及第12擴散層以及第6閘極電極的第6電晶體,和包含各加以形成於前述半導體基板之第13及第14擴散層以及第7閘極電極的第7電晶體,和包含各加以形成於前述半導體基板之第15及第16擴散層以及第8閘極電極的第8電晶體,和包含各加以形成於前述半導體基板之第17及第18擴散層以及第9閘極電極的第9電晶體, 前述第3擴散層係加以連接於前述第2凸塊電極,前述第5擴散層係加以連接於前述第3凸塊電極,前述第7擴散層係加以連接於前述第4凸塊電極,前述第9擴散層係加以連接於前述第5凸塊電極,前述第11擴散層係加以連接於前述第6凸塊電極,前述第13擴散層係加以連接於前述第7凸塊電極,前述第15擴散層係加以連接於前述第8凸塊電極,前述第17擴散層係加以連接於前述第9凸塊電極,前述第4擴散層,前述第2閘極電極,前述第6擴散層,前述第3閘極電極,前述第8擴散層,前述第4閘極電極,前述第10擴散層,前述第5閘極電極,前述第12擴散層,前述第6閘極電極,前述第14擴散層,前述第7閘極電極,前述第16擴散層,前述第8閘極電極,前述第18擴散層,及前述第9閘極電極係加以連接於前述第1電源線,前述第1乃至第9電晶體係各從前述第1乃至第9凸塊電極之中之對應之構成的平面中心而視,於前述第1方向離開第1距離,且於前述第2方向離開第2距離之位置,呈位於平面的中心地加以配置,前述第1距離係較前述第1間距為小,前述第2距離係較前述第2間距為小者。
- 如申請專利範圍第1項或第2項記載之半導體裝置,其中,更具備:包含各加以形成於前述半導體基板之第3及第4擴散層的第2電晶體, 和加以配置於前述半導體基板上,且加以供給有與前述第1電源線不同之電位的第2電源線,前述第3擴散層係加以連接於前述第1凸塊電極,前述第4擴散層係加以連接於前述第2電源線,前述第1電晶體係加以配置於前述第1凸塊電極與前述第7凸塊電極之間的範圍,前述第2電晶體係加以配置於前述第1凸塊電極與前述第4凸塊電極之間的範圍者。
- 如申請專利範圍第5項記載之半導體裝置,其中,更具備:加以配置於前述第1凸塊電極與前述第7凸塊電極之間的範圍的第1活性範圍,加以配置於前述第1凸塊電極與前述第4凸塊電極之間的範圍的第2活性範圍,前述第1及第2擴散層係加以配置於前述第1活性範圍內,前述第3及第4擴散層係加以配置於前述第2活性範圍內者。
- 如申請專利範圍第5項記載之半導體裝置,其中,前述第1電晶體係為第1導電型之電晶體,前述第2電晶體係與前述第1導電型不同之第2導電型之電晶體者。
- 如申請專利範圍第5項記載之半導體裝置,其中,前述第1電晶體係包含第1閘極電極,前述第2電晶體係包含第2閘極電極, 對於各前述第1及第2閘極電極,係加以供給有顯示應通過前述第1凸塊電極而加以輸出之輸出資料的電位者。
- 如申請專利範圍第5項記載之半導體裝置,其中,更具備:包含各加以形成於前述半導體基板之第5及第6擴散層的第3電晶體,和包含各加以形成於前述半導體基板之第7及第8擴散層的第4電晶體,和包含各加以形成於前述半導體基板之第9及第10擴散層的第5電晶體,和包含各加以形成於前述半導體基板之第11及第12擴散層的第6電晶體,和包含各加以形成於前述半導體基板之第13及第14擴散層的第7電晶體,包含各加以形成於前述半導體基板之第15及第16擴散層的第8電晶體,和包含各加以形成於前述半導體基板之第17及第18擴散層的第9電晶體,和包含各加以形成於前述半導體基板之第19及第20擴散層的第10電晶體,和包含各加以形成於前述半導體基板之第21及第22擴散層的第11電晶體,和包含各加以形成於前述半導體基板之第23及第24擴散層的第12電晶體, 和包含各加以形成於前述半導體基板之第25及第26擴散層的第13電晶體,和包含各加以形成於前述半導體基板之第27及第28擴散層的第14電晶體,和包含各加以形成於前述半導體基板之第29及第30擴散層的第15電晶體,和包含各加以形成於前述半導體基板之第31及第32擴散層的第16電晶體,和包含各加以形成於前述半導體基板之第33及第34擴散層的第17電晶體,和包含各加以形成於前述半導體基板之第35及第36擴散層的第18電晶體,前述第5及第7擴散層係加以連接於前述第2凸塊電極,前述第9及第11擴散層係加以連接於前述第3凸塊電極,前述第13及第15擴散層係加以連接於前述第4凸塊電極,前述第17及第19擴散層係加以連接於前述第5凸塊電極,前述第21及第23擴散層係加以連接於前述第6凸塊電極,前述第25及第27擴散層係加以連接於前述第7凸塊電極, 前述第29及第31擴散層係加以連接於前述第8凸塊電極,前述第33及第35擴散層係加以連接於前述第9凸塊電極,前述第6、10、14、18、22、26、30、34之擴散層係加以連接於前述第1電源線,前述第8、12、16、20、24、28、32、36之擴散層係加以連接於前述第2電源線,前述第2及第8電晶體係加以配置於前述第1凸塊電極與前述第4凸塊電極之間的範圍,前述第1及第13電晶體係加以配置於前述第1凸塊電極與前述第7凸塊電極之間的範圍,前述第4及第10電晶體係加以配置於前述第2凸塊電極與前述第5凸塊電極之間的範圍,前述第3及第15電晶體係加以配置於前述第2凸塊電極與前述第8凸塊電極之間的範圍,前述第6及第12電晶體係加以配置於前述第3凸塊電極與前述第6凸塊電極之間的範圍,前述第5及第17電晶體係加以配置於前述第3凸塊電極與前述第9凸塊電極之間的範圍,前述第7電晶體係相對前述第4凸塊電極,而加以配置於前述第8電晶體之相反側,前述第9電晶體係相對前述第5凸塊電極,而加以配置於前述第10電晶體之相反側, 前述第11電晶體係相對前述第6凸塊電極,而加以配置於前述第12電晶體之相反側,前述第14電晶體係相對前述第7凸塊電極,而加以配置於前述第13電晶體之相反側,前述第16電晶體係相對前述第8凸塊電極,而加以配置於前述第15電晶體之相反側,前述第18電晶體係相對前述第9凸塊電極,而加以配置於前述第17電晶體之相反側,前述第1、第3、第5、第7、第9、第11、第13、第15、第17之電晶體係第1導電型之電晶體,前述第2、第4、第6、第8、第10、第12、第14、第16、第18之電晶體係與前述第1導電型不同之第2導電型之電晶體者。
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