CN112530971A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN112530971A
CN112530971A CN202010757344.2A CN202010757344A CN112530971A CN 112530971 A CN112530971 A CN 112530971A CN 202010757344 A CN202010757344 A CN 202010757344A CN 112530971 A CN112530971 A CN 112530971A
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pad
wiring layer
plug
semiconductor device
substrate
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CN112530971B (zh
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佐贯朋也
田上政由
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Kioxia Corp
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Kioxia Corp
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Abstract

实施方式提供能够提高由焊盘带来的成品率的半导体装置及其制造方法。根据一个实施方式，半导体装置具备基板和设于所述基板上的多个晶体管。所述装置还具备：第一布线层，设于所述晶体管的上方，与所述晶体管的至少一个电连接；设于所述第一布线层上的第一插塞；以及设于所述第一插塞上的第一焊盘。所述装置还具备设于所述第一焊盘上的第二焊盘、设于所述第二焊盘上的第二插塞、以及设于所述第二插塞上的第二布线层。所述装置还具备设于所述第二布线层的上方并与所述第二布线层电连接的存储单元阵列，所述第二焊盘上的所述第二插塞的个数比所述第一焊盘下的所述第一插塞的个数多。

Description

半导体装置及其制造方法
相关申请
本申请享受以日本专利申请2019－169145号(申请日：2019年9月18日)为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的所有内容。
技术领域
本发明的实施方式涉及半导体装置及其制造方法。
背景技术
在使多个晶片的金属焊盘贴合而制造半导体装置的情况下，期望抑制金属焊盘所引起的成品率的降低。
发明内容
实施方式提供能够使由焊盘带来的成品率提高的半导体装置及其制造方法。
根据一个实施方式，半导体装置具备基板和设于所述基板上的多个晶体管。所述装置还具备：第一布线层，设于所述晶体管的上方，与所述晶体管的至少一个电连接；设于所述第一布线层上的第一插塞；以及设于所述第一插塞上的第一焊盘。所述装置还具备设于所述第一焊盘上的第二焊盘、设于所述第二焊盘上的第二插塞、以及设于所述第二插塞上的第二布线层。所述装置还具备设于所述第二布线层的上方并与所述第二布线层电连接的存储单元阵列，所述第二焊盘上的所述第二插塞的个数比所述第一焊盘下的所述第一插塞的个数多。
附图说明
图1是表示第一实施方式的半导体装置的构造的剖面图。
图2是表示第一实施方式的柱状部的构造的剖面图。
图3是表示第一实施方式的半导体装置的制造方法的剖面图。
图4的(a)、(b)是表示第一实施方式的金属焊盘等构造的立体图。
图5的(a)～(d)是表示第一实施方式的金属焊盘等构造的俯视图。
图6是表示第一实施方式的金属焊盘与布线的关系的俯视图。
图7是表示第一实施方式的半导体装置的构成的电路图。
图8的(a)、(b)是表示第一实施方式的半导体装置的构成的俯视图。
图9是表示第一实施方式的金属焊盘与字线的关系的一个例子的剖面图。
图10是表示第一实施方式的金属焊盘与位线的关系的一个例子的剖面图。
附图标记说明
1：阵列芯片，2：电路芯片，3：控制器，
11：存储单元阵列，12：绝缘膜，13：层间绝缘膜，
14：层间绝缘膜，15：基板，16：基板，
21：台阶构造部，22：接触插塞，
23：字线布线层，24：导通塞(via plug)，
31：晶体管，32：栅极电极，33：接触插塞，
34：布线层，35：布线层，36：布线层，
36a、36b：布线，37：导通塞，38：金属焊盘，
41：金属焊盘，42：导通塞，43：布线层，44：布线层，
45：导通塞，46：金属焊盘，47：钝化膜，
51：绝缘层，52：块绝缘膜，53：电荷蓄积层，
54：隧道绝缘膜，55：沟道半导体层，56：芯绝缘膜，
61：平面(存储单元阵列)，62：行解码器，63：SA/DL部，
64：XDL部，65：YLOG部，66：串行电路，67：I/O电路，
71：低电压产生电路，72：高电压产生电路，
73：行控制电路，74：列控制电路，
81：字线平台(terrace)，82：平台空间，83：焊盘区域，
84：周边电路部，85：SA/YLOG部，86：XFER区域，
87：布线区域，88：焊盘区域
具体实施方式
以下，参照附图对本发明的实施方式进行说明。在图1至图10中，对相同的构成标注相同的附图标记而省略重复的说明。
(第一实施方式)
图1是表示第一实施方式的半导体装置的构造的剖面图。图1的半导体装置是阵列芯片1与电路芯片2贴合而成的三维存储器。
阵列芯片1具备：存储单元阵列11，包含三维地配置的多个存储器单元；存储单元阵列11上的绝缘膜12；以及存储单元阵列11下的层间绝缘膜13。绝缘膜12例如是硅氧化膜或者硅氮化膜。层间绝缘膜13例如是硅氧化膜、或者是包含硅氧化膜与其他绝缘膜的层叠膜。
电路芯片2设于阵列芯片1下。附图标记S表示阵列芯片1与电路芯片2的贴合面。电路芯片2具备层间绝缘膜14和层间绝缘膜14下的基板15。层间绝缘膜14例如是硅氧化膜、或者包含硅氧化膜与其他绝缘膜的层叠膜。基板15例如是硅基板等半导体基板。
图1示出了与基板15的表面平行且相互垂直的X方向以及Y方向、和与基板15的表面垂直的Z方向。在本说明书中，将+Z方向作为上方向处理，将－Z方向作为下方向处理。－Z方向可以与重力方向一致，也可以与重力方向不一致。
阵列芯片1具备多个字线WL和源极线SL作为存储单元阵列11内的电极层。图1示出了存储单元阵列11的台阶构造部21。各字线WL经由接触插塞22而与字线布线层23电连接。贯通多个字线WL的各柱状部CL经由导通塞24而与位线BL电连接，并且与源极线SL电连接。源极线SL包含作为半导体层的第一层SL1和作为金属层的第二层SL2。
电路芯片2具备多个晶体管31。各晶体管31具备经由栅极绝缘膜设于基板15上的栅极电极32和设于基板15内的未图示的源极扩散层以及漏极扩散层。另外，电路芯片2具备设于这些晶体管31的源极扩散层或者漏极扩散层上的多个接触插塞33、设于这些接触插塞33上并包含多个布线的布线层34、以及设于布线层34上并包含多个布线的布线层35。
电路芯片2还具备设于布线层35上并包含多个布线的布线层36、设于布线层36上的多个导通塞37、以及设于这些导通塞37上的多个金属焊盘38。金属焊盘38例如是Cu(铜)层或者Al(铝)层。金属焊盘38是第一焊盘的例子，导通塞37是第一插塞的例子，布线层36是第一布线层的例子。电路芯片2作为控制阵列芯片1的动作的控制电路(逻辑电路)发挥功能。该控制电路由晶体管31等构成，并电连接于金属焊盘38。
阵列芯片1具备设于金属焊盘38上的多个金属焊盘41和设于金属焊盘41上的多个导通塞42。另外，阵列芯片1具备设于这些导通塞42上并包含多个布线的布线层43和设于布线层43上并包含多个布线的布线层44。金属焊盘41例如是Cu层或者Al层。金属焊盘41是第二焊盘的例子，导通塞42是第二插塞的例子，布线层43是第二布线层的例子。
阵列芯片1还具备设于布线层44上的多个导通塞45、设于这些导通塞45上和/或绝缘膜12上的金属焊盘46、以及设于金属焊盘46上和/或绝缘膜12上的钝化膜47。金属焊盘46例如是Cu层或者Al层，作为图1的半导体装置的外部连接焊盘(键合焊盘)发挥功能。钝化膜47例如是硅氧化膜等绝缘膜，具有使金属焊盘46的上表面露出的开口部P。金属焊盘46能够经由该开口部P而利用接合线、焊料球、金属凸块等连接于安装基板和/或其他装置。
另外，之后详细叙述金属焊盘38、41、导通塞37、42、布线层36、43。
图2是表示第一实施方式的柱状部CL的构造的剖面图。
如图2所示，存储单元阵列11具备在层间绝缘膜13(图1)上交替地层叠的多个字线WL与多个绝缘层51。字线WL例如是W(钨)层。绝缘层51例如是硅氧化膜。
柱状部CL依次含有块绝缘膜52、电荷蓄积层53、隧道绝缘膜54、沟道半导体层55、以及芯绝缘膜56。电荷蓄积层53例如是硅氮化膜，隔着块绝缘膜52形成于字线WL以及绝缘层51的侧面。电荷蓄积层53也可以是多晶硅层等半导体层。沟道半导体层55例如是多晶硅层，隔着隧道绝缘膜54形成于电荷蓄积层53的侧面。块绝缘膜52、隧道绝缘膜54、以及芯绝缘膜56例如是硅氧化膜或者金属绝缘膜。
图3是表示第一实施方式的半导体装置的制造方法的剖面图。图3示出了包含多个阵列芯片1的阵列晶片W1和包含多个电路芯片2的电路晶片W2。阵列晶片W1也被称作存储器晶片，电路晶片W2也被称作CMOS晶片。
希望注意的是，图3的存储器晶片W1的朝向与图1的阵列芯片1的朝向相反。在本实施方式中，通过使阵列晶片W1与电路晶片W2贴合而制造半导体装置。图3示出了为了贴合而使朝向反转之前的存储器晶片W1，图1示出了为了贴合而使朝向反转并进行了贴合以及切割之后的阵列芯片1。
在图3中，附图标记S1表示存储器晶片W1的上表面，附图标记S2表示电路晶片W2的上表面。希望注意的是，存储器晶片W1具备设于绝缘膜12下的基板16。基板16例如是硅基板等半导体基板。基板15是第一基板的例子，基板16是第二基板的例子。
在本实施方式中，首先，如图3所示，在存储器晶片W1的基板16上形成存储单元阵列11、绝缘膜12、层间绝缘膜13、台阶构造部21、金属焊盘41等，并在电路晶片W2的基板15上形成层间绝缘膜14、晶体管31、金属焊盘38等。例如在基板16上依次形成导通塞45、布线层44、布线层43、导通塞42、以及金属焊盘41。另外，在基板15上依次形成接触插塞33、布线层34、布线层35、布线层36、导通塞37、以及金属焊盘38。接下来，通过机械性压力使阵列晶片W1与电路晶片W2贴合。由此，层间绝缘膜13与层间绝缘膜14被粘合。接下来，将阵列晶片W1以及电路晶片W2以400℃退火。由此，金属焊盘41与金属焊盘38被接合。
之后，利用CMP(Chemical Mechanical Polishing，化学机械研磨)使基板15薄膜化，利用CMP去除基板16之后，将阵列晶片W1以及电路晶片W2切断成多个芯片。这样，制造出图1的半导体装置。另外，金属焊盘46与钝化膜47例如在基板15的薄膜化以及基板16的去除之后形成于绝缘膜12上。
另外，在本实施方式中，使阵列晶片W1与电路晶片W2贴合，但也可以取代于此而使阵列晶片W1彼此贴合。参照图1至图3的前述的内容、参照图4至图10的前述的内容也能够应用于阵列晶片W1彼此的贴合。
另外，图1示出了层间绝缘膜13与层间绝缘膜14的边界面、金属焊盘41与金属焊盘38的边界面，但在上述的退火后，一般不再能观察到这些边界面。然而，这些边界面所在的位置能够通过检测例如金属焊盘41的侧面和金属焊盘38的侧面的倾斜、或金属焊盘41的侧面与金属焊盘38的位置的偏移来推断。
图4是表示第一实施方式的金属焊盘38、41等构造的立体图。
图4的(a)示出了电连接于字线WL的一组金属焊盘38、41。在本实施方式中，在电连接于字线WL的金属焊盘38的下表面设有一个以上的导通塞37，在电连接于字线WL的金属焊盘41的上表面设有一个以上的导通塞42。除此之外，在电连接于字线WL的一组金属焊盘38、41中，金属焊盘41的上表面的导通塞42的个数比金属焊盘38的下表面的导通塞37的个数多。在图4的(a)中，在金属焊盘38的下表面设有两个导通塞37，在金属焊盘41的上表面设有四个导通塞42。
图4的(a)还示出了布线层36内的多个布线的例子即3条布线36a和布线层43内的多个布线的例子即1条布线43a。金属焊盘38的下表面的两个导通塞37设于布线层36内的相同的布线上，具体而言，设于图4的(a)的中央的布线36a上。同样，金属焊盘41的上表面的四个导通塞42设于布线层43内的相同的布线下，具体而言，设于图4的(a)的布线43a下。
如此，图4的(a)的中央的布线36a与两个导通塞37电连接，图4的(a)的布线43a与四个导通塞42电连接，后者的个数比前者的个数多。因此，本实施方式的布线层43的厚度(Z方向的宽度)设定为比布线层38的厚度(Z方向的宽度)厚。例如布线层38的厚度是0.5μm，布线层43的厚度是1.0μm。另外，导通塞37的厚度(Z方向的宽度)与导通塞42的厚度(Z方向的宽度)可以是相同的值，也可以是不同的值，可以是导通塞37与导通塞42中的任一个较厚。
导通塞42也可以以任意的排列配置在金属焊盘41上。本实施方式的导通塞42在金属焊盘41上配置为正方形(或者长方形)的格子状。该正方形与金属焊盘41相同，由与X方向平行的二边和与Y方向平行的二边构成。
导通塞37也可以在金属焊盘38下以任意的排列配置。本实施方式的导通塞37在金属焊盘38下配置于沿Y方向延伸的直线上。在图4的(a)中，3条布线38a沿Y方向延伸，导通塞37在中央的布线38a上排列地配置。
金属焊盘38的下表面的导通塞37的个数也可以是两个以外，金属焊盘41的上表面的导通塞42的个数也可以是四个以外。但是，金属焊盘41的上表面的导通塞42的个数期望设为金属焊盘38的下表面的导通塞37的个数的二次方个。例如在将金属焊盘38的下表面的导通塞37的个数设为三个的情况下，期望将金属焊盘41的上表面的导通塞42的个数设为9个(＝3的二次方个)。由此，能够适当地将导通塞42配置为正方形(或者长方形)的格子状。而且，能够将导通塞37配置为与该格子的一列的排列相同的排列。
图4的(b)示出了电连接于位线BL的一组金属焊盘38、41。在本实施方式中，在电连接于位线BL的金属焊盘38的下表面设有一个以上的导通塞37，在电连接于位线BL的金属焊盘41的上表面设有一个以上的导通塞42。除此之外，在电连接于位线BL的一组金属焊盘38、41中，金属焊盘41的上表面的导通塞42的个数比金属焊盘38的下表面的导通塞37的个数多。在图4的(b)中，在金属焊盘38的下表面设有两个导通塞37，在金属焊盘41的上表面设有四个导通塞42。图4的(b)的金属焊盘38、41、导通塞37、42的详细情况与图4的(a)的相同。
图4的(b)还示出了作为布线层36内的多个布线的例子的3条布线36a和作为布线层43内的多个布线的例子的1条布线43a。金属焊盘38的下表面的两个导通塞37设于布线层36内的相同的布线上，具体而言，设于图4的(b)的中央的布线36a上。同样，金属焊盘41的上表面的四个导通塞42设于布线层43内的相同的布线下，具体而言，设于图4的(b)的布线43a下。图4的(b)的布线层36、43的详细情况与图4的(a)相同。
如以上那样，在图4的(a)、图4的(b)所示的一组金属焊盘38、41中，在金属焊盘38的下表面设有一个以上的导通塞37，在金属焊盘41的上表面设有一个以上的导通塞42。由此，能够减少金属焊盘38与布线36a之间的连接不良、以及金属焊盘41与布线43a之间的连接不良。其理由是，即使金属焊盘38与布线36a之间的某个导通塞37的连接异常，只要金属焊盘38与布线36a之间的其他的导通塞37的连接正常，就可使金属焊盘38与布线36a之间的连接正常。这对于金属焊盘41与布线43a也相同。本实施方式的半导体装置例如也有具备100万组左右的金属焊盘38、41的情况，因此提高由金属焊盘38、41带来的成品率很有助于半导体装置的成品率的提高。
另一方面，如此配置多个导通塞37、42的情况下，有可能使半导体装置的集成度降低。例如在电路芯片2内，要求密集地配置与字线WL连接的布线36a、在与位线BL连接的布线36a的附近配置信号线。因此，在图4的(a)、图4的(b)所示的一组金属焊盘38、41中，将金属焊盘38的下表面的导通塞37的个数设定为比金属焊盘41的上表面的导通塞42的个数少。由此，能够提高电路芯片2内的布线36a的配置的自由度，并且提高由金属焊盘38、41带来的成品率。
图5是表示第一实施方式的金属焊盘38、41等构造的俯视图。
图5的(a)与图5的(b)示出了电连接于字线WL(或者位线BL)的一组金属焊盘41、38。这些金属焊盘41、38具有大致相同的平面形状。
图5的(c)示出了设于图5的(a)的金属焊盘41上的四个导通塞42和包含设于这些导通塞42上的布线43a的布线层43。图5的(d)示出了设于图5的(b)的金属焊盘38下的两个导通塞37和包含设于这些导通塞37下的布线36a的布线层36。导通塞42、37的平面形状例如是0.25μm×0.25μm的正方形。
图6是表示第一实施方式的金属焊盘38与布线36a的关系的俯视图。
图6示出了电连接于字线WL(或者位线BL)的两个金属焊盘38、设于这些金属焊盘38下的四个导通塞37、以及包含设于这些导通塞37下的两条布线36a的布线层36。这些布线36a经过两个金属焊盘38的正下方而沿Y方向延伸。各金属焊盘38利用两个导通塞37与这些布线36a中的某个电连接。
本实施方式的各金属焊盘38具有能够与四个导通塞37连接的尺寸，但实际上只与两个导通塞37连接。这些导通塞37沿Y方向排列地配置。这能够减小经过图6的金属焊盘38的正下方的布线36a的X方向的宽度。其理由是，各布线36a上的导通塞37虽然沿Y方向排列地配置，但未沿X方向排列地配置，因此各布线36a的X方向的宽度只要设定为能够与一个导通塞37连接的程度的宽度就足以。由此，在本实施方式中，能够减小经过金属焊盘38的正下方的布线36a的宽度，能够使多个布线36a经过各金属焊盘38的正下方。由此，能够提高半导体装置的集成度。
另外，在图6中，2条布线36a经过金属焊盘38的正下方，但也可以是3条以上的布线36a经过金属焊盘38的正下方。
图7是表示第一实施方式的半导体装置的构成的电路图。
图7示出了构成存储单元阵列11的多个平面61、设为这些平面61用的多个行解码器62、多个SA/DL部63、多个XDL部64、以及多个YLOG部65。图7还示出了串行电路66、I/O(Input/Output)电路67、低电压产生电路71、高电压产生电路72、行控制电路73、以及列控制电路74。它们位于阵列芯片1内的存储单元阵列11附近或者电路芯片2内的逻辑电路内。图7还示出了本实施方式的半导体装置所含的控制器3。
各平面61包括多个存储器单元、多个字线WL、多个位线BL等。各行解码器62向字线WL等控制布线施加控制电压。这种控制电压的例子是写入电压(VPRG)、消除电压(VERASE)、中间电压(VPASS)、源极电压(VSL)等。各SA/DL部63是检测在位线BL读出的数据的读出放大器电路以及数据锁存电路。各XDL部64是储存从SA/DL部63、I/O电路67发送的数据的数据锁存电路。各YLOG部65将列地址解码，基于解码结果选择XDL部64内的锁定电路。串行电路66提供多个平面61共享的串行总线等，I/O电路67在与控制器3之间收发输入信号、输出信号。
低电压产生电路71与高电压产生电路72构成了控制电压产生电路，分别产生用作控制电压的低电压与高电压。行控制电路73与列控制电路74分别实施与各平面61的行、列相关的控制。
图7所示的附图标记P示出了图4的(a)、图4的(b)所示的金属焊盘38、41所配置的场所的例子。如图7所示，图4的(a)、图4的(b)所示的金属焊盘38、41例如配置于平面61内的位线BL下和/或行解码器62附近的字线WL下。
图8是表示第一实施方式的半导体装置的构成的俯视图。
图8的(a)示出了贴合前的阵列芯片1，图8的(b)示出了贴合前的电路芯片2。阵列芯片1具备四个存储单元阵列11、它们的台阶构造部21以及字线平台81、存储单元阵列11间的平台空间82、以及键合焊盘(金属焊盘46)用的焊盘区域83。电路芯片2具备四个周边电路部84、它们的SA/YLOG部85以及XFER区域86、周边电路部84间的布线区域87、以及键合焊盘(金属焊盘46)用的焊盘区域88。
图8的(a)以及图8的(b)分别示出了阵列芯片1上的多个金属焊盘41和电路芯片2上的多个金属焊盘38。字线WL用的金属焊盘41、38(参照图4的(a))例如配置于字线平台81上、XFER区域86上。位线BL用的金属焊盘41、38(参照图4的(b))例如配置于台阶构造部21上和/或SA/YLOG部85上。
图9是表示第一实施方式的金属焊盘38、41与字线WL的关系的一个例子的剖面图。
图9与图1相同，示出了阵列芯片1内的存储单元阵列11、台阶构造部21、接触插塞22、字线布线层23、电路芯片2内的基板15、晶体管31、栅极电极32等。
图9进一步与图4的(a)相同地示出了电连接于字线WL的3组金属焊盘38、41。在各组的金属焊盘38、41中，金属焊盘41经由多个导通塞42、布线层43、字线布线层23、以及接触插塞22而与字线WL电连接，金属焊盘38经由多个导通塞37、布线层36、35、34、以及接触插塞33而与晶体管31电连接。
图10是表示第一实施方式的金属焊盘38、41与位线BL的关系的一个例子的剖面图。
图10与图1相同，示出了阵列芯片1内的存储单元阵列11、柱状部CL，导通塞24、位线BL、电路芯片2内的基板15、晶体管31、栅极电极32等。
图10进一步与图4的(b)相同地示出了电连接于位线BL的一组金属焊盘38、41和其他3组金属焊盘38、41。在电连接于位线BL的金属焊盘38、41中，金属焊盘41经由多个导通塞42、布线层43、位线BL、多个导通塞24而与多个柱状部CL电连接，金属焊盘38经由多个导通塞37、布线层36、35、34、以及接触插塞33而与晶体管31电连接。
图10的布线层36包含与图10的多个金属焊盘38电连接的多个布线36a和其他布线36b。布线36b实际上在与图10的YZ剖面不同的YZ剖面中配置为与布线36a相同的高度，但为了方便说明，在图10中用虚线表示。布线36b如图10所示那样沿Y方向较长地延伸。
布线36b例如是在与位线BL连接的布线36a的附近配置的信号线。信号线的例子是源极线。如参照图6说明的那样，在本实施方式中，能够减小经过金属焊盘38的正下方的布线36a的宽度。由此，根据本实施方式，能够将布线36b配置于布线36a的附近，例如能够使布线36b与布线36a同样经过金属焊盘38的正下方。由此，能够提高半导体装置的集成度。
如以上那样，在本实施方式的一组金属焊盘38、41中，在金属焊盘38的下表面设置一个以上的导通塞37，在金属焊盘41的上表面设置一个以上的导通塞42，金属焊盘41的上表面的导通塞42的个数比金属焊盘38的下表面的导通塞37的个数多。由此，根据本实施方式，能够适当地提高由金属焊盘38、41带来的半导体装置的成品率。
以上，虽然说明了几个实施方式，但这些实施方式仅是作为例子而提示的，并不意图限定发明的范围。本说明书中说明的新的装置以及方法能够以其他各种方式实施。另外，对于本说明书中说明的装置以及方法的方式，能够在不脱离发明的主旨范围内进行各种省略、替换、变更。添附的权利要求书以及与其等效的范围意图包含发明的范围及主旨中包含的这种方式及变形例。

Claims (9)

1.一种半导体装置，具备：
基板；
多个晶体管，设于所述基板上；
第一布线层，设于所述晶体管的上方，与所述晶体管的至少一个电连接；
第一插塞，设于所述第一布线层上；
第一焊盘，设于所述第一插塞上；
第二焊盘，设于所述第一焊盘上；
第二插塞，设于所述第二焊盘上；
第二布线层，设于所述第二插塞上；
存储单元阵列，设于所述第二布线层的上方，与所述第二布线层电连接，
所述第二焊盘上的所述第二插塞的个数比所述第一焊盘下的所述第一插塞的个数多。
2.根据权利要求1所述的半导体装置，
所述第二焊盘上的所述第二插塞的个数是所述第一焊盘下的所述第一插塞的个数的二次方个。
3.根据权利要求1或2所述的半导体装置，
所述第二插塞配置为正方形或者长方形的格子状。
4.根据权利要求3所述的半导体装置，
所述第一插塞配置于与所述正方形或者所述长方形中的某一个边平行的直线上。
5.根据权利要求1或2所述的半导体装置，
所述第一插塞设于所述第一布线层内的相同的布线上，
所述第二插塞设于所述第二布线层内的相同的布线下。
6.根据权利要求5所述的半导体装置，
所述第二布线层的厚度比所述第一布线层的厚度厚。
7.根据权利要求5所述的半导体装置，
所述第一布线层包含在所述第一焊盘的正下方经过的两条以上的布线，
所述第一焊盘利用所述第一插塞与所述两条以上的布线中的某一条布线电连接。
8.根据权利要求1或2所述的半导体装置，
所述第二焊盘经由所述第二插塞而与设于所述基板的上方的字线或者位线电连接。
9.一种半导体装置的制造方法，包含如下步骤：
在第一基板上形成多个晶体管；
在所述晶体管的上方形成与所述晶体管的至少一个电连接的第一布线层；
在所述第一布线层上形成第一插塞；
在所述第一插塞上形成第一焊盘；
在第二基板上形成存储单元阵列；
在所述存储单元阵列的上方形成与所述存储单元阵列电连接的第二布线层；
在所述第二布线层上形成第二插塞；
在所述第二插塞上形成第二焊盘；以及
使设于所述第一基板上的所述第一焊盘和设于所述第二基板上的所述第二焊盘贴合，
所述第二焊盘上的所述第二插塞的个数比所述第一焊盘下的所述第一插塞的个数多。
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