TW202125786A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TW202125786A
TW202125786A TW109123307A TW109123307A TW202125786A TW 202125786 A TW202125786 A TW 202125786A TW 109123307 A TW109123307 A TW 109123307A TW 109123307 A TW109123307 A TW 109123307A TW 202125786 A TW202125786 A TW 202125786A
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pad
wiring layer
plug
wiring
plugs
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TW109123307A
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TWI746052B (zh
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佐貫朋也
田上政由
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日商鎧俠股份有限公司
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Abstract

實施方式提供一種半導體裝置及其製造方法，其可使因墊而起的良率提升。 依一實施方式時，半導體裝置具備基板和設於前述基板上的複數個電晶體。前述裝置進一步具備設於前述電晶體之上方且與前述電晶體中的至少一者電連接的第1佈線層、設於前述第1佈線層上的第1插塞、和設於前述第1插塞上的第1墊。前述裝置進一步具備設於前述第1墊上的第2墊、設於前述第2墊上的第2插塞、和設於前述第2插塞上的第2佈線層。前述裝置進一步具備設於前述第2佈線層之上方且與前述第2佈線層電連接的記憶體單元陣列，前述第2墊上的前述第2插塞的個數比前述第1墊下的前述第1插塞的個數多。

Description

半導體裝置及其製造方法
本發明之實施方式涉及半導體裝置及其製造方法。 [關聯案] 本案根據日本特願2019-169145號(申請日：2019年09月18日)主張優先權。本案透過參照此基礎案從而包含基礎案的全部的內容。
在將複數個晶圓的金屬墊貼合而製造半導體裝置的情況下，要求抑制因金屬墊而起的良率的降低。
實施方式提供一種半導體裝置及其製造方法，其可使因墊而起的良率提升。 依一實施方式時，半導體裝置具備基板和設於前述基板上的複數個電晶體。前述裝置進一步具備設於前述電晶體之上方且與前述電晶體中的至少一者電連接的第1佈線層、設於前述第1佈線層上的第1插塞、和設於前述第1插塞上的第1墊。前述裝置進一步具備設於前述第1墊上的第2墊、設於前述第2墊上的第2插塞、和設於前述第2插塞上的第2佈線層。前述裝置進一步具備設於前述第2佈線層之上方且與前述第2佈線層電連接的記憶體單元陣列，前述第2墊上的前述第2插塞的個數比前述第1墊下的前述第1插塞的個數多。
以下，就本發明的實施方式，參照圖式進行說明。於圖1至圖10中，對相同的構成標注相同的符號，省略重複的說明。 (第1實施方式) 圖1為就第1實施方式的半導體裝置的構造進行繪示的剖面圖。圖1的半導體裝置為貼合陣列晶片1與電路晶片2的3維記憶體。 陣列晶片1具備包含被3維地配置的複數個記憶體單元的記憶體單元陣列11、記憶體單元陣列11上的絕緣膜12、和記憶體單元陣列11下的層間絕緣膜13。絕緣膜12為例如矽氧化膜或矽氮化膜。層間絕緣膜13為包含例如氧化矽膜或矽氧化膜、和其他絕緣膜的層積膜。 電路晶片2設於陣列晶片1下。符號S表示陣列晶片1和電路晶片2的貼合面。電路晶片2具備層間絕緣膜14和層間絕緣膜14下的基板15。層間絕緣膜14為包含例如氧化矽膜或矽氧化膜、和其他絕緣膜的層積膜。基板15為例如矽基板等的半導體基板。 圖1示出平行於基板15的表面且彼此垂直的X方向及Y方向和與基板15的表面垂直的Z方向。在本說明書，將+Z方向待為上方向，將-Z方向待為下方向。-Z方向可與重力方向一致亦可不一致。 陣列晶片1具備複數個字線WL和源極線SL作為記憶體單元陣列11內的電極層。圖1示出記憶體單元陣列11的階層構造部21。各字線WL經由接觸插塞22而與字佈線層23電連接。貫通複數個字線WL的各柱狀部CL經由導孔插塞24而與位元線BL電連接，且與源極線SL電連接。源極線SL包含為半導體層之第1層SL1和為金屬層之第2層SL2。 電路晶片2具備複數個電晶體31。各電晶體31具備經由閘極絕緣膜設於基板15上的閘極電極32、設於基板15內的未圖示的源極擴散層及汲極擴散層。此外，電路晶片2具備設於此等電晶體31的源極擴散層或汲極擴散層上的複數個接觸插塞33、設於此等接觸插塞33上且包含複數個佈線的佈線層34、和設於佈線層34上且包含複數個佈線的佈線層35。 電路晶片2進一步具備設於佈線層35上且包含複數個佈線的佈線層36、設於佈線層36上的複數個導孔插塞37、和設於此等導孔插塞37上的複數個金屬墊38。金屬墊38為例如Cu(銅)層或Al(鋁)層。金屬墊38為第1墊之例，導孔插塞37為第1插塞之例，佈線層36為第1佈線層之例。電路晶片2作用為控制陣列晶片1的動作的控制電路(邏輯電路)。此控制電路由電晶體31等構成，與金屬墊38電連接。 陣列晶片1具備設於金屬墊38上的複數個金屬墊41、和設於金屬墊41上的複數個導孔插塞42。此外，陣列晶片1具備設於此等導孔插塞42上且包含複數個佈線的佈線層43、和設於佈線層43上且包含複數個佈線的佈線層44。金屬墊41為例如Cu層或Al層。金屬墊41為第2墊之例，導孔插塞42為第2插塞之例，佈線層43為第2佈線層之例。 陣列晶片1進一步具備設於佈線層44上的複數個導孔插塞45、設於此等導孔插塞45上、絕緣膜12上的金屬墊46、和設於金屬墊46上、絕緣膜12上的鈍化膜47。金屬墊46為例如Cu層或Al層，作用為圖1的半導體裝置的外部連接墊(接合墊)。鈍化膜47為例如矽氧化膜等的絕緣膜，具有使金屬墊46之上表面曝露的開口部P。金屬墊46可經由此開口部P透過接合線、焊球、金屬凸塊等連接於安裝基板、其他裝置。 另外，金屬墊38、41、導孔插塞37、42、佈線層36、43的細節方面後述之。 圖2為就第1實施方式的柱狀部CL的構造進行繪示的剖面圖。 如示於圖2，記憶體單元陣列11具備在層間絕緣膜13(圖1)上交替層積的複數個字線WL和複數個絕緣層51。字線WL為例如W(鎢)層。絕緣層51為例如矽氧化膜。 柱狀部CL依序含有區塊絕緣膜52、電荷存儲層53、通道絕緣膜54、通道半導體層55、及核心絕緣膜56。電荷存儲層53為例如矽氮化膜，隔著區塊絕緣膜52形成於字線WL及絕緣層51之側面。電荷存儲層53可為多晶矽層等的半導體層。通道半導體層55為例如多晶矽層，隔著通道絕緣膜54形成於電荷存儲層53之側面。區塊絕緣膜52、通道絕緣膜54、及核心絕緣膜56為例如矽氧化膜或金屬絕緣膜。 圖3為就第1實施方式的半導體裝置的製造方法進行繪示的剖面圖。圖3示出包含複數個陣列晶片1的陣列晶圓W1、和包含複數個電路晶片2的電路晶圓W2。陣列晶圓W1亦稱為記憶體晶圓，電路晶圓W2亦稱為CMOS晶圓。 應注意點在於，圖3的記憶體晶圓W1的朝向與圖1的陣列晶片1的朝向相反。在本實施方式，將陣列晶圓W1與電路晶圓W2貼合從而製造半導體裝置。圖3示出為了貼合而使朝向反轉前的記憶體晶圓W1，圖1示出為了貼合使朝向反轉而貼合及切割後的陣列晶片1。 於圖3，符號S1表示記憶體晶圓W1之上表面，符號S2表示電路晶圓W2之上表面。應注意點在於，記憶體晶圓W1具備設於絕緣膜12下的基板16。基板16為例如矽基板等的半導體基板。基板15為第1基板之例，基板16為第2基板之例。 在本實施方式，首先如示於圖3，在記憶體晶圓W1的基板16上，形成記憶體單元陣列11、絕緣膜12、層間絕緣膜13、階層構造部21、金屬墊41等，在電路晶圓W2的基板15上，形成層間絕緣膜14、電晶體31、金屬墊38等。例如，在基板16上依序形成導孔插塞45、佈線層44、佈線層43、導孔插塞42、及金屬墊41。此外，在基板15上依序形成接觸插塞33、佈線層34、佈線層35、佈線層36、導孔插塞37、及金屬墊38。接著，將陣列晶圓W1與電路晶圓W2透過機械壓力進行貼合。據此，層間絕緣膜13與層間絕緣膜14被接合。接著，將陣列晶圓W1及電路晶圓W2以400℃進行退火。據此，金屬墊41與金屬墊38被接合。 之後，將基板15透過CMP(Chemical Mechanical Polishing)薄膜化，將基板16透過CMP除去後，將陣列晶圓W1及電路晶圓W2切斷為複數個晶片。如此，製造出圖1的半導體裝置。另外，金屬墊46與鈍化膜47例如在基板15的薄膜化及基板16的除去後形成於絕緣膜12上。 另外，在本實施方式雖將陣列晶圓W1和電路晶圓W2貼合，惟亦可替而將陣列晶圓W1彼此貼合。參照圖1～圖3而前述的內容、參照圖4～圖10而後述的內容亦可適用於陣列晶圓W1彼此的貼合。 此外，圖1雖示出層間絕緣膜13與層間絕緣膜14的邊界面、金屬墊41與金屬墊38的邊界面，惟一般而言上述的退火後無法觀察到此等邊界面。然而，此等邊界面存在的位置可透過檢測出例如金屬墊41之側面、金屬墊38之側面的傾斜、金屬墊41之側面和金屬墊38的位置偏差從而推定。 圖4為就第1實施方式的金屬墊38、41等的構造進行繪示的透視圖。 圖4(a)示出與字線WL電連接的1組金屬墊38、41。在本實施方式，在與字線WL電連接的金屬墊38的下表面設置1個以上的導孔插塞37，在與字線WL電連接的金屬墊41的上表面設置1個以上的導孔插塞42。此外，在與字線WL電連接的1組金屬墊38、41方面，金屬墊41之上表面的導孔插塞42的個數比金屬墊38的下表面的導孔插塞37的個數多。在圖4(a)，在金屬墊38的下表面設置2個導孔插塞37，在金屬墊41之上表面設置4個導孔插塞42。 圖4(a)進一步示出為佈線層36內的複數個佈線之例的3個佈線36a、和為佈線層43內的複數個佈線之例的1個佈線43a。金屬墊38的下表面的2個導孔插塞37設於佈線層36內的相同的佈線上，具體而言設於圖4(a)之中央的佈線36a上。同樣地，金屬墊41之上表面的4個導孔插塞42設於佈線層43內的相同的佈線下，具體而言設於圖4(a)的佈線43a下。 如此，圖4(a)之中央的佈線36a與2個導孔插塞37電連接，圖4(a)的佈線43a與4個導孔插塞42電連接，後者的個數比前者的個數多。為此，本實施方式的佈線層43的厚度(Z方向的寬)設定為比佈線層38的厚度(Z方向的寬)厚。例如，佈線層38的厚度為0.5μm，佈線層43的厚度為1.0μm。另外，導孔插塞37的厚度(Z方向的寬)與導孔插塞42的厚度(Z方向的寬)可為相同的值亦可為不同的值，導孔插塞37與導孔插塞42的其中一方較厚皆可。 導孔插塞42以任何排列配置於金屬墊41上皆可。本實施方式的導孔插塞42在金屬墊41上配置為正方形(或長方形)的格子狀。此正方形如同金屬墊41，由平行於X方向的二邊、和平行於Y方向的二邊形成。 導孔插塞37亦以任何排列配置於金屬墊38下皆可。本實施方式的導孔插塞37於金屬墊38下配置於延伸於Y方向的直線上。在圖4(a)，3個佈線38a延伸於Y方向，導孔插塞37排列於中央的佈線38a上而被配置。 金屬墊38的下表面的導孔插塞37的個數可為2個以外，金屬墊41之上表面的導孔插塞42的個數可為4個以外。其中，金屬墊41之上表面的導孔插塞42的個數優選上為金屬墊38的下表面的導孔插塞37的個數的平方個。例如，在金屬墊38的下表面的導孔插塞37的個數為3個的情況下，金屬墊41之上表面的導孔插塞42的個數為9個(＝3的平方個)為優選。據此，可將導孔插塞42在無過與不足之下配置為正方形(或長方形)的格子狀。再者，可將導孔插塞37配置為與此格子的一行份的排列相同的排列。 圖4(b)示出與位元線BL電連接的1組金屬墊38、41。在本實施方式，在與位元線BL電連接的金屬墊38的下表面設置1個以上的導孔插塞37，在與位元線BL電連接的金屬墊41之上表面設置1個以上的導孔插塞42。此外，在與位元線BL電連接的1組金屬墊38、41方面，金屬墊41之上表面的導孔插塞42的個數比金屬墊38的下表面的導孔插塞37的個數多。在圖4(b)，在金屬墊38的下表面設置2個導孔插塞37，在金屬墊41之上表面設置4個導孔插塞42。圖4(b)的金屬墊38、41、導孔插塞37、42的細節與圖4(a)的細節同樣。 圖4(b)進一步示出為佈線層36內的複數個佈線之例的3個佈線36a、和為佈線層43內的複數個佈線之例的1個佈線43a。金屬墊38的下表面的2個導孔插塞37設於佈線層36內的相同的佈線上，具體而言，設於圖4(b)之中央的佈線36a上。同樣地，金屬墊41之上表面的4個導孔插塞42設於佈線層43內的相同的佈線下，具體而言設於圖4(b)的佈線43a下。圖4(b)的佈線層36、43的細節與圖4(a)的細節同樣。 如以上，在示於圖4(a)、圖4(b)的1組金屬墊38、41方面，在金屬墊38的下表面設置1個以上的導孔插塞37，在金屬墊41之上表面設置1個以上的導孔插塞42。據此，可減低金屬墊38和佈線36a之間的連接不良、金屬墊41和佈線43a之間的連接不良。理由在於，即使金屬墊38和佈線36a之間的一導孔插塞37的連接為異常，只要金屬墊38和佈線36a之間的別的導孔插塞37的連接為正常，則金屬墊38和佈線36a之間的連接可為正常。此在金屬墊41和佈線43a方面亦同。本實施方式的半導體裝置有時亦具備例如100萬組程度的金屬墊38、41，故使因金屬墊38、41而起的良率提升可大為有助於半導體裝置的良率的提升。 另一方面，如此般配置多數個導孔插塞37、42恐使半導體裝置的積體度降低。在例如電路晶片2內，需要密集地配置與字線WL連接的佈線36a、在與位元線BL連接的佈線36a的附近配置信號線。因此，在示於圖4(a)、圖4(b)的1組金屬墊38、41方面，將金屬墊38的下表面的導孔插塞37的個數設定為比金屬墊41之上表面的導孔插塞42的個數少。據此，可一面提高電路晶片2內的佈線36a的配置的自由度，一面使因金屬墊38、41而起的良率提升。 圖5為就第1實施方式的金屬墊38、41等的構造進行繪示的平面圖。 圖5(a)和圖5(b)示出與字線WL(或位元線BL)電連接的1組金屬墊41、38。此等金屬墊41、38具有大致相同的平面形狀。 圖5(c)示出設於圖5(a)的金屬墊41上的4個導孔插塞42、和包含設於此等導孔插塞42上的佈線43a之佈線層43。圖5(d)示出設於圖5(b)的金屬墊38下的2個導孔插塞37、和包含設於此等導孔插塞37下的佈線36a之佈線層36。導孔插塞42、37的平面形狀為例如0.25μm×0.25μm的正方形。 圖6為就第1實施方式的金屬墊38和佈線36a的關係進行繪示的平面圖。 圖6示出與字線WL(或位元線BL)電連接的2個金屬墊38、設於此等金屬墊38下的4個導孔插塞37、和包含設於此等導孔插塞37下的2個佈線36a之佈線層36。此等佈線36a通過2個金屬墊38的正下方而延伸於Y方向。各金屬墊38透過2個導孔插塞37而與此等佈線36a中的任一者電連接。 本實施方式的各金屬墊38雖具有可與4個導孔插塞37連接的尺寸，惟實際上僅與2個導孔插塞37連接。此等導孔插塞37排列於Y方向而被配置。此可使通過圖6的金屬墊38的正下方的佈線36a的X方向的寬變細。理由在於，各佈線36a上的導孔插塞37雖排列於Y方向而被配置，惟未排列於X方向而被配置，故各佈線36a的X方向的寬設定為可與1個導孔插塞37連接的程度的寬即充分。因此，在本實施方式，可使通過金屬墊38的正下方的佈線36a的寬變細，可使複數個佈線36a通過於各金屬墊38的正下方。據此，可使半導體裝置的積體度提升。 另外，在圖6方面雖2個佈線36a通過金屬墊38的正下方，惟亦可3個以上的佈線36a通過。 圖7為就第1實施方式的半導體裝置的構成進行繪示的電路圖。 圖7示出構成記憶體單元陣列11的複數個平面61、為此等平面61用而設的複數個橫列解碼器62、複數個SA/DL部63、複數個XDL部64、及複數個YLOG部65。圖7進一步示出串列電路66、I/O(輸入/輸出)電路67、低電壓產生電路71、高電壓產生電路72、橫列控制電路73、和直行控制電路74。此等位於陣列晶片1內的記憶體單元陣列11附近或電路晶片2內的邏輯電路內。圖7進一步示出含於本實施方式的半導體裝置中的控制器3。 各平面61由複數個記憶體單元、複數個字線WL、複數個位元線BL等構成。各橫列解碼器62對字線WL等的控制佈線施加控制電壓。如此的控制電壓之例為寫入電壓(VPRG)、消除電壓(VERASE)、中間電壓(VPASS)、源極電壓(VSL)等。各SA/DL部63為就讀出於位元線BL的資料進行檢測的感測放大器電路及資料鎖存電路。各XDL部64為儲存從SA/DL部63、I/O電路67發送的資料的資料鎖存電路。各YLOG部65將直行位址進行解碼，根據解碼結果選擇XDL部64內的鎖存電路。串列電路66提供在複數個平面61共用的串列匯流排等，I/O電路67在控制器3之間收受輸入信號、輸出信號。 低電壓產生電路71和高電壓產生電路72構成控制電壓產生電路，分別予以產生作為控制電壓而使用的低電壓和高電壓。橫列控制電路73和直行控制電路74分別實施涉及各平面61的橫列、直行的控制。 示於圖7的符號P示出配置示於圖4(a)、圖4(b)的金屬墊38、41之處之例。如示於圖7，示於圖4(a)、圖4(b)的金屬墊38、41配置於例如平面61內的位元線BL下、橫列解碼器62附近的字線WL下。 圖8為就第1實施方式的半導體裝置的構成進行繪示的平面圖。 圖8(a)示出貼合前的陣列晶片1，圖8(b)示出貼合前的電路晶片2。陣列晶片1具備4個記憶體單元陣列11、此等之階層構造部21及字線階面81、記憶體單元陣列11間的階面空間82、和接合墊(金屬墊46)用的墊區域83。電路晶片2具備4個周邊電路部84、此等的SA/YLOG部85及XFER區域86、周邊電路部84間的佈線區域87、和接合墊(金屬墊46)用的墊區域88。 圖8(a)及圖8(b)分別示出陣列晶片1上的複數個金屬墊41、和電路晶片2上的複數個金屬墊38。字線WL用的金屬墊41、38(圖4(a)參照)例如配置於字線階面81上、XFER區域86上。位元線BL用的金屬墊41、38(圖4(b)參照)例如配置於階層構造部21上、SA/YLOG部85上。 圖9為就第1實施方式的金屬墊38、41和字線WL的關係的一例進行繪示的剖面圖。 圖9如同圖1，示出陣列晶片1內的記憶體單元陣列11、階層構造部21、接觸插塞22、字佈線層23、電路晶片2內的基板15、電晶體31、閘極電極32等。 圖9如同圖4(a)進一步示出與字線WL電連接的3組金屬墊38、41。在各組的金屬墊38、41方面，金屬墊41經由複數個導孔插塞42、佈線層43、字佈線層23、及接觸插塞22而與字線WL電連接，金屬墊38經由複數個導孔插塞37、佈線層36、35、34、及接觸插塞33而與電晶體31電連接。 圖10為就第1實施方式的金屬墊38、41和位元線BL的關係的一例進行繪示的剖面圖。 圖10如同圖1般示出陣列晶片1內的記憶體單元陣列11、柱狀部CL、導孔插塞24、位元線BL、電路晶片2內的基板15、電晶體31、閘極電極32等。 圖10如同圖4(b)般進一步示出與位元線BL電連接的1組金屬墊38、41、其他3組金屬墊38、41。在與位元線BL電連接的金屬墊38、41方面，金屬墊41經由複數個導孔插塞42、佈線層43、位元線BL、複數個導孔插塞24而與複數個柱狀部CL電連接，金屬墊38經由複數個導孔插塞37、佈線層36、35、34、及接觸插塞33而與電晶體31電連接。 圖10的佈線層36包含與圖10的複數個金屬墊38電連接的複數個佈線36a和其他佈線36b。佈線36b實際上雖配置於在與圖10的YZ剖面不同的YZ剖面中與佈線36a相同的高度，惟為了說明的方便在圖10以點線表示。佈線36b如示於圖10般長長地延伸於Y方向。 佈線36b為例如配置在與位元線BL連接的佈線36a的附近的信號線。信號線之例為源極線。如參照圖6而說明，在本實施方式，可使通過金屬墊38的正下方的佈線36a的寬變細。因此，依本實施方式時，可將佈線36b配置於佈線36a的附近，例如可使佈線36b如同佈線36a般通過金屬墊38的正下方。據此，可使半導體裝置的積體度提升。 如以上，在本實施方式的1組金屬墊38、41，在金屬墊38的下表面設置1個以上的導孔插塞37，在金屬墊41之上表面設置1個以上的導孔插塞42，金屬墊41之上表面的導孔插塞42的個數比金屬墊38的下表面的導孔插塞37的個數多。因此，依本實施方式時，可適合地使因金屬墊38、41而起的半導體裝置的良率提升。 以上，雖說明數個實施方式，惟此等實施方式為作為範例提示者，非意圖限定發明的範圍者。在本說明書說明的新穎的裝置及方法能以其他各種的方式實施。此外，對在本說明書說明的裝置及方法的方式，在不脫離發明的要旨的範圍內，可進行各種的省略、置換、變更。申請專利範圍及與其均等的範圍應包含含於發明的範圍、要旨中的如此的方式、變形例。
1:陣列晶片 2:電路晶片 3:控制器 11:記憶體單元陣列 12:絕緣膜 13:層間絕緣膜 14:層間絕緣膜 15:基板 16:基板 21:階層構造部 22:接觸插塞 23:字佈線層 24:導孔插塞 31:電晶體 32:閘極電極 33:接觸插塞 34:佈線層 35:佈線層 36:佈線層 36a,36b:佈線 37:導孔插塞 38:金屬墊 41:金屬墊 42:導孔插塞 43:佈線層 44:佈線層 45:導孔插塞 46:金屬墊 47:鈍化膜 51:絕緣層 52:區塊絕緣膜 53:電荷存儲層 54:通道絕緣膜 55:通道半導體層 56:核心絕緣膜 61:平面(記憶體單元陣列) 62:橫列解碼器 63:SA/DL部 64:XDL部 65:YLOG部 66:串列電路 67:I/O電路 71:低電壓產生電路 72:高電壓產生電路 73:橫列控制電路 74:直行控制電路 81:字線階面 82:階面空間 83:墊區域 84:周邊電路部 85:SA/YLOG部 86:XFER區域 87:佈線區域 88:墊區域
[圖1]就第1實施方式的半導體裝置的構造進行繪示的剖面圖。 [圖2]就第1實施方式的柱狀部的構造進行繪示的剖面圖。 [圖3]就第1實施方式的半導體裝置之製造方法進行繪示的剖面圖。 [圖4(a)、(b)]就第1實施方式的金屬墊等的構造進行繪示的透視圖。 [圖5(a)～(d)]就第1實施方式的金屬墊等的構造進行繪示的平面圖。 [圖6]就第1實施方式的金屬墊與佈線的關係進行繪示的平面圖。 [圖7]就第1實施方式的半導體裝置的構成進行繪示的電路圖。 [圖8(a)、(b)]就第1實施方式的半導體裝置的構成進行繪示的平面圖。 [圖9]就第1實施方式的金屬墊與字線的關係的一例進行繪示的剖面圖。 [圖10]就第1實施方式的金屬墊與位元線的關係的一例進行繪示的剖面圖。
36:佈線層
36a:佈線
37:導孔插塞
38:金屬墊
41:金屬墊
42:導孔插塞
43:佈線層
43a:佈線
BL:位元線
WL:字線

Claims (9)

  1. 一種半導體裝置，其具備： 基板； 設於前述基板上的複數個電晶體； 設於前述電晶體之上方且與前述電晶體中的至少一者電連接的第1佈線層； 設於前述第1佈線層上的第1插塞； 設於前述第1插塞上的第1墊； 設於前述第1墊上的第2墊； 設於前述第2墊上的第2插塞； 設於前述第2插塞上的第2佈線層；和 設於前述第2佈線層之上方且與前述第2佈線層電連接的記憶體單元陣列； 其中，前述第2墊上的前述第2插塞的個數比前述第1墊下的前述第1插塞的個數多。
  2. 如請求項1的半導體裝置，其中，前述第2墊上的前述第2插塞的個數為前述第1墊下的前述第1插塞的個數的平方個。
  3. 如請求項1或2的半導體裝置，其中，前述第2插塞配置為正方形或長方形的格子狀。
  4. 如請求項3的半導體裝置，其中，前述第1插塞配置於與前述正方形或前述長方形中的任一者的邊平行的直線上。
  5. 如請求項1或2的半導體裝置，其中， 前述第1插塞設於前述第1佈線層內的相同的佈線上， 前述第2插塞設於前述第2佈線層內的相同的佈線下。
  6. 如請求項5的半導體裝置，其中，前述第2佈線層的厚度比前述第1佈線層的厚度厚。
  7. 如請求項5的半導體裝置，其中， 前述第1佈線層包含通過前述第1墊的正下方的2個以上的佈線， 前述第1墊透過前述第1插塞而與前述2個以上的佈線中的任一者電連接。
  8. 如請求項1或2的半導體裝置，其中，前述第2墊透過前述第2插塞而與設於前述基板之上方的字線或位元線電連接。
  9. 一種半導體裝置之製造方法，其包含： 在第1基板上形成複數個電晶體； 在前述電晶體之上方，形成與前述電晶體中的至少一者電連接的第1佈線層； 在前述第1佈線層上形成第1插塞； 在前述第1插塞上形成第1墊； 在第2基板上形成記憶體單元陣列； 在前述記憶體單元陣列之上方，形成與前述記憶體單元陣列電連接的第2佈線層； 在前述第2佈線層上形成第2插塞； 在前述第2插塞上形成第2墊；和 將設於前述第1基板上的前述第1墊、和設於前述第2基板上的前述第2墊貼合； 其中，前述第2墊上的前述第2插塞的個數比前述第1墊下的前述第1插塞的個數多。
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