TW201511229A - 半導體裝置之製造方法 - Google Patents

半導體裝置之製造方法 Download PDF

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Publication number
TW201511229A
TW201511229A TW103116523A TW103116523A TW201511229A TW 201511229 A TW201511229 A TW 201511229A TW 103116523 A TW103116523 A TW 103116523A TW 103116523 A TW103116523 A TW 103116523A TW 201511229 A TW201511229 A TW 201511229A
Authority
TW
Taiwan
Prior art keywords
film
conductor
vertical
layer
insulating film
Prior art date
Application number
TW103116523A
Other languages
English (en)
Chinese (zh)
Inventor
Nobuyuki Sako
Eiji Hasunuma
Keisuke Otsuka
Original Assignee
Ps4 Luxco Sarl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ps4 Luxco Sarl filed Critical Ps4 Luxco Sarl
Publication of TW201511229A publication Critical patent/TW201511229A/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/92—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by patterning layers, e.g. by etching conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)
TW103116523A 2013-05-09 2014-05-09 半導體裝置之製造方法 TW201511229A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013099519A JP2014220423A (ja) 2013-05-09 2013-05-09 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
TW201511229A true TW201511229A (zh) 2015-03-16

Family

ID=51867293

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103116523A TW201511229A (zh) 2013-05-09 2014-05-09 半導體裝置之製造方法

Country Status (3)

Country Link
JP (1) JP2014220423A (ja)
TW (1) TW201511229A (ja)
WO (1) WO2014181815A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113078103A (zh) * 2021-03-24 2021-07-06 长鑫存储技术有限公司 半导体器件的形成方法及半导体器件

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112309985A (zh) 2019-07-30 2021-02-02 三星电子株式会社 制造电容器和半导体器件的方法以及半导体器件和装置
KR20220059846A (ko) 2020-11-03 2022-05-10 삼성전자주식회사 배선 콘택 플러그들을 포함하는 반도체 메모리 소자
US11710642B2 (en) 2021-03-23 2023-07-25 Changxin Memory Technologies, Inc. Semiconductor structure and manufacturing method thereof
CN113078057B (zh) * 2021-03-23 2022-09-23 长鑫存储技术有限公司 半导体结构及其制作方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5646798B2 (ja) * 1999-11-11 2014-12-24 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体集積回路装置の製造方法
JP2013016632A (ja) * 2011-07-04 2013-01-24 Elpida Memory Inc 半導体装置及びその製造方法
JP2013048188A (ja) * 2011-08-29 2013-03-07 Elpida Memory Inc 半導体装置の製造方法
JP2013197133A (ja) * 2012-03-16 2013-09-30 Elpida Memory Inc 半導体装置及びその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113078103A (zh) * 2021-03-24 2021-07-06 长鑫存储技术有限公司 半导体器件的形成方法及半导体器件
CN113078103B (zh) * 2021-03-24 2022-09-02 长鑫存储技术有限公司 半导体器件的形成方法及半导体器件

Also Published As

Publication number Publication date
WO2014181815A1 (ja) 2014-11-13
JP2014220423A (ja) 2014-11-20

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