TW201511229A - Method of manufacturing a semiconductor device - Google Patents

Abstract

A method of manufacturing a semiconductor device includes forming on a semiconductor substrate a conductive layer including a protruding portion having an upper surface and a side surface; conformally and successively forming on the conductive layer a plate electrode layer, a mask layer, and a photoresist layer; patterning the photoresist layer to leave a part corresponding to the upper surface and the side surface of the protruding portion and to expose a part of the mask layer; etching the mask layer with the patterned photoresist layer used as a mask to remove the exposed part of the mask layer and to retreat an edge portion of the mask layer which portion is formed by the removal; and etching the plate electrode layer using as a mask the mask layer left after the etching.

Description

Semiconductor device manufacturing method

The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a semiconductor device in which a plate electrode and a plug to be electrically separated are disposed adjacent to each other.

FIG. 16 of Patent Document 1 discloses a semiconductor device having a memory cell range and a peripheral circuit range which are adjacent to each other on one surface of a semiconductor substrate, and a method of manufacturing the same.

In the memory cell range of the semiconductor device of Patent Document 1, a plurality of capacitors are formed, and the plurality of capacitors have a common upper electrode. Further, a plate electrode was formed so as to cover the upper surface and the side surface of the upper electrode. The edge portion of the plate electrode forms a weir portion that extends toward the side of the peripheral circuit. Further, an interlayer insulating film in which a stepped portion between the range of the memory cell and the peripheral circuit range is formed is formed as a coated electrode. In the peripheral circuit range, a plug that penetrates the interlayer insulating film and reaches the lower wiring is formed.

In addition, with regard to Patent Document 2, it is disclosed that there are plural numbers. A method of manufacturing a semiconductor device supporting a film.

[Previous Technical Literature] [Patent Document]

[Patent Document 1]: JP-A-2013-16632 (especially FIG. 16)

[Patent Document 2]: JP-A-2013-30557

The plate electrodes formed in the range of the memory cells and the plugs formed in the range of the peripheral circuits are required to be electrically separated from each other. However, with the miniaturization of the semiconductor device, the distance between the edge portion of the plate electrode (the beak portion) and the plug of the peripheral circuit range is reduced, and a short circuit occurs. In other words, in order to ensure the insulation of the plate electrode from the plug, the miniaturization of the semiconductor device is hindered.

The method of manufacturing the semiconductor device described in Patent Documents 1 and 2 does not fully suggest the existence of such a problem and the means for solving the problem.

A semiconductor device according to an embodiment of the present invention includes: a conductor layer constituting a side surface of a memory pad formed on a semiconductor substrate; and a photomask film provided on a side surface of the conductor layer, The bottom surface of the photomask film is located at a position away from the semiconductor substrate in a first direction perpendicular to the semiconductor substrate, and at least a portion of a bottom surface of the photomask film is orthogonal to The second direction of the first direction is higher than the position of the bottom surface of the conductor layer from the memory pad.

In addition, a semiconductor guide according to another embodiment of the present invention The manufacturing method of the body device is characterized in that a conductive layer including a protrusion having an upper surface and a side surface is formed over the semiconductor substrate, and a plate electrode layer, a mask layer and a mask layer are formed in sequence over the conductive layer. The photoresist layer is formed by patterning the photoresist layer and exposing one of the mask layers to the portion of the front surface and the side surface of the protruding portion of the photoresist layer, and patterning the mask layer The photoresist layer is used as a photomask to etch the photomask layer, and the exposed portion of the photomask layer is removed, and the edge portion of the photomask layer formed therethrough is retreated, and the photomask layer remaining after etching is used as The reticle is etched while the aforementioned plate electrode layer is etched.

The etching of the exposed portion of the mask layer is removed, so that the edge portion of the mask layer formed at this time is retreated. As a result, it is possible to reduce the edge portion (the ridge portion) of the plate electrode layer remaining after the etching of the plate electrode layer by using the photomask layer remaining after the etching as a mask.

10‧‧‧Memory unit range

20‧‧‧ peripheral circuit range

101‧‧‧Semiconductor substrate

103‧‧‧Component separation range

105‧‧‧ buried in the gate line

107‧‧‧Gap insulation film

109‧‧‧1st interlayer insulating film

111‧‧‧Capacitive contact plug

113‧‧‧Circuit wiring layer

115‧‧‧ nitride film

117‧‧‧1st cylinder interlayer film

119‧‧‧1st beam nitride film

121‧‧‧Second cylinder interlayer film

123‧‧‧2nd beam nitride film

125‧‧‧Amorphous germanium (α-Si) layer

127‧‧‧ Plasma Oxide Film

129‧‧‧Amorphous carbon (α-C) layer

131‧‧‧Photoresist film

133‧‧‧ openings

135‧‧‧ cylinder bore

137‧‧‧Metal film (titanium nitride (TiN) film)

139‧‧‧ lower electrode

141‧‧‧ Plasma Oxide Film

143‧‧‧Photoresist film

145‧‧‧ openings

147‧‧‧ openings

149‧‧‧2nd beam

151‧‧‧ openings

153‧‧‧1st beam

155‧‧‧Capacitive insulation film

157‧‧‧TiN film

157A‧‧‧Vertical 3rd conductor

157B‧‧‧3rd conductor part

157a‧‧‧ side of the edge

159‧‧‧B-SiGe film

159A‧‧‧Vertical second conductor

159B‧‧‧ horizontal second conductor

159a‧‧‧ side of the edge

159b‧‧‧ bottom

159c‧‧‧ side

159d‧‧‧ side

161‧‧‧W film

161A‧‧‧Vertical 1st conductor

161B‧‧‧Level 1st conductor

161a‧‧‧ side of the edge

161b‧‧‧ bottom

161c‧‧‧ side

161d‧‧‧ side

163‧‧‧Photomask oxide film

163A‧‧‧Vertical Shield Insulation Film Division

163B‧‧‧ horizontal mask insulating film

163a‧‧‧ side

163b‧‧‧ bottom

163c‧‧‧ side

163d‧‧‧ side

165‧‧‧Photoresist film mask

167‧‧‧ corner

169‧‧‧ plate electrode

171‧‧‧Second interlayer insulating film

173‧‧‧1st plug

175‧‧‧2nd plug

177‧‧‧Upper wiring

179‧‧‧Protective layer

200‧‧‧ side

201‧‧‧ side

Figure 1 is a diagram for explaining the problem of the related technology reviewed by the inventors.

Fig. 2 is an enlarged view of a dotted line frame C in Fig. 1.

Fig. 3 is a plan view showing a part of the manufacturing method of the semiconductor device according to the first embodiment of the present invention.

Figure 4 is a cross-sectional view taken along line Y-Y' of Figure 3.

Figure 5 is a plan view for illustrating the work continuing in Figures 3 and 4.

Figure 6 is a cross-sectional view taken along line Y-Y' of Figure 5.

Figure 7 is a plan view for illustrating the work continuing in Figures 5 and 6.

Figure 8 is a cross-sectional view taken along line Y-Y' of Figure 7.

Figure 9 is a plan view for explaining the work continuing in Figures 7 and 8.

Figure 10 is a cross-sectional view taken along line Y-Y' of Figure 9.

Figure 11 is a plan view for explaining the work continuing in Figures 9 and 10.

Figure 12 is a cross-sectional view taken along line Y-Y' of Figure 11.

Figure 13 is a plan view for explaining the work continuing in Figures 11 and 12.

Figure 14 is a cross-sectional view taken along line Y-Y' of Figure 13.

Figure 15 is a plan view for explaining the work continuing in Figures 13 and 14.

Figure 16 is a cross-sectional view taken along line Y-Y' of Figure 15.

Figure 17 is a plan view for explaining the work continuing in Figures 15 and 16.

Figure 18 is a cross-sectional view taken along line Y-Y' of Figure 17.

Figure 19 is a plan view for explaining the work continuing in Figures 17 and 18.

Figure 20 is a cross-sectional view taken along line Y-Y' of Figure 19.

Figure 21 is an enlarged view of a dotted line frame C of Figure 20;

Figure 22 is a plan view for illustrating the work continuing with Figures 19-21.

Figure 23 is an enlarged view of the inside of the chain line frame C of Figure 22.

Figure 24 is a cross-sectional view for explaining the work continued in Figures 22 and 23.

Figure 25 is an enlarged view of a dotted line frame C of Figure 24;

Figure 26 is a cross-sectional view for explaining the work continued in Figures 24 and 25.

Figure 27 is an enlarged view of a dotted line frame C of Figure 26;

Figure 28 is a cross-sectional view for explaining the work continued in Figures 26 and 27.

Figure 29 is an enlarged view of a dotted line frame C in one of Figure 28.

Figure 30 is a plan view for explaining the work continuing in Figures 28 and 29.

Figure 31 is a cross-sectional view taken along line Y-Y' of Figure 30.

Figure 32 is an enlarged view of the inside of the chain line frame C of Figure 31.

Fig. 33 is a view showing a modification of the semiconductor device according to the first embodiment, and corresponds to an enlarged view of a portion in a chain line frame C of Fig. 31;

Fig. 34 is a cross-sectional view showing another example of the amount of retreat of the W film and the B-SiGe film.

Figure 35 is an enlarged view of a dotted line frame C in one of Figure 34;

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

First, in order to facilitate the understanding of the present invention, the related art reviewed by the inventors will be described.

1 is a view showing a state in which a process of forming a capacitor in a memory cell range 10 by a manufacturing method of a related semiconductor device is completed. In addition, FIG. 2 is an enlarged view of one of the dotted line frames C shown in FIG.

In FIG. 1, the right side indicates the memory unit range 10, and the left side indicates the peripheral circuit range 20. However, for the memory cell range 10, a plurality of memory cell pads are formed by placing a specific interval, and FIG. 1 is a part of one of them.

As shown in FIGS. 1 and 2, a crown-shaped lower electrode 139 is formed in a plurality of memory cell ranges 10 (in each memory cell pad). Further, a capacitor insulating film 155 is formed on the surface of the plurality of lower electrode 139, and a TiN film 157 is formed thereon (not shown in FIG. 1). Further, while covering the surface of the TiN film 157, the B-SiGe film 159 is formed by being embedded around the lower electrode 139, and the W film 161 is formed to cover the upper surface and the side surface thereof.

Here, the formation of the capacitor insulating film 155, the TiN film 157, the B-SiGe film 159, and the W film 161 is performed on the semiconductor substrate 101. The exposed surface of the structure is carried out in a comprehensive manner. That is, these film systems are also formed in an unnecessary range. Therefore, in order to remove these films from an unnecessary range (to electrically separate a plurality of memory pads), a mask oxide film 163 is formed on the W film 161.

However, in the present embodiment, the "memory pad" mainly refers to a structure including a plurality of lower electrodes 139 formed in a specific range of the semiconductor substrate 101 and common upper electrodes (155, 157), but There is a plate electrode 169 which is formed by covering the upper electrode and is called a memory pad.

The formation of the mask oxide film 163 is also performed in the entirety of the W film 161. The patterning of the mask oxide film 163 must be performed as much as possible without removing the mask oxide film 163 formed at the corner 167 of the memory pad. In order to dry the etching process later, the W film 161 or the like is etched at the corner portion 167 to damage the function of the capacitor. In the related art, the formation of the patterned photoresist film for the mask oxide film 163 is performed, and at the corner portion 167, the photoresist film is formed to have a specific thickness. As a result, the photoresist film is also thickened on the mask oxide film 163 formed on the side wall of the memory pad. When the mask oxide film 163 is etched by the photoresist film having such a thickness, the edge portion of the mask oxide film 163 is greatly protruded toward the peripheral circuit region 20 side as shown in FIG. 2 . As a result, the edge portion of the plate electrode 169 or the like formed by etching the W film 161 is also greatly protruded toward the peripheral circuit range 20 side.

However, in FIGS. 1 and 2, the edge portion of the plate electrode 169 or the like is formed so as to overlap the peripheral wiring layer 113 in the vertical direction, but It is necessary to arrange the peripheral wiring layer 113 away from the memory cell range 10 without causing such overlap. Therefore, the miniaturization of the semiconductor device is hindered.

Next, a method of manufacturing a semiconductor device according to a first embodiment of the present invention will be described with reference to FIG. 3 to FIG.

Fig. 3 is a plan view showing a state in which a cylinder hole pattern is formed in order to form a photoresist film for use in a cylinder hole of a lower electrode of a capacitor. 4 is a cross-sectional view taken along line Y-Y' of FIG. 3. However, the right side of FIG. 4 corresponds to one portion of the memory cell range, and the left side corresponds to one of the peripheral circuit ranges.

First, as shown in FIG. 4, the element isolation range 103 is formed on one surface side of the semiconductor substrate 101 by a known method, and the gate line 105, the gap insulating film 107, and the like are buried. Further, an impurity diffusion layer (not shown) is formed on one surface side of the semiconductor substrate 101, or is connected to the underlying wiring layer, and a first interlayer insulating film 109 covering the same is formed. Further, the capacitor contact plug 111 and other contact plugs (not shown) are formed through the first interlayer insulating film 109. In addition, the peripheral wiring layer 113 is formed on the first interlayer insulating film 109, and the tantalum nitride film 115 which is etch-stopped for dry etching at the time of cylinder hole formation is formed over the entire surface.

Then, the first cylinder interlayer film 117, the first beam nitride film 119, the second cylinder interlayer film 121, and the second beam nitride film 123 are sequentially formed on the tantalum nitride film 115.

Further, on the second beam nitride film 123, an amorphous germanium (α-Si) layer 125 which is a photomask at the time of formation of the cylinder bore is sequentially formed, and the plasma is formed. The oxide film 127, the amorphous carbon (α-C) layer 129, and the photoresist film 131.

Next, a hole pattern in which a plurality of openings 133 are formed at a predetermined interval is formed in the photoresist film 131 by photolithography.

However, as the semiconductor substrate 101, for example, a p-type single crystal germanium substrate can be used.

A portion of the buried gate line 105 formed in the memory cell range 10 and a diffusion layer (not shown) constitute a transistor. In addition, the buried gate line 105 also functions as a character. The capacitor contact plug 111 is connected to a diffusion line (not shown) and is connected to a bit line (not shown).

The tantalum nitride film 115 is formed on the semiconductor substrate 101 in a total thickness of 50 nm by, for example, a CVD (Chemical Vapor Deposition) method.

The first cylinder interlayer film 117 is, for example, an impurity-containing yttrium oxide film, and is formed to have a thickness of 450 nm by a CVD method. As the impurity-containing cerium oxide film, BPSG (Boro-Phospho Silicate Glass) containing boron (B) or phosphorus (P) can be used. The impure substance containing the ruthenium oxide film is fast because the etching rate through the etching solution is fast, and it is easy to remove it after the subsequent process.

The first beam nitride film 119 is formed to have a thickness of, for example, 50 nm by a CVD method. The first beam nitride film 119 may be formed by a sputtering method or an HDP (High Density Plasma) method. The film formed by the sputtering method or the HDP method has a high density and can be formed by a CVD method. The film reduces the etch rate through the solution.

The second cylinder interlayer film 121 and the second beam nitride film 123 are Each of the first cylinder interlayer film 117 and the first beam nitride film 119 is formed to have a thickness of, for example, 450 nm and 50 nm.

The α-Si layer 125 is formed, for example, by a CVD method. to make. Further, the plasma oxide film 127 is formed by a plasma CVD method. Further, the α-C layer 129 is formed, for example, by a CVD method.

a shape formed in the plurality of openings 133 of the photoresist film 131 The position is formed in the memory cell range 10 corresponding to the capacitor formation position. The arrangement of the openings is not limited to the example of Fig. 3, but may be arranged as the most dense. In this case, the diameter of the opening is 50 to 150 nm, and the closest interval between the adjacent openings can be 30 to 50 nm.

Next, dry etching is used to form the photoresist film 131. The pattern is transferred to the α-C layer 129, the plasma oxide film 127, and the α-Si layer 125. Further, when the plasma-oxide film 127 and the α-Si layer 125 are dry-etched as a mask by the α-C layer 129, as shown in FIGS. 5 and 6, a nitride film penetrating through the second beam is formed. 123, the second cylinder interlayer film 121, the first beam nitride film 119, the first cylinder interlayer film 117, and the tantalum nitride film 115 reach the cylinder hole 135 of the capacitor contact plug 111.

Next, as shown in FIG. 7 and FIG. 8, it will become the lower electrode. A metal film (titanium nitride (TiN) film) 137 is formed on the exposed surface including the inner surface of the cylinder bore 135. For the formation of the metal film 137, it can be used CVD method or ALD (Atomic Layer Deposition) method. The total thickness of the metal film 137 and the film thickness of the capacitor insulating film (155) formed later is selected to be smaller than 1/2 of the diameter of the cylinder bore 135. The film thickness of the metal film 137 is, for example, 10 nm.

Then, the metal film 137 is completely etched back, and in the cylinder hole 135 While the metal film 137 remains, the metal film 137 on the second beam nitride film 123 is removed. For this etch back, a dry etcher using chlorine containing plasma can be utilized. Thereby, the inner surface of the cylinder hole 135 is covered and connected to the upper surface of the capacitor contact plug 111, and the lower electrode (139) formed by the metal film 137 is formed. However, the first beam nitride film 119 and the second beam nitride film 123 are connected to the outer peripheral surface of the lower electrode (139).

Next, as shown in FIG. 9 and FIG. 10, the plasma oxide film is used. 141, the film is formed on the entire surface of the second beam nitride film 123. The plasma oxide film 141 is formed to have a thickness of, for example, 150 nm by a plasma CVD method. In this method, the plasma oxide film 141 is formed inside the lower electrode 139 and is formed to block the opening of the lower electrode 139 because of poor coverage.

Next, a photoresist film is formed on the plasma oxide film 141. 143. Between these, the antireflection film may be interposed. The photoresist film 143 is formed, for example, by a spin coating method. Thereafter, an opening portion 145 having a specific pattern is formed on the photoresist film 143. At this time, the photoresist film 143 positioned at the peripheral circuit range 20 is also removed.

Next, the pattern of the photoresist film 143 is dried by dry etching, Transfer to the plasma oxide film 141. And, by making the plasma oxide film 141 As a dry etching of the photomask, as shown in FIGS. 11 and 12, an opening 147 is formed in the second beam nitride film 123. Further, the second beam nitride film 123 positioned at the peripheral circuit range 20 is completely removed. Thereby, the second beam nitride film 123 constitutes the second beam 149 that supports the lower electrode 139.

Next, as shown in FIG. 13 and FIG. 14 , the second cylinder interlayer film 121 is completely removed by wet etching using hydrofluoric acid (HF) as an etching solution.

Then, the specific range of the first beam nitride film 119 is dry-etched by self-alignment of the pattern of the second beam, and as shown in FIGS. 15 and 16, the first beam nitride film 119 is opened. 151. Further, the first beam nitride film 119 positioned at the peripheral circuit range 20 is completely removed. Thus, the first beam nitride film 119 constitutes the first beam 153 that supports the lower electrode 139.

Next, the first cylinder interlayer film 117 is completely removed by wet etching using hydrofluoric acid (HF) as shown in FIGS. 17 and 18 .

As a result of the above, the lower electrode 139 formed in the memory cell range 10 is connected to the first beam 153 and the second beam 149, and the beams are connected to each other. Further, the outer wall surface of the lower electrode 139 is completely exposed except for the portions connected to the first beam 153 and the second beam 149. Further, the upper surface of the tantalum nitride film 115 is entirely exposed except for the portion where the lower electrode 139 is formed.

Next, as shown in FIG. 19, FIG. 20 and FIG. 21, the capacitor insulating film 155 is formed over the entire exposed surface including the inner surface and the outer wall surface of the lower electrode 139. The capacitor insulating film 155 is also for the first beam 153 and the second beam The surface of 149 and the tantalum nitride film 115 are also formed. The capacitor insulating film 155 is composed of a laminated film made of a zirconia film, an aluminum oxide film, a titanium oxide film, a yttrium oxide film, a yttrium oxide film, or a plurality of films. Any film can be formed using the ALD method. The film thickness of the capacitor insulating film 155 is, for example, 6 nm.

Next, a TiN film that will become part of the upper electrode 157 is formed on the capacitor insulating film 155. Thereafter, it is coated on the TiN film 157, and is buried in the space between the lower electrodes 139, and a B-SiGe film 159 which is a part of the upper electrode is formed. The B-SiGe film 159 constitutes a conductive layer including protrusions having upper and lower sides. The TiN film 157 and the B-SiGe film 159 can be formed by using a CVD method at the same time.

Figure 21 is an enlarged view of a dotted line frame C of Figure 20; As shown in FIG. 21, on the surface of the lower electrode 139, a capacitor insulating film 155, a TiN film 157, and a B-SiGe film 159 are sequentially laminated.

Next, as shown in FIG. 22 and FIG. 23, the coated B-SiGe is present. The surface of the film 159 is entirely formed by forming a W (tungsten) film 161 which becomes a plate electrode, and further, a mask oxide film 163 is formed thereon. The W film 161 is formed by a CVD method or a sputtering method, for example, to have a thickness of 100 nm. The W film 161 is in the memory cell range 10 and is overlaid on the upper surface and the side surface of the upper memory pad (the same surface of the B-SiGe film 159) and on the upper surface of the peripheral circuit range 20. However, between the W film 161 and the B-SiGe film 159, a B-Si film having a thickness of about 5 nm may be interposed as an adhesion layer.

Next, as shown in FIG. 24 and FIG. 25, the mask oxide film A photoresist mask film 165 is formed on 163. The photoresist mask film 165 is formed by a spin coating method to form a photoresist film in its entirety, and then patterned into a specific pattern via photolithography. The pattern of the photoresist mask film 165 is defined by dividing the W film 161 or the like into a memory pad unit. The photoresist mask film 165 is formed on the upper surface of the memory pad, but may be formed on the side surface of the memory pad in order to avoid etching of the corner portion 167. Therefore, the edge portion of the photoresist mask film 165 inevitably protrudes from the peripheral circuit range 20 as shown in the one-dot chain line C in FIG. 24 and as shown in FIG.

Next, as shown in FIG. 26 and FIG. 27, dry etching the mask oxygen Film 163. At this time, not only the mask oxide film 163 is exposed but also the photoresist mask film 165 is etched, and dry etching is performed. The edge portion of the photoresist mask film 165 is thinner than the portion formed on the protruding portion via the previous photo lithography. Therefore, the edge portion of the photoresist mask film 165 is gradually retreated by this dry etching. As a result, a portion of the mask oxide film 163 coated on the photoresist mask film 165 is again exposed, and a portion of the mask oxide film 163 which is newly exposed is additionally etched. As a result, the front end position of the edge portion of the mask oxide film 163 is lower than the front end position of the edge portion when the photoresist mask film 165 is formed, and is retracted to the memory unit range 10 side as indicated by an arrow D.

For this dry etching, as the etching gas, a mixed gas of CF ₄ and O ₂ can be used. The flow ratio of these gases is adjusted so that not only the mask oxide film 163 but also the photoresist mask film 165 is etched. In addition, EPD (End Point Detection) is performed until the etching of the mask oxide film 163 is completed, and the etching is continued until the etching of the mask oxide film 163 is resumed. That is, when it is determined that the exposed portion of the mask oxide film 163 is removed, the etching is not completed and the etching is continued. Thus, the mask oxide film 163 having the corner portion 167 is soon exposed, and the etching of the mask oxide film 163 is detected again. At this time, by the etcher who has finished the mask oxide film 163, the undesired etching (etching) of the mask oxide film 163 at the corner portion 167 of the memory pad can be suppressed to a minimum, and the mask oxide film 163 can be made small. The amount of protrusion at the edge (Fig. 27) is reduced.

Then, after removing the photoresist mask film 165, select the pair In the mask oxide film 163, the chlorine having a high selectivity contains a gas plasma, and the W film 161, the B-SiGe film 159, and the TiN film 157 are dry-etched. At this time, the etching proceeds in an isotropic manner, and the bias voltage is lowered as much as possible. Thus, as shown in FIG. 28 and FIG. 29, the edge portions of the W film 161, the B-SiGe film 159, and the TiN film 157 can be retracted from the edge of the mask oxide film 163 as indicated by an arrow E. On the side of the memory unit range of 10 sides. The capacitor insulating film 155 made of a metal oxide film is also etched at the same time, but the capacitor insulating film 155 may remain even if it is an insulating film. By this etching, the W film 161 is a plate electrode 169 which is separated into memory cell units.

For the lower electrode included in the plural of each memory pad The conductor layer formed of a laminated film of the TiN film 157 and the B-SiGe film 159 and the W film 161 is provided on the outer side of the outermost lower electrode.

The bottom surface of the mask oxide film 163 is a conductor formed of a laminated film of a W film (first conductive film) 161, a B-SiGe film (second conductive film) 159, and a TiN film (third conductive film) 157. The bottom of the layer, about the Z side The direction (the vertical direction of the drawing) is away from the semiconductor substrate 101. Further, at least a part of the bottom surface of the mask oxide film 163 is located on the bottom surface of the conductor layer formed by the laminated film of the W film 161, the B-SiGe film 159 and the TiN film 157, and the memory pad is used in the Y direction. The side 161d) of the membrane 161 is away from the position (left side of the figure).

However, in the examples shown in FIGS. 28 and 29, the mask oxygen The film 163, the W film 161, the B-SiGe film 159, and the TiN film 157 each have a crotch portion (a portion surrounding the opposite broken line F of FIG. 9), and the front end of the crotch oxide film 163 is present in the W The front end of the film 161, the B-SiGe film 159 and the TiN film 157 is away from the memory pad (side surface 161d of the W film 161) (the left side of the figure). However, the mask oxide film 163 does not necessarily have to have a crotch portion, and the side surface thereof may be substantially flat. In this case, the side surface of the mask oxide film 163 is present at the tip end of the top portion of the TiN film 157, and the conductor layer is etched away from the position of the memory pad (side surface 161d of the W film 161). At this time, the W film 161 and the B-SiGe film 159 may or may not have a crotch portion. The W film 161 and the B-SiGe film 159 have a crotch portion, and the front end thereof substantially coincides with the tip end of the crotch portion of the TiN film 157 with respect to the Y direction. In other words, the front ends of the W film 161, the B-SiGe film 159, and the top portion of the TiN film 157 are formed between the mask oxide film 163 and the semiconductor substrate 101 to form a substantially flat side surface. The W film 161 does not have a crotch portion, that is, the W film 161 has a flat side surface, and the front ends of the B-SiGe film 159 and the TiN film 157 are aligned on the side surface of the W film 161. Alternatively, the B-SiGe film 159 may have a substantially flat side surface. In this case, the bottom surface of the W film 161 is about The Z direction may be the same as the bottom surface of the mask oxide film 163.

Then, as shown in FIG. 30, FIG. 31, and FIG. 32, the second interlayer insulating film 171 is formed over the entire surface as a step difference between the peripheral circuit range 20 and the memory cell range 10, and is flattened thereon. . As the second interlayer insulating film 171, a ruthenium oxide film formed by a CVD method can be used. The film thickness of the second interlayer insulating film 171 is the lowest surface position at the time of formation, and is higher than the upper surface of the plate electrode 169, for example, 1500 nm.

Next, the first plug 173 that has penetrated the second interlayer insulating film 171, reaches the plate electrode 169, and reaches the second plug 175 that reaches the peripheral wiring layer 113. In addition, a protective layer 179 which is buried around the upper wiring 177 is formed on the second interlayer insulating film 171 while being connected to the upper wiring 177 of the first plug 173 and the second plug 175. The semiconductor device of the present embodiment is completed by the above manufacturing method.

As shown in FIG. 32, in the semiconductor device of the present embodiment, the vertical mask insulating film portion 163A extending in the first direction (Z direction) perpendicular to the surface of the semiconductor substrate is formed in the lower end portion of the peripheral side surface of the memory pad. And a photomask insulating film formed by the horizontal mask insulating film portion 163B which is in contact with the bottom side surface of the vertical mask insulating film portion 163A and protrudes in the second direction (Y direction) horizontal to the surface of the semiconductor substrate, and has a mask oxidation Membrane 163. In addition, the semiconductor device has a vertical first conductor portion 161A extending in the first direction and a bottom side surface contacting the vertical first conductor portion 161A as being contacted with one side surface 163c of the vertical mask insulating film portion 163A. The upper surface is in contact with the reticle insulating film (the reticle oxide film 163) The bottom surface 163b protrudes from the W film 161 of the first conductor film formed by the horizontal first conductor portion 161B in the second direction. Further, the semiconductor device is formed so as to be in contact with the side surface 161c of the vertical first conductor portion 161A and extend to the vertical second conductor portion 159A in the first direction and the bottom side surface of the vertical second conductor portion 159A. The second conductor film formed by the horizontal second conductor portion 159B that is in contact with the bottom surface 161b of the horizontal first conductor portion 161B and protrudes in the second direction has a B-SiGe film 159. Further, the semiconductor device has a vertical third conductor portion 157A extending in the first direction and a bottom side surface contacting the vertical third conductor portion 157A as a contact with the one side surface 159c of the vertical second conductor portion 159A, and the upper surface thereof Then, the third conductor film formed by the horizontal third conductor portion 157B protruding in the second direction is in contact with the bottom surface 159b of the second conductor film (B-SiGe film 159), and has a TiN film 157. Further, the edge portion side surface 161a of the horizontal first conductor portion 161B and the edge portion side surface 159a of the horizontal second conductor portion 159B and the edge portion side surface 157a of the horizontal third conductor portion 157B are attached to the mask insulating film (mask oxide film). The space below the bottom surface 163b of 163) constitutes the side surface 200 that is flattened in the first direction. Further, the side surface 200 is notched to the memory cell range side with respect to the side surface 163a of the photomask insulating film (the mask oxide film 163).

In addition, the mask oxidation performed at the stage of Figs. 26, 27 In the etching of the film 163, the etching rate in the horizontal direction of the mask oxide film 163 is enhanced by the conditions of the isotropic etching, so that the shoulder of the mask oxide film at the pad end can be prevented from being damaged at the same time. The slit of the conductor film. Thereby, the configuration shown in Fig. 33 is obtained.

That is, the semiconductor device shown in FIG. 33 is in the memory pad. The lower end portion of the peripheral side surface has a mask insulating film (mask oxide film 163) formed by a vertical mask insulating film portion 163A extending in a first direction (Z direction) perpendicular to the surface of the semiconductor substrate. In addition, the semiconductor device has a W film 161 which is a first conductor film formed by the vertical first conductor portion 161A extending in the first direction as a side surface 163c of the vertical mask insulating film portion 163A. Further, the semiconductor device is formed so as to be in contact with the side surface 161c of the vertical first conductor portion 161A and extend to the vertical second conductor portion 159A in the first direction and the bottom side surface of the vertical second conductor portion 159A. The second conductor film formed by the horizontal second conductor portion 159B that is in contact with the bottom surface 161b of the vertical first conductor portion 161A and protrudes in the second direction has a B-SiGe film 159. Further, the semiconductor device has a vertical third conductor portion 157A extending in the first direction and a bottom side surface contacting the vertical third conductor portion 157A as a contact with the one side surface 159c of the vertical second conductor portion 159A, and the upper surface thereof Then, the third conductor film formed by the horizontal third conductor portion 157B protruding in the second direction is in contact with the bottom surface 159b of the second conductor film (B-SiGe film 159), and has a TiN film 157. Further, the side surface 161d of the vertical first conductor portion 161A and the edge side surface 159a of the horizontal second conductor portion 159B and the edge side surface 157a of the horizontal third conductor portion 157B are attached to the mask insulating film (mask oxide film 163). The space below the bottom surface 163b constitutes the side surface 200 that is flattened in the first direction. Further, the side surface 200 is notched to the memory cell range side with respect to the side surface 163d of the photomask insulating film (the mask oxide film 163).

Furthermore, from the stage of FIG. 33, the W film 161 is continued, The isotropic etching of the B-SiGe film 159 and the TiN film 157 is as shown in Figs. 34 and 35, and the W film 161, the B-SiGe film 159, and the TiN film 157 are provided as shown in Figs. 32 and 33. , is more regressed to the memory unit range 10 side.

That is, the semiconductor device shown in FIG. 35 is in the memory pad. The lower end portion of the peripheral side surface has a mask insulating film (mask oxide film 163) formed by a vertical mask insulating film portion 163A extending in a first direction (Z direction) perpendicular to the surface of the semiconductor substrate. Further, the semiconductor device is in contact with one surface side 163c of the vertical mask insulating film portion 163A, and has a bottom surface 161b which is flattened to the bottom surface 163b of the vertical mask insulating film 163A, and has a vertical first conductor portion 161A extending in the first direction. The W film 161 of the first conductor film formed. Further, the semiconductor device has a B-SiGe film 159 as a second conductor film formed by the vertical second conductor portion 159A extending in the first direction in contact with one side surface 161c of the vertical first conductor portion 161A. Further, the semiconductor device has a vertical third conductor portion 157A extending in the first direction and a bottom side surface contacting the vertical third conductor portion 157A as a contact with the one side surface 159c of the vertical second conductor portion 159A, and the upper surface thereof Then, the third conductor film formed by the horizontal third conductor portion 157B protruding in the second direction is in contact with the bottom surface 159b of the second conductor film (B-SiGe film 159), and has a TiN film 157. Further, the side surface 159d of the vertical second conductor portion 159A and the edge side surface 157a of the horizontal third conductor portion 157B are formed in a space below the bottom surface 163b of the photomask insulating film (the mask oxide film 163). Side of the first direction 201. Further, the side surface 201 is notched to the memory cell range side with respect to the side surface 163d of the photomask insulating film (the mask oxide film 163).

However, in Fig. 35, the second conductor film is formed, that is, The side surface 159d of the B-SiGe film 159 is formed so as to be in the second direction until it is exposed (consistent with one side surface 161c of the vertical mask insulating film portion 163A), but the surface of the TiN film 157 which is the upper electrode is exposed as a slit. It is not ideal. The capacitor located at the end has a problem of being damaged by etching and causing deterioration in characteristics. Accordingly, it is not preferable to excessively use the B-SiGe film 159 as a slit.

In the present embodiment, the W film of the plate electrode 169 is formed. In the etching of the mask oxide film 163 which is the etching mask of 161, etching is performed so that the edge portion thereof retreats. Further, when the W film 161 is etched, it is etched in an isotropic manner and etched. Thereby, the second plug 175 formed in the peripheral circuit range 20 and the shortest distance Lmin (see FIG. 31) formed in the plate electrode 169 of the memory cell range 10 can be enlarged. Therefore, according to the present embodiment, it is possible to correspond to a more subtle semiconductor device.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the gist of the present invention. change.

The present application claims the priority of Japanese Patent Application No. 2013-99519, filed on May 9, 2013, the entire disclosure of which is incorporated herein.

113‧‧‧Circuit wiring layer

115‧‧‧ nitride film

139‧‧‧ lower electrode

155‧‧‧Capacitive insulation film

157‧‧‧TiN film

159‧‧‧B-SiGe film

161‧‧‧W film

161d‧‧‧ side

163‧‧‧Photomask oxide film

169‧‧‧ plate electrode

Claims (20)

A semiconductor device comprising: a conductor layer constituting a side surface of a memory pad formed on a semiconductor substrate; and a photomask film provided on a side surface of the conductor layer, wherein a bottom surface of the photomask film is perpendicular to The first direction of the semiconductor substrate is located farther from the semiconductor substrate than the bottom surface of the conductor layer, and at least a portion of the bottom surface of the photomask film is located in a second direction orthogonal to the first direction, The bottom surface of the conductor layer is away from the aforementioned memory pad. The semiconductor device according to claim 1, wherein each of the conductor layer and the photomask film is provided at a bottom portion thereof, and has a crotch portion protruding from an outer side of the memory pad in the second direction, and the photomask film The front end of the crotch portion is located in the second direction, and is located away from the front end of the end portion of the conductor layer from the memory pad. The semiconductor device according to claim 2, wherein the conductor layer is formed by laminating the first, second, and third conductor films. The semiconductor device according to claim 1, wherein the photomask film has a substantially flat side surface. The semiconductor device according to claim 4, wherein the conductor layer is formed by laminating the first, second, and third conductor films. The semiconductor device according to claim 5, wherein the first, the second, and the third conductor film are formed as described above The first direction is a flat side surface between the bottom surface of the photomask film and the semiconductor substrate. The semiconductor device according to claim 5, wherein at least one of the first, second, and third conductor films has a substantially flat side surface. The semiconductor device according to claim 5, wherein the first and second conductive films have substantially flat sides. A semiconductor device characterized in that a lower end portion of a peripheral side surface of a memory pad formed on a semiconductor substrate has a vertical mask insulating film portion extending in a first direction perpendicular to a surface of the semiconductor substrate, and is in contact with the semiconductor device a reticle insulating film formed by a horizontal reticle insulating film portion horizontally extending in a second direction of the surface of the semiconductor substrate, and a side surface of the vertical reticle insulating film portion, and a side surface of the vertical reticle insulating film portion The vertical first conductor portion extending in the first direction and the bottom side surface contacting the vertical first conductor portion simultaneously contact the bottom surface of the photomask insulating film and protruding from the horizontal first conductor portion in the second direction And forming the first conductor film and the vertical second conductor portion extending in the first direction and the bottom side surface contacting the vertical second conductor portion in contact with one side surface of the vertical first conductor portion a second conductor film formed by the horizontal second conductor portion protruding from the bottom surface of the horizontal first conductor portion and protruding in the second direction, And a vertical third conductor portion extending in the first direction and a bottom side surface contacting the vertical third conductor portion in contact with one side surface of the vertical second conductor portion, and the upper surface is in contact with the bottom surface of the second conductor film And a third conductor film formed by the horizontal third conductor portion protruding in the second direction, an edge portion side surface of the horizontal first conductor portion, and an edge portion side surface of the horizontal second conductor portion, and the horizontal third conductor a side surface of the edge portion is formed in a lower space of the bottom surface of the photomask insulating film, and a side surface of the flattening is formed in the first direction, and the side surface of the flattening is a memory of the side surface of the photomask insulating film. Unit range side. A semiconductor device characterized in that a lower end portion of a peripheral side surface of a memory pad formed on a semiconductor substrate has a photomask extending from a vertical mask insulating film portion perpendicular to a first direction of a surface of the semiconductor substrate The insulating film and the first conductor film formed by the first conductor portion extending in the first direction in contact with one side surface of the vertical mask insulating film portion and the one side surface of the vertical first conductor portion And extending the vertical second conductor portion in the first direction and the bottom side surface contacting the vertical second conductor portion, and contacting the bottom surface of the vertical first conductor portion to protrude from the horizontal second conductor in the second direction a second conductor film formed by the portion and a vertical third conductor portion extending in the first direction and a bottom side surface contacting the vertical third conductor portion in contact with one side surface of the vertical second conductor portion Then contacting the bottom surface of the second conductor film a third conductor film formed by the horizontal third conductor portion protruding in the second direction, a side surface of the vertical first conductor portion, and a side surface of the edge portion of the horizontal second conductor portion and the edge of the horizontal third conductor portion The side surface of the portion is formed in a lower space of the bottom surface of the photomask insulating film, and the side surface is formed in the first direction, and the side surface of the flattening is a side surface of the photomask insulating film that is notched to the side of the memory cell. . A semiconductor device characterized in that a lower end portion of a peripheral side surface of a memory pad formed on a semiconductor substrate has a photomask extending from a vertical mask insulating film portion perpendicular to a first direction of a surface of the semiconductor substrate The insulating film has a bottom surface that is in contact with the bottom surface of the vertical mask insulating film, and has a bottom surface that is flattened with the bottom surface of the vertical mask insulating film, and extends through the first conductor formed by the first vertical conductor portion in the first direction a film, and a second conductor film formed by the vertical second conductor portion extending in a side of the first vertical direction contacting the one side of the vertical first conductor portion, and extending to contact a side surface of the vertical second conductor portion The vertical third conductor portion in the first direction and the bottom side surface contacting the vertical third conductor portion simultaneously contact the bottom surface of the second conductor film and protrude from the horizontal third conductor portion in the second direction The third conductor film, the side surface of the vertical second conductor portion, and the side surface of the edge of the horizontal third conductor portion are in a space below the bottom surface of the photomask insulating film, in the first side To the side that forms the flattening, the side of the aforementioned flattening is for the front In the side surface of the reticle insulating film, the slit is on the side of the memory cell range. A method of manufacturing a semiconductor device, characterized in that a conductive layer including a protrusion having an upper surface and a side surface is formed over the semiconductor substrate, and a plate electrode layer is formed in sequence over the conductive layer, and the mask layer is sequentially formed And the photoresist layer is formed so that the portion of the upper surface and the side surface of the protruding portion facing the photoresist layer remains, the photoresist layer is patterned, and one of the mask layers is partially exposed and patterned. The photoresist layer is used as a mask to etch the mask layer, and the exposed portion of the mask layer is removed, and the edge portion of the mask layer formed through the film layer is retreated to remove the mask layer remaining after etching. As the photomask, the above-mentioned plate electrode layer is etched. The method of manufacturing a semiconductor device according to claim 12, wherein the retreat of the edge portion of the photomask layer is realized by etching the photoresist layer while etching the photomask layer. The method of manufacturing a semiconductor device according to claim 12, wherein the mask layer is formed of a tantalum oxide film, and the mask layer is etched using a gas containing CF ₄ and O ₂ . Conductor. The method of manufacturing a semiconductor device according to claim 14, wherein the end point detection by the plasma emission analysis is performed, and the etching of the tantalum oxide film is judged to be restarted once it reaches the end point. At the time, as the reference, the etcher of the mask layer is finished. The method of manufacturing a semiconductor device according to the invention of claim 12, wherein the etching of the plate electrode layer is performed by dry etching, and the dry etching is performed in an isotropic manner, and the bias is adjusted. Voltage. The method of manufacturing a semiconductor device according to claim 16, wherein the conductive layer is etched while etching the plate electrode layer. The method of manufacturing a semiconductor device according to claim 17, wherein the edge portion of the plate electrode layer is retracted from the edge portion of the photomask layer. The method of manufacturing a semiconductor device according to claim 12, wherein after the etching of the plate electrode layer, the protruding portion forms a buried interlayer insulating film simultaneously with the plate electrode and the photomask layer. A connection plug that penetrates the interlayer insulating film and reaches the semiconductor substrate is formed. The method of manufacturing a semiconductor device according to claim 12, wherein a lower electrode is formed on the semiconductor substrate, an insulating film is formed over the entire surface of the lower electrode, and then the conductive layer is formed. At the time of the film, a capacitor structure formed by the lower electrode and the insulating film and the conductive film is formed, and the protruding portion is formed in a range in which the lower electrode is formed.