JPH1084090A - Semiconductor memory and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory which is formed on a SOI substrate and has a capacitor having a large capacitance in a buried oxide film layer under a source region. SOLUTION: A buried oxide film layer 2 is formed on a semiconductor substrate 1. A MOS transistor 4 is formed on a silicon layer 3 on the buried oxide film layer 2. A trench-type capacitor 10 is formed in the buried oxide film layer 2 and right under a source region 6 of the transistor 4. The capacitor 10 comprises a conductive capacitor electrode 11a which is buried along the inner sides so that it may be directly connected to the lower part of the source region 6, a dielectric film 12 deposited inside the capacitor electrode 11a and a capacitor electrode 11b buried through the capacitor dielectric film 12. With this structure, the area of the capacitor electrode is larger than that of a conventional device and the capacitance of the capacitor is accordingly larger.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device using an SOI structure and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, a dynamic random access memory (DRAM) has been developed.
ory) has made remarkable progress. The DRAM cell structure is
In order to secure the maximum amount of stored charge in the smallest possible area, the structure has changed significantly from a planar structure up to 1M bit to a 3D structure after 4M. In addition, from 4M to 16M, from 16M
As it progressed to 64M, it became a more complex three-dimensional structure. This is because the reduction ratio of the design rule has decreased, and the process margin and the processing accuracy have become less proportional to the reduction in the design rule.

The main three-dimensional structures include a stack type and a trench type. Other than these, there is a semiconductor memory device using an SOI structure, which is one of the conventional examples.

Hereinafter, an example of the above-described semiconductor memory device will be described with reference to the drawings. This technology is disclosed in
No. 42607.

FIG. 6 is a schematic sectional view of a semiconductor memory device using the SOI structure. In FIG. 6, the semiconductor substrate 31
The dielectric layers 32a and 32b are formed on the main surface of. A silicon layer 33 is formed on the dielectric layers 32a and 32b.
MOS transistors 34a and 34b are formed in the silicon layer 33. Further, impurity regions 35a and 35b are formed in the silicon layer 33.
have. The impurity region 35a, the dielectric layer 32b, and the semiconductor substrate 31 form a capacitor.

FIG. 7 is a schematic sectional view showing a manufacturing process of a semiconductor memory device using an SOI structure.

[0007] As shown in FIG.
Sputtering or CVD (Chemi
The dielectric layer 32a is formed by using a cal vapor deposition method or the like. Then, an opening 41 for selectively exposing the main surface of the semiconductor substrate 31 is formed by patterning the dielectric layer 32a into a predetermined shape.

Next, as shown in FIG.
A dielectric layer 32b is deposited on the entire surface of the main surface by sputtering or CVD.

Next, as shown in FIG. 7C, the dielectric layer 32b is subjected to a CMP (Chemical Mechanical Polishing) process. Thus, the dielectric layer 32b is left only in the opening 41.

[0010] Next, as shown in FIG.
A silicon layer 33 into which, for example, a p-type impurity is introduced is formed on a and 32b by using a CVD method or the like. Further, a gate insulating film 37 is formed on the surface of the silicon layer 33 by a thermal oxidation method. A polycrystalline silicon layer 38 is formed on the gate insulating film 37 by using a CVD method. An insulating layer 39 is formed on the polycrystalline silicon layer 38 by using a CVD method.

Next, as shown in FIG.
9. The gate electrode portion 40 is formed by sequentially etching the polycrystalline silicon layer 38 and the gate insulating film 37. Next, an n-type impurity is implanted into the silicon layer 33 using the gate electrode portion 40 as a mask. As described above, the semiconductor memory device is formed.

[0012]

However, in the above-mentioned structure, since the width immediately below the source region is small and the electrode area of the capacitor is small, sufficient capacitance of the capacitor cannot be secured. In addition, in the above-described manufacturing method, since a method of alignment is not reliable, a capacitor is not always formed by the impurity region, the dielectric layer, and the semiconductor substrate.

In addition, further miniaturization is expected in the future, but in that case, even if the element width is small, it is necessary to increase the area of the capacitor electrode, to secure the capacitor capacity required for operation, and to use the alignment key. In addition, the importance of forming a capacitor immediately below the source region is increasing, and its process accuracy is required.

An object of the present invention is to provide a semiconductor memory device having a larger capacity than a conventional one when a capacitor is formed in a buried oxide film layer immediately below a source region in a transistor formed on an SOI substrate. An object of the present invention is to provide a manufacturing method that can be surely formed immediately below a source region.

[0015]

According to the present invention, the problem of the semiconductor memory device can be solved by forming a trench capacitor immediately below a source region of a transistor. Further, the problem of the above-described manufacturing method can be solved by employing a semiconductor memory device having an alignment key and a manufacturing method using the key as a mark.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) Hereinafter, a first embodiment of the present invention will be described with reference to FIG.

FIG. 1 is a sectional view of a semiconductor memory device according to a first embodiment of the present invention.

First, FIG. 1 shows a semiconductor substrate 1 having conductivity.
There is a buried oxide film layer 2 above, and a MOS transistor 4 is formed on the upper silicon layer 3 thereabove. The MOS transistor 4 has a source region 6 and a drain region 7 which are impurity regions formed in the silicon layer 3 so as to define the channel region 5, and a gate oxide film 8 is interposed on the channel region 5. A gate electrode 9 formed by Further, a trench type capacitor 10 is provided immediately below the source region 6 in the buried oxide film layer 2. Trench type capacitor 10
Is a conductive one capacitor electrode 11a buried along the inner peripheral surface so as to be directly connected to the lower part of the source region 6.
And a capacitor dielectric film 12 deposited on the inner peripheral surface of the capacitor electrode 11a, and another capacitor electrode 11b embedded through the capacitor dielectric film 12. The configuration of the semiconductor memory device is as described above.

The present embodiment is characterized in that a trench type capacitor 10 is provided immediately below the source region 6. According to such a configuration, the effect that the surface area of the capacitor electrode is increased and the capacitance of the capacitor is increased as compared with the related art can be obtained.

(Embodiment 2) A second embodiment of the present invention will be described below with reference to FIG. FIG. 2 is a sectional view of a semiconductor memory device according to a second embodiment of the present invention.

The structure of the semiconductor memory device of the present embodiment is different from that of the first embodiment in that the element non-forming portion 14 is provided with an element isolation groove 15 in which an insulator also serving as a mark and a positioning mark is embedded. It is a point which has. This element separation groove 15
Is an opening formed from the upper silicon layer to the buried oxide film layer, and an insulator is buried in the trench 15 for element isolation. Other configurations are the same as those of the first embodiment.
In this configuration, in particular, the groove 15 for element isolation in the element non-forming portion 14 is formed.
And a trench type capacitor 10 is provided immediately below the source region 6. With such a configuration, when the capacitor is formed by the manufacturing method of the fourth embodiment, the trench 15 for element isolation also serves as an alignment key for forming the trench capacitor 10 immediately below the source region 6. Capacitors can be reliably formed immediately below the source region 6 as compared with the conventional example. In addition, since the capacitor is a trench capacitor, the effect of increasing the surface area of the capacitor electrode and increasing the capacitance of the capacitor can be obtained.

(Embodiment 3) Hereinafter, a third embodiment of the present invention will be described with reference to FIG. FIG. 3 is a sectional view of a semiconductor memory device according to a third embodiment of the present invention.

The difference from the second embodiment is that the element non-forming portion 1
4 has a conductive mark and a positioning mark 16 formed on the oxide film 17 for element isolation. The mark and the alignment mark 16 are tungsten plugs buried in openings formed from the upper part of the element isolation oxide film 17 to the buried oxide film layer. Other configurations are the same as those of the second embodiment.

Particularly, the oxide film 17 for element isolation in the element non-forming portion 14
A feature is that a trench type capacitor 10 is provided immediately below the conductive mark, the alignment mark 16 and the source region 6 formed on the substrate. With such a configuration, when the capacitor is formed by the manufacturing method of the fifth embodiment, the mark and the alignment mark 16 serve as an alignment key for forming the trench capacitor 10 immediately below the source region 6, and the conventional example. In comparison, a capacitor can be formed directly under the source region 6. In addition, since the capacitor is a trench capacitor, the effect of increasing the surface area of the capacitor electrode and increasing the capacitance of the capacitor can be obtained.

(Embodiment 4) Hereinafter, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 4 is a process sectional view of a semiconductor memory device according to a fourth embodiment of the present invention.

First, as shown in FIG. 4A, the lower semiconductor substrate 1 is moved from the upper silicon layer 3 to the element non-formed portion 14 of the SOI substrate.
To form a trench 15 for element isolation, and further bury SiO2, which is an insulator, in the trench 15 by a CVD method.

Thereafter, as shown in FIG.
A MOS transistor 4 is formed on 13.

Next, as shown in FIG.
After the necessary wiring step 18 and the protection film 19 are deposited thereon, the entire surface of the protection film 19 is flattened by a CMP method or the like.

Next, as shown in FIG. 4D, a polishing support metal plate 20 is attached on the protective film 19 to increase the strength during polishing.

Further, as shown in FIG.
Until it reaches oxide layer 2 (from bottom to top in the figure)
Polish by MP method. If the strength during polishing is sufficient, the flattening step of the protective film 19 and the polishing support metal plate 20
Is unnecessary. By this polishing, the insulator buried in the trench 15 for element isolation is exposed, and the insulator is aligned with the mark in a later step. This step is not limited to polishing, but may be etching with an alkaline solution such as an aqueous solution of ethylenediamine or pyrocatechol or an aqueous solution of hydrazine or isopropyl alcohol. The reason for using these alkaline solutions is that silicon is etched due to a difference in selectivity, but an oxide film is difficult to etch.

Next, as shown in FIG. 4 (f), the wafer is aligned using the groove 15 for element isolation as a mark, and the buried oxide film layer 2 immediately below the source region 6 is etched by the mark. A groove 21 for charge storage is formed. This charge storage groove
21 reaches the source region 6.

Next, as shown in FIG. 4 (g), platinum is deposited on the inner surface of the groove 21 as one capacitor electrode 11a in the charge storage groove 21 by a sputtering method. This capacitor electrode 11a is electrically directly connected to the source region 6. After that, BST ((Ba, Sr) TiO3) which is a high dielectric substance is applied to the inner peripheral surface of the capacitor electrode 11a by MOCVD (Metal Organic
The capacitor dielectric film 12 is formed by deposition using a Chemical Vapor Deposition method. Dielectric film is P except for BST
ZT (Pb (Zr, Ti) O3), PLZT ((Pb, La) (Zr, Ti) O3), Ta2O
5, TiO2 and the like. Platinum is embedded as the other capacitor electrode 11b via the capacitor dielectric film 12.

Then, as shown in FIG.
Perform 23. As described above, the element non-forming portion 14 is formed with an element isolation groove 15 in which an insulator that also serves as an element separation and mark and alignment is formed, and this is used as a mark to form a trench immediately below the source region 6. The mold capacitor 10 can be reliably formed.

(Embodiment 5) A fifth embodiment of the present invention will be described below with reference to FIG. FIG. 5 is a process sectional view of a semiconductor memory device according to a fifth embodiment of the present invention.

First, as shown in FIG. 5A, an oxide film 17 for element isolation is formed on the upper silicon layer 3 of the element non-formed portion 14 of the SOI substrate.
Is formed, the central portion of the oxide film 17 for element isolation, which is an SiO2 film, is marked to form a groove 22 for positioning, and is etched until it reaches the lower semiconductor substrate 1. Further, a metal such as tungsten is buried in the alignment groove 22 by a CVD method, and a mark and an alignment mark 16 are formed. The mark 16 serves as a mark for aligning the wafer after removing the semiconductor substrate 1 from the back surface, and also as a mark for opening a groove 21 for charge accumulation in the buried oxide film layer below the source region 6. I have.

After this step, as shown in FIG. 5B, the MOS transistor 4 is formed in the element forming section 13. Note that the mark and the alignment mark 16 may be an insulator other than metal or a gap.

Next, as shown in FIG.
After the necessary wiring step 18 and the protection film 19 are deposited thereon, the entire surface of the protection film 19 is flattened by a CMP method or the like.

Next, as shown in FIG. 5D, a polishing support metal plate 20 is attached on the protective film 19 to increase the strength during polishing.

Further, as shown in FIG.
Until it reaches oxide layer 2 (from bottom to top in the figure)
Polish by MP method. If the strength during polishing is sufficient, the flattening step of the protective film 19 and the polishing support metal plate 20
Is unnecessary. Also, this step is not limited to polishing, ethylenediamine, aqueous solution of pyrocatechol and hydrazine,
Etching with an alkaline solution such as an aqueous solution of isopropyl alcohol may be used. The reason for using these alkaline solutions is that silicon is etched due to a difference in selectivity, but an oxide film is difficult to etch.

Next, as shown in FIG. 5 (f), the wafer is aligned using the mark and the alignment mark 16 as a mark, and then the mark is applied to the buried oxide film layer 2 below the source region 6 with the mark. A groove 21 for charge storage is formed. The groove 21 for charge storage reaches the source region 6. Next, as shown in FIG. 5 (g), platinum is deposited on the inner peripheral surface of the charge storage groove 21 as one capacitor electrode 11a by a sputtering method. This capacitor electrode 11a is electrically directly connected to the source region 6. Thereafter, the above-mentioned capacitor electrode 11a
BST, which is a high dielectric substance, is deposited on the inner peripheral surface of the
A capacitor dielectric film 12 is formed. Further, platinum is buried as the other capacitor electrode 11b via the capacitor dielectric film 12.

Then, as shown in FIG.
Perform 23. As described above, by forming the mark and the alignment mark 16 in the element non-forming portion 14 and using the mark as a mark, the trench capacitor 10 can be surely formed immediately below the source region 6.

[0042]

As described above, the present invention provides a silicon substrate,
It has a three-layer structure consisting of a buried oxide layer and an upper silicon layer.
By forming a trench capacitor in the buried oxide film layer directly below the source region of the SOI field effect transistor formed on the SOI substrate, the area of the capacitor electrode becomes larger than in the conventional example, and a larger capacitor capacity is obtained. Can be secured. In addition, a mark and a positioning mark are formed in the element non-formed portion, and alignment is performed using the mark as a mark, whereby the trench capacitor can be reliably formed immediately below the source region.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of an SOI type DRAM structure according to a first embodiment of the present invention.

FIG. 2 is a schematic sectional view of an SOI type DRAM structure according to a second embodiment of the present invention;

FIG. 3 is a schematic sectional view of the structure of an SOI DRAM according to a third embodiment of the present invention;

FIG. 4 is a schematic sectional view of a method for manufacturing an SOI DRAM according to a fourth embodiment of the present invention;

FIG. 5 is a schematic cross-sectional view of a method for manufacturing an SOI DRAM according to a fifth embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view of a conventional SOI DRAM structure

FIG. 7 is a schematic cross-sectional view of a conventional SOI DRAM manufacturing method.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 buried oxide film layer 3 upper silicon layer 4 MOS transistor (5, 6, 7, 8, 9) 5 channel region 6 source region 7 drain region 8 gate oxide film 9 gate electrode 10 capacitor (11a, 11b, 12) 11a, b capacitor electrode 12 capacitor dielectric layer 13 element forming part 14 element non-forming part 15 element separating groove 16 mark, alignment mark 17 element separating oxide film 18 wiring 19 protective film 20 polishing support substrate 21 Grooves for charge storage 22 Marks, grooves for alignment 23 Aluminum wiring 31 Semiconductor substrate 32a, b Dielectric layer 33 Silicon layer 34 MOS transistor 35a, b Impurity region 36 Capacitor 37 Gate insulating film 38 Polycrystalline silicon layer 39 Insulating film 40 gate electrode 41 opening

Claims (5)

[Claims] 1. A semiconductor memory device having an SOI structure, comprising: a field effect transistor formed on an upper silicon layer of the SOI substrate; and a buried oxide film layer below an upper silicon layer on which the field effect transistor is formed. At least one or more charge storage grooves formed therein, one electrode formed on the inner peripheral surface of the groove, a dielectric film formed on the inner peripheral surface of the electrode, A second electrode formed on an inner peripheral surface of the body film, wherein one of the electrodes in the groove is electrically connected to a source region of the field effect transistor. 2. An element isolation groove formed so as to leave an island-shaped element region from a surface of an upper silicon layer of the SOI substrate to a lower end of a buried oxide film layer below the upper silicon layer. 2. The semiconductor memory device according to claim 1, further comprising an insulator inside the element isolation groove. 3. An insulating film for element isolation formed so as to leave an island-shaped element region from a surface of an upper silicon layer of the SOI substrate to a lower end of a buried oxide film layer below the upper silicon layer. Formed at least from the upper portion of the insulating film to the lower end of the buried oxide film layer below the insulating film;
2. The semiconductor memory device according to claim 1, comprising one or more marks and alignment marks. 4. A method of manufacturing a semiconductor memory device having an SOI structure, comprising: forming an island-shaped element region from a surface of an upper silicon layer of the SOI substrate to a lower end of a buried oxide film layer below the upper silicon layer. Forming a groove for element isolation to be left, a step of embedding an insulator in the groove for element isolation, a step of forming a field effect transistor in the element region, a wiring pattern on the field effect transistor, Forming a protective film sequentially, removing the semiconductor substrate from the back surface, exposing the element isolation trench,
Forming a groove for charge storage in the buried oxide film layer below the source region of the field effect transistor using the groove for element isolation as a mark and an alignment key; and an inner peripheral surface of the groove for charge storage. Forming a first electrode, forming a dielectric film on the inner surface of the electrode, and forming another electrode on the inner surface of the dielectric film. Production method. 5. A method for manufacturing a semiconductor memory device having an SOI structure, comprising: forming an insulating film for element isolation such that an island-shaped element region is left on a surface of an upper silicon layer of the SOI substrate; Forming at least one or more openings from the upper portion of the insulating film to the lower end of the buried oxide film layer below the insulating film; forming a mark in the openings; forming a positioning mark; and Forming a field effect transistor, a step of sequentially forming a wiring pattern and a protective film on the field effect transistor, removing the semiconductor substrate from the back surface, exposing the mark,
Forming a groove for charge storage in the buried oxide film layer below the source region of the field-effect transistor using the mark as a mark and an alignment key; and forming one electrode on an inner peripheral surface of the groove for charge storage. Forming a dielectric film on the inner peripheral surface of the electrode; and forming another electrode on the inner peripheral surface of the dielectric film.