TW201511222A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TW201511222A
TW201511222A TW103107051A TW103107051A TW201511222A TW 201511222 A TW201511222 A TW 201511222A TW 103107051 A TW103107051 A TW 103107051A TW 103107051 A TW103107051 A TW 103107051A TW 201511222 A TW201511222 A TW 201511222A
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semiconductor layer
semiconductor
substrate
switching element
region
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TW103107051A
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TWI533435B (zh
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Keita Takahashi
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Toshiba Kk
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Abstract

若根據實施形態，則半導體裝置是具備設於同基板上的開關元件及二極體。開關元件是具有：第1半導體層，第1半導體領域，第2半導體領域，通道領域，閘極絕緣膜，閘極電極，第1電極及第2電極。第1半導體層是設在基板內，與基板電性分離。二極體是具有：第2半導體層，陽極領域，陰極領域，陽極電極及陰極電極。第2半導體層是設在基板內，與基板電性分離。

Description

半導體裝置
本申請案是享受2013年9月13日申請之日本專利申請案號2013-191112的優先權的利益，該日本專利申請案的全內容是被援用於本案。
本發明的實施形態是有關半導體裝置。
例如在線圈等的感應性負荷所連接的開關元件中，當閘極為關閉時，藉由被積蓄於感應性負荷的能量，在開關元件的本體二極體(寄生二極體)流動電流。這使開關元件，形成有開關元件的基板，及在形成於同基板的其他的元件之間寄生的半導體閘流管(Thyristor)動作，成為引起其他的元件的破壞之原因。
本發明所欲解決的課題是在於提供一種可抑制開關元件的寄生元件的動作之半導體裝置。
一實施形態的半導體裝置，其特徵係具備設 在同基板上的開關元件及二極體，前述開關元件係具有：第1半導體層，其係設於前述基板內，與前述基板電性分離；第1半導體領域，其係設於前述第1半導體層的表面；第2半導體領域，其係於前述第1半導體層的表面對於前述第1半導體領域分離設置，與前述第1半導體領域同導電型；通道領域，其係設在前述第1半導體層的表面的前述第1半導體領域與前述第2半導體領域之間，與前述第1半導體領域及前述第2半導體領域的導電型相反導電型；閘極絕緣膜，其係設在前述通道領域上；閘極電極，其係設在前述閘極絕緣膜上；第1電極，其係被連接至前述第1半導體領域；及第2電極，其係被連接至前述第2半導體領域，前述二極體係具有：第2半導體層，其係設於前述基板內，與前述基板電性分離；陽極領域，其係設於前述第2半導體層的表面；陰極領域，其係於前述第2半導體層的表面對於前述陽極領域分離設置；陽極電極，其係被連接至前述陽極領域；及陰極電極，其係被連接至前述陰極領域。
若根據上述構成的半導體裝置，則可抑制開關元件的寄生元件的動作。
4‧‧‧低側開關元件
5‧‧‧高側開關元件
6‧‧‧二極體
7‧‧‧邏輯元件
10‧‧‧基板
11‧‧‧N型半導體層
12‧‧‧N型半導體層
13‧‧‧N型半導體層
21‧‧‧P+型汲極領域
22‧‧‧P+型源極領域
23‧‧‧P型半導體領域
24‧‧‧N型半導體領域
26‧‧‧P-型半導體領域
27‧‧‧通道領域
28‧‧‧閘極電極
29‧‧‧閘極絕緣膜
30‧‧‧絕緣膜
31‧‧‧汲極電極
32‧‧‧源極電極
33‧‧‧N+型半導體領域
41‧‧‧P+型陽極領域
42‧‧‧N+型陰極領域
43‧‧‧P型半導體領域
44‧‧‧N型半導體領域
51‧‧‧陽極電極
52‧‧‧陰極電極
61‧‧‧N+型半導體領域
62‧‧‧N+型半導體領域
63‧‧‧P+型半導體領域
64‧‧‧N+型半導體領域
65‧‧‧P型半導體領域
91‧‧‧寄生PNP電晶體
92‧‧‧寄生PNP電晶體
93‧‧‧寄生電阻
94‧‧‧基極電阻
100‧‧‧NPN電晶體
111‧‧‧電源線
112‧‧‧輸出線
120‧‧‧N+型埋入層
圖1是實施形態的半導體裝置的模式剖面圖。
圖2是實施形態的半導體裝置的電路圖。
圖3是表示實施形態的半導體裝置的雜質濃度的一例圖。
圖4是實施形態的半導體裝置的電路圖。
圖5是其他的實施形態的半導體裝置的模式剖面圖。
圖6是其他的實施形態的半導體裝置的模式剖面圖。
圖7是其他的實施形態的半導體裝置的電路圖。
圖8是其他的實施形態的半導體裝置的模式剖面圖。
圖9(a)~(c)是其他的實施形態的半導體裝置的模式平面圖。
若根據實施形態，則半導體裝置是具備設於同基板上的開關元件及二極體。前述開關元件是具有：第1半導體層，第1半導體領域，第2半導體領域，通道領域，閘極絕緣膜，閘極電極，第1電極及第2電極。前述第1半導體層是設在前述基板內，與前述基板電性分離。前述第1半導體領域是設在前述第1半導體層的表面。前 述第2半導體領域是在前述第1半導體層的表面對於前述第1半導體領域分離設置，與前述第1半導體領域同導電型。前述通道領域是設在前述第1半導體層的表面之前述第1半導體領域與前述第2半導體領域之間，與前述第1半導體領域及前述第2半導體領域的導電型是相反導電型。前述閘極絕緣膜是設在前述通道領域上。前述閘極電極是設在前述閘極絕緣膜上。前述第1電極是被連接至前述第1半導體領域。前述第2電極是被連接至前述第2半導體領域。前述二極體是具有：第2半導體層，陽極領域，陰極領域，陽極電極及陰極電極。前述第2半導體層是設在前述基板內，與前述基板電性分離。前述陽極領域是設在前述第2半導體層的表面。前述陰極領域是在前述第2半導體層的表面對於前述陽極領域分離設置。前述陽極電極是被連接至前述陽極領域。前述陰極電極是被連接至前述陰極領域。
以下，參照圖面說明有關實施形態。另外， 各圖面中，對於同要素附上同符號。在以下的實施形態是將第1導電型設為p型，將第2導電型設為n型來說明，但即使將第1導電型設為n型，將第2導電型設為p型也可實施。
圖1是實施形態的半導體裝置的模式剖面圖。
實施形態的半導體裝置是具有：開關元件5，二極體6及邏輯元件7被混載於同基板10上的構造。
基板10是P型半導體基板，例如P型矽基 板。並且，以下說明的半導體層(領域)是矽層(領域)。或，基板10及半導體層(領域)並非限於矽，例如亦可為碳化矽，氮化鎵等。
在半導體層的表面所欲分離的要素間是例如設有STI(Shallow Trench Isolation)構造的絕緣膜30。
在晶片狀的半導體裝置的中心側領域是形成有包含邏輯元件7之例如類比積體電路。開關元件5及二極體6是例如形成於晶片周邊領域。開關元件5是例如形成於邏輯元件7與二極體6之間的領域。
邏輯元件7與開關元件5是藉由形成於該等之間的絕緣膜30來絕緣分離。開關元件5與二極體6是藉由形成於該等之間的絕緣膜30來絕緣分離。
開關元件5是例如P通道型的DMOS(double diffused metal oxide semiconductor field effect transistor)。在DMOS中，通道是以雙重擴散形成，利用擴散領域的橫方向擴散的差作為實效通道長。
開關元件5是具有作為形成於基板10內的第1半導體層之N型半導體層11。N型半導體層11與P型的基板10是pn接合，N型半導體層11是對於基板10電性分離。基板10是被接地，N型半導體層11是經由N型半導體領域24及N+型半導體領域33來連接至開關元件5的源極電位。
在N型半導體層11的表面是形成有一對的P- 型半導體領域26，在該等P-型半導體領域26之間是形成有P型半導體領域23。P型半導體領域23的P型雜質濃度是比P-型半導體領域26的P型雜質濃度更高。
在P型半導體領域23的表面是形成有P+型汲 極領域21作為第1半導體領域。P+型汲極領域21的P型雜質濃度是比P型半導體領域23的P型雜質濃度更高。
P+形汲極領域21的兩側面是接觸於P-型半導 體領域26的表面所形成的絕緣膜30。
在N型半導體層11的表面，分別對於一對的 P-型半導體領域26分離而形成有一對的N型半導體領域24。
在各N型半導體領域24的表面是形成有P+ 型源極領域22作為第2半導體領域。
並且，在各N型半導體領域24的表面，與 P+型源極領域22鄰接而形成有N+型半導體領域33。N+型半導體領域33的N型雜質濃度是比N型半導體領域24的N型雜質濃度更高。
N+型半導體領域33的一方的側面是接觸於P+ 型源極領域22，另一方的側面是接觸於絕緣膜30。
P+型源極領域22之P+型汲極領域21側的側面 是位於N型半導體領域24內。在該N型半導體領域24與P-型半導體領域26之間是形成有N型半導體層11。
在P+型源極領域22與P-型半導體領域26之 間所形成的N型半導體領域24的表面領域及N型半導體 層11的表面領域是作為通道領域27的機能。
在通道領域27上，及與此通道領域27鄰接 的P-型半導體領域26的表面上是設有閘極絕緣膜29。在閘極絕緣膜29上是設有閘極電極28。
在P+型汲極領域21上是設有汲極電極31作 為第1電極。P+型汲極領域21是直接或經由金屬矽化物層等的所望的方法來歐姆接觸於汲極電極31，電性連接。
在P+型源極領域22上是設有源極電極32作 為第2電極。P+型源極領域22是直接或經由金屬矽化物層等的所望的方法來歐姆接觸於源極電極32，電性連接。
並且，源極電極32是在N+型半導體領域33 上也被設置，接觸於N+型半導體領域33。
開關元件5的各半導體領域及閘極電極28是 例如以條紋狀的平面圖案所形成。
在以上說明的開關元件5中，一旦所望的閘 極電壓被施加於閘極電極28，則會在通道領域27形成反轉層(P通道)，電流會經由P+型源極領域22，通道領域27，P-型半導體領域26，P型半導體領域23及P+型汲極領域21來流動於源極電極32與汲極電極31間。在P-型半導體領域26及P型半導體領域23中，使可繞入絕緣膜30之下的領域來通過電流。
形成於汲極側的絕緣膜30是提高開關元件5 的耐壓。並且，P型雜質濃度比P+形汲極領域21更低的P-型半導體領域26是在閘極關閉時空乏化，使耐壓提升。
並且，藉由在P-型半導體領域26與P+型汲極 領域21之間設置P-型半導體領域26的P型雜質濃度與P+型汲極領域21的P型雜質濃度之中間的P型雜質濃度的P型半導體領域23，可從P-型半導體領域26到P+型汲極領域21來抑制雜質濃度突然變化所造成的耐壓降低。
其次，說明有關二極體6。
二極體6是具有作為形成於基板10內的第2 半導體層之N型半導體層12。N型半導體層12與P型的基板10是pn接合，N型半導體層12是對於基板10電性分離。基板10是被接地，N型半導體層12是經由N型半導體領域44及N+型陰極領域42來連接至二極體6的陰極電極52。
在N型半導體層12的表面是形成有複數的P 型半導體領域43，及複數的N型半導體領域44。P型半導體領域43及N型半導體領域44是例如以條紋狀的平面圖案來交替地配列。P型半導體領域43與N型半導體領域44是分離。
在各P型半導體領域43的表面是形成有P+型 陽極領域41。P+型陽極領域41的P型雜質濃度是比P型半導體領域43的P型雜質濃度更高。
在各N型半導體領域44的表面是形成有N+ 型陰極領域42。N+型陰極領域42的N型雜質濃度是比N型半導體領域44的N型雜質濃度更高。
在P+型陽極領域41與N+型陰極領域42之間 是設有絕緣膜30，P+型陽極領域41與N+型陰極領域42是藉由絕緣膜30來分離。
在P+型陽極領域41上是設有陽極電極51。 P+型陽極領域41是直接或經由金屬矽化物層等的所望的方法來歐姆接觸於陽極電極51，電性連接。
在N+型陰極領域42上是設有陰極電極52。N+型陰極領域42是直接或經由金屬矽化物層等的所望的方法來歐姆接觸於陰極電極52，電性連接。
邏輯元件7是具有與DMOS構造的開關元件5或二極體6相異的構造，例如具有CMOS構造。在圖1中顯示邏輯元件7的一部分(例如N通道型MOSFET)。
邏輯元件7是具有例如形成於基板10內的N型半導體層13。N型半導體層13與P型的基板10是pn接合，N型半導體層13是對於基板10電性分離。
在N型半導體層13的表面是形成有P型半導體領域65。在P型半導體領域65的表面是形成有N+型半導體領域61及N+型半導體領域62。N+型半導體領域61及N+型半導體領域62的一方是汲極領域，另一方是作為源極領域的機能。
在N+型半導體領域61與N+型半導體領域62之間的通道領域(P型半導體領域65的表面領域)上是 經由閘極絕緣膜29來設有閘極電極28。
並且，在N型半導體層13的表面，與P型半 導體領域65鄰接而形成有N型半導體領域66。在N型半導體領域66的表面是形成有N+型半導體領域64。
N+型半導體領域64的N型雜質濃度是比N型 半導體領域66的N型雜質濃度更高。
並且，在P型半導體領域65的表面是形成有 P+型半導體領域63。在P+型半導體領域63與N+型半導體領域62之間是形成有絕緣膜30。在P+型半導體領域63與N+型半導體領域64之間是形成有絕緣膜30。
開關元件5，二極體6及邏輯元件7是分別形 成於對基板10電性分離的N型半導體層11，N型半導體層12及N型半導體層13的表面。亦即，開關元件5，二極體6及邏輯元件7是不經由基板10來電性連接。
基板10是被接地，相對的，N型半導體層11 及N型半導體層12的電位是位於高電位。因此，電流不易從開關元件5，二極體6及邏輯元件7流至基板10。
開關元件5是例如使用在輸出大電流的H電 橋電路，反相器(inverter)電路，DC-DC變換器(converter)電路等。
圖2是具備實施形態的半導體裝置的電路的 電路圖。
在電源線(輸入線)111與接地端子之間串聯 有前述的開關元件(高側(High-Side)開關元件)5及低 側(Low-Side)開關元件4，該電源線(輸入線)111是與電源連接，被供給電源電壓(輸入電壓)Vcc。
開關元件5的源極端子(源極電極32)是被 連接至電源線111，汲極端子(汲極電極31)是被連接至輸出線112。
低側開關元件4是例如N通道型MOSFET。 低側開關元件4的汲極端子是被連接至開關元件5的汲極端子及輸出線112。低側開關元件4的源極端子是被連接至接地端子。
並且，在電源線111與輸出線112之間是連 接有前述的二極體6。二極體6的陽極端子(陽極電極51)會被連接至輸出線112，陰極端子(陰極電極52)會被連接至電源線111。
在輸出線112是連接有線圈L作為感應性負 荷。因此，開關元件5及二極體6是被並聯於電源與線圈L之間。亦即，開關元件5及二極體6是具有：被連接至電源的端子，及被連接至線圈L的端子。
高側開關元件5，低側開關元件4，及驅動該等的驅動電路或控制電路是被集聚於1晶片。
例如在DC-DC變換器(buck converter)中，藉由將高側開關元件5及低側開關元件4交替地開啟關閉，比輸入電壓Vcc更低的平均輸出電壓會被輸出。
當低側開關元件4開啟，高側開關元件5關閉時，電流會從輸出端子經由線圈L來輸出至低側開關元 件4及接地端子。此時，電流會流至線圈L，能量會被蓄積。
其次，若高側開關元件5及低側開關元件4 同時開啟，則貫通電流會從電源線111經由開關元件5、4來流至接地端子。為了予以避免，而在設定開關元件5、4的開啟關閉的任務時，設定開關元件5，4皆成為關閉的期間之空載時間。
在空載時間期間，開關元件5的閘極是關 閉，但線圈L是藉由所被蓄積的能量來繼續流動電流，因此回生電流會流至開關元件5的本體二極體(圖1的P型半導體領域23與N型半導體領域11的pn接合)。此時，有時寄生PNP電晶體91會動作。
可藉由自N型半導體層11與P型基板10的 pn接合擴展的空乏層來謀求開關元件5的高耐壓化。因此，N型半導體層11的N型雜質濃度及P型基板10的P型雜質濃度是被壓低。
由於N型半導體層11的N型雜質濃度低，因 此寄生PNP電晶體91的基極的再結合電流會減少，基極電阻94會變高，電流容易流至基板10。
而且，基板10的寄生電阻93也高，因此基 板10的電位會容易上昇，開關元件5，基板10及寄生在其他的元件7的NPN電晶體100(圖1)的基極電位會上昇，寄生NPN電晶體100會動作。
一旦寄生NPN電晶體100動作，則寄生PNP 電晶體91的基極電流會持續被供給，因此寄生PNP電晶體91不會回到關閉，寄生PNP電晶體91持續動作，因此寄生NPN電晶體100也不會回到關閉。亦即，藉由寄生半導體閘流管的動作，引起閂鎖(Latch up)，大電流會流入邏輯元件7，擔心使邏輯元件7破壞。
然而，若根據實施形態，則在電源與線圈L之間，對於開關元件5並列地連接有二極體6。
因此，在空載時間期間，從線圈L流動的電流I1是被分散成：流至開關元件5的汲極側的電流I"1，及流至二極體6的陽極側的電流I'1，可降低經由開關元件5的寄生PNP電晶體91來流至基板10的電流I"3。
另外，在二極體6也與開關元件5同樣產生寄生PNP電晶體92，但藉由降低寄生PNP電晶體92的基極電阻95，可抑制流至基板10的電流I'3。
亦即，二極體6的寄生電阻是比開關元件5的寄生電阻更低。因此，從線圈L流動的電流I1是作為電流I'1及I'2，容易從二極體6的陽極流至陰極，可抑制流至基板10的電流I'3。
流至基板10的電流I"3及I'3會被抑制，藉此高電阻的基板10的電位上昇會被抑制，可防止寄生半導體閘流管動作所產生的閂鎖所造成的元件破壞。
在實施形態中，為了使二極體6的寄生電阻形成比開關元件5的寄生電阻更低，例如將N型半導體層12的N型雜質濃度形成比N型半導體層11的N型雜質 濃度更高。
圖3是表示二極體6的N型半導體層12的N 型雜質濃度(實線)，及開關元件5的N型半導體層11的N型雜質濃度(虛線)的一例。橫軸的深度(μm)是表示離N型半導體層12及N型半導體層11的各表面的深度。
例如，若將二極體6的N型半導體層12的峰 值濃度設為約5×1016(cm-3)，將開關元件5的N型半導體層11的峰值濃度設為約1.3×1016(cm-3)，則要比寄生電阻大的開關元件5的本體二極體的N型半導體層11更可擴大流至寄生電阻小的二極體6的N型半導體層12之回生電流。
N型半導體層12及N型半導體層11的N型 雜質濃度的範圍也會依據所被求取的耐壓，設定在1×1016(cm-3)~1×1018(cm-3)。
並且，在圖1所示的實施形態中，開關元件5 的N型半導體層11與二極體6的N型半導體層12是在P型基板10內分離形成。亦即，在N型半導體層11與N型半導體層12之間形成有與該等相反導電型的P型半導體領域。
因此，N型半導體層11與N型半導體層12 之間的載子移動會被抑制，可使開關元件5及二極體6分別難以誤動作。
又，為了使二極體6的寄生電阻形成比開關 元件5的寄生電阻更低，例如將二極體6的陽極領域41與陰極領域42之間的距離形成比開關元件5的汲極領域21與源極領域22之間的距離形成更短。在此的距離是顯示以最短距離來連結兩領域間的直線距離。
又，為了使二極體6的寄生電阻形成比開關 元件5的寄生電阻更低，例如亦可將二極體6的配線電阻形成比開關元件5的配線電阻更低。
二極體6的配線電阻是圖4所示的陽極配線 電阻Rax與陰極配線電阻Rkx的和。陽極配線電阻Rax是表示連接陽極領域41與輸出線112的配線的電阻(亦包含陽極電極51的電阻)。陰極配線電阻Rkx是表示連接陰極領域42與電源線111的配線的電阻(亦包含陰極電極52的電阻)。
開關元件5的配線電阻是圖4所示的汲極配 線電阻Rdx與源極配線電阻Rsx的和。汲極配線電阻Rdx是表示連接汲極領域21與輸出線112的配線的電阻(亦包含汲極電極31的電阻)。源極配線電阻Rsx是表示連接源極領域22與電源線111的配線的電阻(亦包含源極電極32的電阻)。
例如，若使開關元件5的配線電阻 (Rsx+Rdx)形成10mΩ，使二極體6的配線電阻(Rax+Rkx)形成5mΩ，則比起開關元件5，來自線圈L的回生電流I1是更容易流至二極體6。
例如，藉由將二極體6的配線(亦包含陽極 電極51及陰極電極52)的寬度形成比開關元件5的配線(亦包含汲極電極31及源極電極32)的寬度更大，可使二極體6的配線電阻形成比開關元件5的配線電阻更低。
並且，藉由將電極對於二極體6的陽極領域 41及陰極領域42接觸的通孔數量形成比電極對於開關元件5的汲極領域21及源極領域22接觸的通孔數量更多，可使二極體6的配線電阻形成比開關元件5的配線電阻更低。
圖5是其他的實施形態的半導體裝置的模式 剖面圖。
在圖5所示的半導體裝置中，在開關元件5 的N型半導體層11與基板10之間設有N+型埋入層120。並且，在二極體6的N型半導體層12與基板10之間設有N+型埋入層120。並且，在邏輯元件7的N型半導體層13與基板10之間設有N+型埋入層120。
N+型埋入層120的N型雜質濃度是比N型半 導體層11的N型雜質濃度，N型半導體層12的N型雜質濃度，及N型半導體層13的N型雜質濃度更高。
N+型埋入層120的電位是被賦予電源電位 Vcc。藉由此N+型埋入層120，開關元件5，二極體6及邏輯元件7分別確實地從基板電位分離。
圖6是另外其他的實施形態的半導體裝置的 模式剖面圖。
在圖6所示的半導體裝置中，開關元件5及 二極體6是被形成於該等元件間未被分離連接的同N型半導體層15的表面。此情況，開關元件5及二極體6是藉由N型半導體層15來從P型基板10電性分離。
並且，實施形態的開關元件4，5，二極體6 是可適用在圖7所示的Motor Control Driver電路。圖7是表示雙極驅動方式的Motor Control Driver電路，為了在線圈L使電流流於2方向驅動，而使用2組的高側開關元件5及低側開關元件4。
在高側開關元件5及低側開關元件4的閘極是包含邏輯元件7的控制電路70的控制訊號會被輸出。亦即，控制電路70控制開關元件5，4的開啟關閉。
如圖8所示般，低側開關元件4也與高側開關元件5，二極體6及邏輯元件7一起形成於同基板10。
圖9A是表示基板10上的邏輯元件7，高側開關元件5，二極體6及低側開關元件4的配置關係的模式平面圖。
低側開關元件4是例如N通道型的DMOS，具有與P通道型的DMOS的高側開關元件5對應的要素的導電型為相反的同構造。在圖8所示的低側開關元件4中，與前述的高側開關元件5的各要素對應的要素是在符號附上"N"。
若根據以上說明的實施形態，則回生電流要比高側開關元件5更容易流至二極體6側。因此，為了抑制回生電流流至邏輯元件7側，最好使基板10上的二極 體6的位置與邏輯元件7的位置分開。
在Motor Control Driver電路等中，由於在高 側被賦予馬達電源電壓的最高電壓VM，因此雖二極體6與高側開關元件5間的寄生動作不成問題，但因為邏輯元件7的電源電壓Vcc大多比VM更低，所以一旦回生電流經由基板10流至邏輯元件7，則會因閂鎖而容易破壞。
於是，如圖8及圖9A所示般，在基板10 上，在邏輯元件7與二極體6之間配置高側開關元件5，藉此可抑制流至二極體6的回生電流經由基板10流至邏輯元件7。
或，如圖9B所示般，亦可在邏輯元件7與二 極體6之間配置高側開關元件5及低側開關元件4的雙方。
或，如圖9C所示般，亦可在邏輯元件7與二 極體6之間配置低側開關元件4。
以上說明了本發明的幾個實施形態，但該等的實施形態是舉例提示者，非意圖限定發明的範圍。該等新穎的實施形態是可在其他各種的形態下被實施，可在不脫離發明的要旨的範圍內進行各種的省略、置換、變更。該等實施形態或其變形是為發明的範圍或要旨所包含，且為申請專利範圍記載的發明及其均等的範圍所包含。
例如即使使用N型MOSFET作為開關元件也無妨。此情況，第1半導體層是成為P型半導體。例如藉由更追加包含第1半導體層的周圍的N型的半導體層，可將P 型的第1半導體層與P型半導體基板電性分離。因此，不限於半導體基板與第1半導體層形成不同的導電型。藉由設置將基板與第1半導體層電性分離的半導體層，即使基板與第1半導體層設為同導電型，還是可取得本案發明的效果。
而且，即使在二極體中也是將第2半導體層設為P型的二極體，還是可例如藉由更追加包含第2半導體層的周圍的N型的半導體層，來電性分離P型的第2半導體層與P型半導體基板。
5‧‧‧高側開關元件
6‧‧‧二極體
7‧‧‧邏輯元件
10‧‧‧基板
11‧‧‧N型半導體層
12‧‧‧N型半導體層
13‧‧‧N型半導體層
21‧‧‧P+型汲極領域
22‧‧‧P+型源極領域
23‧‧‧P型半導體領域
24‧‧‧N型半導體領域
26‧‧‧P-型半導體領域
27‧‧‧通道領域
28‧‧‧閘極電極
29‧‧‧閘極絕緣膜
30‧‧‧絕緣膜
31‧‧‧汲極電極
32‧‧‧源極電極
33‧‧‧N+型半導體領域
41‧‧‧P+型陽極領域
42‧‧‧N+型陰極領域
43‧‧‧P型半導體領域
44‧‧‧N型半導體領域
51‧‧‧陽極電極
52‧‧‧陰極電極
61‧‧‧N+型半導體領域
62‧‧‧N+型半導體領域
63‧‧‧P+型半導體領域
64‧‧‧N+型半導體領域
65‧‧‧P型半導體領域
66‧‧‧N型半導體領域
91‧‧‧寄生PNP電晶體
92‧‧‧寄生PNP電晶體
93‧‧‧寄生電阻
94‧‧‧基極電阻
95‧‧‧基極電阻
100‧‧‧NPN電晶體

Claims (16)

  1. 一種半導體裝置，其特徵係具備設在同基板上的開關元件及二極體，前述開關元件係具有：第1半導體層，其係設於前述基板內，與前述基板電性分離；第1半導體領域，其係設於前述第1半導體層的表面；第2半導體領域，其係於前述第1半導體層的表面對於前述第1半導體領域分離設置，與前述第1半導體領域同導電型；通道領域，其係設在前述第1半導體層的表面的前述第1半導體領域與前述第2半導體領域之間，與前述第1半導體領域及前述第2半導體領域的導電型相反導電型；閘極絕緣膜，其係設在前述通道領域上；閘極電極，其係設在前述閘極絕緣膜上；第1電極，其係被連接至前述第1半導體領域；及第2電極，其係被連接至前述第2半導體領域，前述二極體係具有：第2半導體層，其係設於前述基板內，與前述基板電性分離；陽極領域，其係設於前述第2半導體層的表面；陰極領域，其係於前述第2半導體層的表面對於前述陽極領域分離設置； 陽極電極，其係被連接至前述陽極領域；及陰極電極，其係被連接至前述陰極領域。
  2. 如申請專利範圍第1項之半導體裝置，其中，前述第1半導體層及前述第2半導體層係具有與前述基板的導電型相反的導電型，前述第1半導體層及前述第2半導體層係對於前述基板pn接合。
  3. 如申請專利範圍第1項之半導體裝置，其中，前述二極體的寄生電阻係比前述開關元件的寄生電阻更低。
  4. 如申請專利範圍第1項之半導體裝置，其中，前述第2半導體層的雜質濃度係比前述第1半導體層的雜質濃度更高。
  5. 如申請專利範圍第1項之半導體裝置，其中，前述二極體的前述陽極領域與前述陰極領域之間的距離係比前述開關元件的前述第1半導體領域與前述第2半導體領域之間的距離更短。
  6. 如申請專利範圍第1項之半導體裝置，其中，前述二極體的配線電阻係比前述開關元件的配線電阻更低。
  7. 如申請專利範圍第1項之半導體裝置，其中，前述第1半導體層及前述第2半導體層為同導電型，前述第1半導體層與前述第2半導體層係藉由與前述第1半導體層及前述第2半導體層相反導電型的領域來分離。
  8. 如申請專利範圍第1項之半導體裝置，其中，更 具備：設在前述基板與前述第1半導體層之間，及設在前述基板與前述第2半導體層之間，與前述基板相反導電型的埋入層。
  9. 如申請專利範圍第1項之半導體裝置，其中，前述開關元件係具有DMOS(double diffused metal oxide semiconductor field effect transistor)構造。
  10. 如申請專利範圍第1項之半導體裝置，其中，前述第2電極及前述陰極電極係具有與電源的連接端子，前述第1電極及前述陽極電極係具有與感應性負荷的連接端子。
  11. 如申請專利範圍第1項之半導體裝置，其中，在前述基板上更具備前述開關元件及與前述二極體不同構造的邏輯元件。
  12. 如申請專利範圍第11項之半導體裝置，其中，在前述基板上的前述邏輯元件與前述二極體之間設有前述開關元件。
  13. 如申請專利範圍第1項之半導體裝置，其中，前述開關元件係具有：P通道型DMOS(double diffused metal oxide semiconductor field effect transistor)，及與前述P通道型DMOS串聯的N通道型DMOS。
  14. 如申請專利範圍第13項之半導體裝置，其中，前述二極體係對於前述P通道型DMOS並聯。
  15. 如申請專利範圍第13項之半導體裝置，其中，在前述基板上更具備：前述P通道型DMOS，前述N通道 型DMOS，及與前述二極體不同構造的邏輯元件。
  16. 如申請專利範圍第15項之半導體裝置，其中，在前述基板上的前述邏輯元件與前述二極體之間設有前述P通道型DMOS及前述N通道型DMOS的至少任一個。
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JP6034268B2 (ja) * 2013-09-13 2016-11-30 株式会社東芝 半導体装置

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