TW201501255A - 底部塡充膜、密封片、半導體裝置之製造方法及半導體裝置 - Google Patents

底部塡充膜、密封片、半導體裝置之製造方法及半導體裝置 Download PDF

Info

Publication number
TW201501255A
TW201501255A TW103112617A TW103112617A TW201501255A TW 201501255 A TW201501255 A TW 201501255A TW 103112617 A TW103112617 A TW 103112617A TW 103112617 A TW103112617 A TW 103112617A TW 201501255 A TW201501255 A TW 201501255A
Authority
TW
Taiwan
Prior art keywords
underfill film
semiconductor element
semiconductor device
conductive filler
underfill
Prior art date
Application number
TW103112617A
Other languages
English (en)
Inventor
Kosuke Morita
Naohide Takamoto
Hiroyuki Hanazono
Akihiro Fukui
Original Assignee
Nitto Denko Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nitto Denko Corp filed Critical Nitto Denko Corp
Publication of TW201501255A publication Critical patent/TW201501255A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J7/00—Adhesives in the form of films or foils
    • C09J7/30—Adhesives in the form of films or foils characterised by the adhesive composition
    • C09J7/38—Pressure-sensitive adhesives [PSA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/295—Organic, e.g. plastic containing a filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J2301/00—Additional features of adhesives in the form of films or foils
    • C09J2301/30—Additional features of adhesives in the form of films or foils characterized by the chemical, physicochemical or physical properties of the adhesive or the carrier
    • C09J2301/302—Additional features of adhesives in the form of films or foils characterized by the chemical, physicochemical or physical properties of the adhesive or the carrier the adhesive being pressure-sensitive, i.e. tacky at temperatures inferior to 30°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68336—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding involving stretching of the auxiliary support post dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H01L2221/68386—Separation by peeling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16265—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
    • H01L2224/16268—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/27003—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the layer preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2743—Manufacturing methods by blanket deposition of the material of the layer connector in solid form
    • H01L2224/27436—Lamination of a preform, e.g. foil, sheet or layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/29386—Base material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757—Means for aligning
    • H01L2224/75753—Means for optical alignment, e.g. sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/8113—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Adhesive Tapes (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Dicing (AREA)

Abstract

本發明提供一種熱導性優異、且可良好地填充半導體元件與基板之間之空間的底部填充膜及密封片。 本發明係關於一種底部填充膜，其包含樹脂及熱導性填料，且上述熱導性填料之含量為50體積%以上，上述熱導性填料之平均粒徑相對於底部填充膜之厚度為30%以下之值，上述熱導性填料之最大粒徑相對於上述底部填充膜之厚度為80%以下之值。

Description

底部填充膜、密封片、半導體裝置之製造方法及半導體裝置
本發明係關於一種底部填充膜、密封片、半導體裝置之製造方法及半導體裝置。
作為提高半導體封裝體等之散熱性之方法，有設置散熱片等散熱構件之方法。
例如，專利文獻1中揭示有於邏輯LSI(Large Scale Integration，大型積體電路)中安裝散熱構件而將邏輯LSI之熱進行散熱的技術。專利文獻2中揭示有使驅動晶片之發熱傳導至散熱金屬箔而進行散熱的技術。
然而，不希望於數位相機或行動電話等對殼體尺寸有限制之機器內設置散熱構件。又，若設置散熱構件，則不僅必需散熱構件之構件費，製造製程亦增加，故而亦有帶來成本上升之問題。
然而，於覆晶安裝之半導體封裝體中，為了確保半導體元件與基板之間之連接可靠性，而對半導體元件與基板之間之空間填充底部填充材料(密封樹脂)。作為此種底部填充材料，廣泛使用液狀型(專利文獻3)。
[先前技術文獻] [專利文獻]
[專利文獻1]日本專利特開2008-258306號公報
[專利文獻2]日本專利特開2008-275803號公報
[專利文獻3]日本專利特開2011-176278號公報
作為提高覆晶安裝之半導體封裝體之散熱性之方法，認為有提高底部填充材料之熱導性之方法。然而，若為了提高熱導性而於液狀型底部填充材料中大量調配填料，則有黏度增高而難以填充半導體元件與基板之間之空間的情形。對於小型高密度之半導體封裝體，亦有無法填充之情形。
專利文獻3中揭示：藉由在底部填充組合物中調配二乙烯基芳烴二環氧化物而即便調配高等級之填料亦可獲得低黏度之底部填充組合物；但由於使用二氧化矽，故而熱導性不充分。又，由於為液狀型，故而對於填充性有改善之餘地。
本發明係鑒於上述問題而完成者，其目的在於提供一種熱導性優異、且可良好地填充半導體元件與基板之間之空間的底部填充膜及密封片。
本發明之底部填充膜包含樹脂及熱導性填料，且上述熱導性填料之含量為50體積%以上，上述熱導性填料之平均粒徑相對於底部填充膜之厚度為30%以下之值，上述熱導性填料之最大粒徑相對於上述底部填充膜之厚度為80%以下之值。
於本發明之底部填充膜中，相對於底部填充膜之厚度，而將熱導性填料之平均粒徑設為30%以下，且將熱導性填料之最大粒徑設為80%以下，故而可將熱導性填料之含量設定為50體積%以上之較高值。即，可相對密地填塞熱導性填料，故而可獲得優異之熱導性。又，使熱導性填料之平均粒徑及最大粒徑相對於底部填充膜之厚度最佳化，故而可良好地填充半導體元件與基板之間之空間。
本發明之底部填充膜較佳為熱導率為2W/mK以上。藉由此種熱導率，可將自半導體元件所產生之熱高效率地散熱至外部。
較佳為，上述熱導性填料之含量為50~80體積%，上述熱導性填料之平均粒徑相對於上述底部填充膜之厚度為10~30%之值，上述熱導性填料之最大粒徑相對於上述底部填充膜之厚度為40~80%之值。藉由將熱導性填料之含量及形態具體地設為此種特定值，可良好地提高底部填充膜之散熱性。
本發明之底部填充膜較佳為表面粗糙度(Ra)為300nm以下。由於採用特定含量及特定形態之熱導性填料，故而可將表面粗糙度(Ra)設為300nm以下。可藉由將表面粗糙度(Ra)設為300nm以下，而獲得與基板或晶片之良好接著力。
本發明之底部填充膜較佳為包含平均粒徑不同之熱導性填料作為上述熱導性填料。藉此，可將平均粒徑較小之熱導性填料填充至平均粒徑較大之熱導性填料之間，而可提高熱導性。
本發明之底部填充膜較佳為全光線透過率為50%以上。若全光線透過率為50%以上，則於下述包括位置校準步驟之製法中可精度良好地檢測半導體元件之位置，故而可容易地決定切割位置。又，亦可容易地形成半導體元件與被接著體間之電性連接。
本發明亦關於一種密封片，其具備上述底部填充膜及黏著帶，且上述黏著帶具有基材及設置於上述基材上之黏著劑層，上述底部填充膜設置於上述黏著劑層上。
上述底部填充膜自上述黏著劑層之剝離力較佳為0.03~0.10N/20mm。藉此，可防止切割時之晶片飛散。
上述黏著帶較佳為半導體晶圓之背面研削用帶或切割帶。
本發明亦關於一種半導體裝置之製造方法，其係具備被接著體、與上述被接著體電性連接之半導體元件、及填充上述被接著體與 上述半導體元件之間之空間之底部填充膜的半導體裝置之製造方法，且包括：準備步驟，其係準備於半導體元件貼合有上述底部填充膜的附底部填充膜之半導體元件；及連接步驟，其係以上述附底部填充膜之半導體元件之上述底部填充膜填充上述被接著體與上述半導體元件之間之空間，且將上述被接著體與上述半導體元件電性連接。
本發明之半導體裝置之製造方法較佳為包括位置校準步驟，其係對上述附底部填充膜之半導體元件之上述底部填充膜之露出面照射斜光，而使上述半導體元件與上述被接著體之相對位置校準為相互之連接預定位置。藉此，可容易地進行半導體元件與被接著體向連接預定位置之位置校準。
較佳為，對上述底部填充膜之露出面以5~85°之入射角照射斜光。藉由以此種入射角照射斜光，可防止正反射光而提高半導體元件之位置檢測精度，可進一步提高向連接預定位置之校準精度。
上述斜光較佳為包含400~550nm之波長。若斜光包含上述特定波長，則對於由包含無機填充劑之一般材料所形成之底部填充材料亦顯示出良好之穿透性，故而可更容易地進行半導體元件與被接著體向連接預定位置之校準。
較佳為，對上述底部填充膜之露出面自兩個以上之方向或全方向照射上述斜光。藉由來自多個方向或全方向(全周方向)之斜光照射，可增大來自半導體元件之漫反射而提高位置檢測之精度，可進一步提高半導體元件與被接著體向連接預定位置之校準精度。
本發明亦關於一種使用上述底部填充膜所製作之半導體裝置。
本發明亦關於一種利用上述方法所製作之半導體裝置。
1‧‧‧黏著帶
1a‧‧‧基材
1b‧‧‧黏著劑層
2‧‧‧底部填充膜
2a‧‧‧底部填充膜之露出面
3、43‧‧‧半導體晶圓
3a‧‧‧半導體晶圓之電路面
3b‧‧‧半導體晶圓之與電路面相反側之面
4、44‧‧‧連接構件
5、45‧‧‧半導體元件(半導體晶片)
6‧‧‧被接著體
7‧‧‧導通材料
10‧‧‧密封片
11‧‧‧切割帶
11a‧‧‧基材
11b‧‧‧黏著劑層
21、31、71‧‧‧攝像裝置
22、32、72‧‧‧環狀照明
30、80‧‧‧半導體裝置
L‧‧‧斜光
α‧‧‧斜光之入射角
圖1係本發明之密封片剖面之模式圖。
圖2A-2I係表示實施形態1之半導體裝置之製造方法之各步驟的 圖。
圖3係表示實施形態1之切割位置決定步驟的圖。
圖4係表示實施形態1之位置校準步驟的圖。
圖5A-5E係表示實施形態2之半導體裝置之製造方法之各步驟的圖。
[底部填充膜]
本發明之底部填充膜包含樹脂及熱導性填料，且上述熱導性填料之含量為50體積%以上，上述熱導性填料之平均粒徑相對於底部填充膜之厚度為30%以下之值，上述熱導性填料之最大粒徑相對於上述底部填充膜之厚度為80%以下之值。
本發明之底部填充膜包含熱導性填料。
作為熱導性填料，並無特別限定，例如可列舉：氧化鋁、氧化鋅、氧化鎂、氮化硼、氫氧化鎂、氮化鋁、碳化矽等電絕緣性者。該等可單獨使用或併用兩種以上。其中，氧化鋁就高傳導率且分散性優異、獲取容易性方面而言，較佳。
熱導性填料之熱導率只要可對底部填充膜賦予熱導性則並無特別限定，較佳為12W/mK以上，更佳為15W/mK以上，進而較佳為25W/mK以上。若熱導率為12W/mK以上，則可對底部填充膜賦予2W/mK以上之熱導性。熱導性填料之熱導率例如為70W/mK以下。
熱導性填料之含量於底部填充膜中為50體積%以上，較佳為55體積%以上。熱導性填料之含量為50體積%以上，故而可提高底部填充膜之熱導率，可將半導體封裝體中所產生之熱高效率地進行散熱。另一方面，熱導性填料之含量於底部填充膜中較佳為80體積%以下，更佳為75體積%以下。若熱導性填料之含量為80體積%以下，則可防止底部填充膜中之接著成分相對減少，可確保對半導體元件等之潤濕性 及接著性。
熱導性填料之平均粒徑相對於底部填充膜之厚度為30%以下，較佳為25%以下，進而較佳為5%以下，尤佳為4%以下。若超過30%，則有對基板、半導體元件之凹凸之覆蓋性不充分而產生空隙之情況。另一方面，平均粒徑之下限並無特別限定，相對於底部填充膜之厚度，較佳為0.5%以上，更佳為1%以上。
熱導性填料之最大粒徑相對於底部填充膜之厚度為80%以下，較佳為70%以下，更佳為40%以下，進而較佳為15%以下。若超過80%，則對半導體元件、基板之覆蓋性降低，並且有於連接端子間產生夾入而導致接合不良之情況。另一方面，最大粒徑之下限並無特別限定，相對於底部填充膜之厚度，較佳為1%以上，更佳為5%以上。再者，所謂熱導性填料之最大粒徑，係指於底部填充膜中所含之熱導性填料整體中最大之粒徑。
熱導性填料之平均粒徑及最大粒徑係利用雷射繞射式之粒度分佈計(HORIBA製造，裝置名：LA-910)所求出之值。
本發明之底部填充膜較佳為包含平均粒徑不同之熱導性填料。藉此，可將平均粒徑較小之熱導性填料填充至平均粒徑較大之熱導性填料之間，可提高熱導性。
平均粒徑較小之熱導性填料之平均粒徑相對於平均粒徑較大之熱導性填料之平均粒徑較佳為1~50%。若為上述範圍，則可進一步提高熱導性。
熱導性填料之粒子形狀並無特別限定，例如可列舉：球狀、橢圓球體狀、扁平形狀、針狀、纖維狀、薄片狀、穗狀(spike)、線圈狀等。該等形狀中，就分散性優異、可提高填充率方面而言，較佳為球狀。
本發明之底部填充膜包含樹脂。作為樹脂，並無特別限定，例 如可列舉：丙烯酸系樹脂、熱硬化性樹脂等。其中，較佳為併用丙烯酸系樹脂、熱硬化性樹脂。
作為上述丙烯酸系樹脂，並無特別限定，可列舉以具有碳數30以下、尤其是碳數4~18之直鏈或分支之烷基之丙烯酸或甲基丙烯酸之酯中之一種或兩種以上作為成分之聚合物等。作為上述烷基，例如可列舉：甲基、乙基、丙基、異丙基、正丁基、第三丁基、異丁基、戊基、異戊基、己基、庚基、環己基、2-乙基己基、辛基、異辛基、壬基、異壬基、癸基、異癸基、十一烷基、月桂基、十三烷基、十四烷基、硬脂基、十八烷基、或二十烷基等。
又，作為形成上述聚合物之其他單體，並無特別限定，例如可列舉：如丙烯腈之含氰基單體；如丙烯酸、甲基丙烯酸、丙烯酸羧基乙酯、丙烯酸羧基戊酯、伊康酸、順丁烯二酸、反丁烯二酸或丁烯酸等之含羧基單體；如順丁烯二酸酐或伊康酸酐等之酸酐單體；如(甲基)丙烯酸2-羥基乙酯、(甲基)丙烯酸2-羥基丙酯、(甲基)丙烯酸4-羥基丁酯、(甲基)丙烯酸6-羥基己酯、(甲基)丙烯酸8-羥基辛酯、(甲基)丙烯酸10-羥基癸酯、(甲基)丙烯酸12-羥基月桂酯或丙烯酸(4-羥基甲基環己基)-甲酯等之含羥基單體；如苯乙烯磺酸、烯丙基磺酸、2-(甲基)丙烯醯胺-2-甲基丙磺酸、(甲基)丙烯醯胺丙磺酸、(甲基)丙烯酸磺丙酯或(甲基)丙烯醯氧基萘磺酸等之含磺酸基單體；或如2-羥基乙基丙烯醯基磷酸酯等之含磷酸基單體。
底部填充膜中之丙烯酸系樹脂之含量較佳為2重量%以上，更佳為5重量%以上。若丙烯酸系樹脂之含量為2重量%以上，則可使片材具有可撓性而提高操作性。又，底部填充膜中之丙烯酸系樹脂之含量較佳為30重量%以下，更佳為25重量%以下。若丙烯酸系樹脂之含量為30重量%以下，則可獲得對基板、半導體元件之凹凸之充分覆蓋性。
作為上述熱硬化性樹脂，可列舉：酚樹脂、胺基樹脂、不飽和聚酯樹脂、環氧樹脂、聚胺基甲酸酯樹脂、聚矽氧樹脂、或熱硬化性聚醯亞胺樹脂等。該等樹脂可單獨使用或併用兩種以上。尤其就含有較少腐蝕半導體元件之離子性雜質等方面，就可抑制底部填充膜之糊劑於切割之切斷面溢出、可抑制切斷面彼此之再附著(黏連)方面而言，較佳為環氧樹脂。又，作為環氧樹脂之硬化劑，較佳為酚樹脂。
上述環氧樹脂只要為通常用作接著劑組合物者，則並無特別限定，例如可使用：雙酚A型、雙酚F型、雙酚S型、溴化雙酚A型、氫化雙酚A型、雙酚AF型、聯苯型、萘型、茀型、苯酚酚醛清漆型、鄰甲酚酚醛清漆型、三羥基苯基甲烷型、四酚基乙烷型等二官能環氧樹脂或多官能環氧樹脂，或乙內醯脲型、三縮水甘油基異氰尿酸酯型或縮水甘油胺型等環氧樹脂。該等可單獨使用，或併用兩種以上。該等環氧樹脂中，尤佳為：酚醛清漆型環氧樹脂、聯苯型環氧樹脂、三羥基苯基甲烷型樹脂或四酚基乙烷型環氧樹脂。其原因在於：該等環氧樹脂與作為硬化劑之酚樹脂之反應性豐富、耐熱性等優異。
進而，上述酚樹脂係作為上述環氧樹脂之硬化劑發揮作用者，例如可列舉：苯酚酚醛清漆樹脂、苯酚芳烷基樹脂、甲酚酚醛清漆樹脂、第三丁基苯酚酚醛清漆樹脂、壬基苯酚酚醛清漆樹脂等酚醛清漆型酚樹脂；可溶酚醛型酚樹脂、聚對羥基苯乙烯等聚羥基苯乙烯等。該等可單獨使用，或併用兩種以上。該等酚樹脂中，尤佳為苯酚酚醛清漆樹脂、苯酚芳烷基樹脂。其原因在於：可提高半導體裝置之連接可靠性。
上述環氧樹脂與酚樹脂之調配比率例如較佳為以相對於上述環氧樹脂成分中之環氧基每1當量而酚樹脂中之羥基成為0.5~2.0當量之方式進行調配。更佳為0.8~1.2當量。若脫離上述範圍，則不進行充分之硬化反應，底部填充膜之特性容易劣化。
底部填充膜中之熱硬化性樹脂之含量較佳為5重量%以上，更佳為10重量%以上。若熱硬化性樹脂之含量為5重量%以上，則硬化後之熱特性提高，容易保持可靠性。又，底部填充膜中之熱硬化性樹脂之含量較佳為80重量%以下，更佳為50重量%以下，進而較佳為30重量%以下。若熱硬化性樹脂之含量為80重量%以下，則容易保持可靠性。
作為環氧樹脂與酚樹脂之熱硬化促進觸媒，並無特別限制，可自公知之熱硬化促進觸媒中適當選擇而使用。熱硬化促進觸媒可單獨使用或組合兩種以上而使用。作為熱硬化促進觸媒，例如可使用：胺系硬化促進劑、磷系硬化促進劑、咪唑系硬化促進劑、硼系硬化促進劑、磷-硼系硬化促進劑等。
熱硬化促進觸媒之含量係相對於環氧樹脂及酚樹脂之合計含量100重量份，較佳為0.01重量份以上，更佳為0.1重量份以上。若熱硬化促進觸媒之含量為0.01重量份以上，則可使利用熱處理之硬化時間縮短而提高生產性。又，熱硬化促進觸媒之含量較佳為5重量份以下，更佳為2重量份以下。若熱硬化促進觸媒之含量為5重量份以下，則可提高熱硬化性樹脂之保存性。
為了去除焊料凸塊之表面之氧化膜而使半導體元件之安裝較為容易，亦可於底部填充膜中添加助焊劑。作為助焊劑，並無特別限定，可使用先前公知之具有助焊作用之化合物，例如可列舉：鄰甲氧基苯甲酸(o-anisic acid)、雙酚酸、己二酸、乙醯水楊酸、苯甲酸、二苯乙醇酸、壬二酸、苄基苯甲酸、丙二酸、2,2-雙(羥基甲基)丙酸、水楊酸、鄰甲氧基苯甲酸(o-methoxybenzoic acid)、間羥基苯甲酸、丁二酸、2,6-二甲氧基甲基對甲酚、苯甲醯肼、碳醯肼、丙二醯肼、丁二醯肼、戊二醯肼、水楊醯肼、亞胺基二乙二醯肼、伊康二醯肼、檸檬三醯肼、硫卡肼、二苯甲酮腙、4,4'-氧基雙苯磺醯肼及己二醯肼 等。助焊劑之添加量只要為發揮上述助焊作用之程度即可，通常相對於底部填充膜中所含之樹脂成分(丙烯酸系樹脂、熱硬化性樹脂等樹脂成分)100重量份為0.1~20重量份左右。
底部填充膜亦可視需要進行著色。底部填充膜中，作為藉由著色所呈現之色，並無特別限制，例如較佳為：黑色、藍色、紅色、綠色等。於進行著色時，可自顏料、染料等公知之著色劑中適當選擇而使用。
於使底部填充膜預先某種程度交聯之情形時，於製作時，亦可添加與聚合物之分子鏈末端之官能基等反應之多官能性化合物作為交聯劑。
作為上述交聯劑，尤佳為：甲苯二異氰酸酯、二苯基甲烷二異氰酸酯、對苯二異氰酸酯、1,5-萘二異氰酸酯、多元醇與二異氰酸酯之加成物等聚異氰酸酯化合物。
再者，可於底部填充膜中適當地調配除上述成分以外之其他添加劑。作為其他添加劑，例如可列舉：阻燃劑、矽烷偶合劑、離子捕捉劑等。作為上述阻燃劑，例如可列舉：三氧化二銻、五氧化二銻、溴化環氧樹脂等。該等可單獨使用，或併用兩種以上。作為上述矽烷偶合劑，例如可列舉：β-(3,4-環氧基環己基)乙基三甲氧基矽烷、γ-縮水甘油氧基丙基三甲氧基矽烷、γ-縮水甘油氧基丙基甲基二乙氧基矽烷等。該等化合物可單獨使用，或併用兩種以上。作為上述離子捕捉劑，例如可列舉：水滑石類、氫氧化鉍等。該等可單獨使用或併用兩種以上。
底部填充膜例如可以如下方式進行製作。首先，調配作為底部填充膜之形成材料之上述各成分，使其等溶解或分散於溶劑(例如，甲基乙基酮、乙酸乙酯等)中而製備塗佈液。繼而，將所製備之塗佈液以成為特定厚度之方式塗佈於基材分隔件上而形成塗佈膜後，將該 塗佈膜進行乾燥，而形成底部填充膜。
本發明之底部填充膜之熱導率通常為2W/mK以上，較佳為3W/mK以上，更佳為5W/mK以上。若熱導率為2W/mK以上，則可將半導體封裝體中所產生之熱高效率地進行散熱。熱導率之上限並無特別限定，例如為70W/mK以下。
本發明之底部填充膜於熱硬化前之表面粗糙度(Ra)較佳為300nm以下，更佳為250nm以下。若表面粗糙度(Ra)為300nm以下，則可獲得對基板或半導體元件之良好潤濕性。表面粗糙度(Ra)之下限並無特別限定，例如為10nm以上。
再者，表面粗糙度(Ra)係基於JIS B 0601，使用Veeco公司製造之非接觸三維粗糙度測定裝置(NT3300)進行測定。具體而言，可將測定條件設為50倍，對測定資料應用Median filter(中值濾波器)而求出測定值。
本發明之底部填充膜之厚度係考慮半導體元件與被接著體之間之差距或連接構件之高度而適當設定即可。例如，厚度較佳為10μm以上，更佳為15μm以上。又，厚度較佳為100μm以下，更佳為50μm以下。
本發明之底部填充膜較佳為受分隔件保護。分隔件具有於供於實用前作為保護底部填充膜之保護材料的功能。分隔件係於在底部填充膜上貼合半導體元件時被剝去。作為分隔件，亦可使用聚對苯二甲酸乙二酯(PET)、聚乙烯、聚丙烯、或經氟系剝離劑、丙烯酸長鏈烷基酯系剝離劑等剝離劑進行過表面塗佈的塑膠膜或紙等。
本發明之底部填充膜之全光線透過率越高越佳。具體而言，較佳為50%以上，更佳為60%以上，進而較佳為70%以上。再者，若為下述包含位置校準步驟之製法，則即便為50%左右之全光線透過率，亦可精度良好地檢測半導體元件之位置，故而切割位置之決定較為容 易。又，亦可容易地形成半導體元件與被接著體間之電性連接。
全光線透過率可依據JIS K 7361，使用霧度計HM-150(村上色彩技術研究所製造)進行測定。
本發明之底部填充膜可用作填充半導體元件與被接著體之間之空間的密封用膜。作為被接著體，可列舉：配線電路基板、撓性基板、插入式基板(interposer)、半導體晶圓、半導體元件等。
本發明之底部填充膜可與黏著帶一體化而使用。藉此，可高效率地製造半導體裝置。
[密封片(黏著帶一體型底部填充膜)]
本發明之密封片具備底部填充膜及黏著帶。
圖1係本發明之密封片10剖面之模式圖。如圖1所示，密封片10具備底部填充膜2及黏著帶1。黏著帶1具備基材1a及黏著劑層1b，且黏著劑層1b設置於基材1a上。底部填充膜2係設置於黏著劑層1b上。
再者，底部填充膜2如圖1所示般無需設置於黏著帶1之整個面，只要以足夠與半導體晶圓3(參照圖2A)貼合之尺寸設置即可。
黏著帶1具備：基材1a、及積層於基材1a上之黏著劑層1b。
上述基材1a係形成密封片10之強度母體者。例如可列舉：低密度聚乙烯、直鏈狀聚乙烯、中密度聚乙烯、高密度聚乙烯、超低密度聚乙烯、無規共聚聚丙烯、嵌段共聚聚丙烯、均聚丙烯、聚丁烯、聚甲基戊烯等聚烯烴、乙烯-乙酸乙烯酯共聚物、離子聚合物樹脂、乙烯-(甲基)丙烯酸共聚物、乙烯-(甲基)丙烯酸酯(無規、交替)共聚物、乙烯-丁烯共聚物、乙烯-己烯共聚物、聚胺基甲酸酯、聚對苯二甲酸乙二酯、聚萘二甲酸乙二酯等聚酯、聚碳酸酯、聚醯亞胺、聚醚醚酮、聚醯亞胺、聚醚醯亞胺、聚醯胺、全芳香族聚醯胺、聚苯硫醚、芳族聚醯胺(紙)、玻璃、玻璃布、氟樹脂、聚氯乙烯、聚偏二氯乙烯、纖維素系樹脂、聚矽氧樹脂、金屬(箔)、紙等。於黏著劑層1b為紫外線 硬化型之情形時，基材1a較佳為對紫外線具有穿透性。
可對基材1a之表面實施慣用之表面處理。
上述基材1a可適當地選擇而使用同種或異種者，亦可視需要使用摻和有複數種者。又，為了對基材1a賦予防靜電能力，可於上述基材1a上設置包含金屬、合金、該等之氧化物等之厚度為30~500Å左右之導電性物質之蒸鍍層。基材1a亦可為單層或兩種以上之複數層。
基材1a之厚度可適當地決定，通常為約5μm以上且200μm以下，較佳為35μm以上且120μm以下。
再者，基材1a中亦可於無損本發明之效果等之範圍內包含各種添加劑(例如，著色劑、填充劑、塑化劑、抗老化劑、抗氧化劑、界面活性劑、阻燃劑等)。
作為用於形成黏著劑層1b之黏著劑，並無特別限制，例如可使用丙烯酸系黏著劑、橡膠系黏著劑等通常之感壓性接著劑。作為上述感壓性接著劑，就利用超純水或醇等有機溶劑之潔淨洗淨性良好方面而言，較佳為以丙烯酸系聚合物作為基礎聚合物之丙烯酸系黏著劑。
作為上述丙烯酸系聚合物，可列舉將丙烯酸酯用作主單體成分者。作為上述丙烯酸酯，例如可列舉將(甲基)丙烯酸烷基酯(例如，甲酯、乙酯、丙酯、異丙酯、丁酯、異丁酯、第二丁酯、第三丁酯、戊酯、異戊酯、己酯、庚酯、辛酯、2-乙基己酯、異辛酯、壬酯、癸酯、異癸酯、十一烷基酯、十二烷基酯、十三烷基酯、十四烷基酯、十六烷基酯、十八烷基酯、二十烷基酯等烷基之碳數1~30、尤其是碳數4~18之直鏈狀或支鏈狀之烷基酯等)及(甲基)丙烯酸環烷基酯(例如，環戊酯、環己酯等)之一種或兩種以上用作單體成分的丙烯酸系聚合物等。再者，所謂(甲基)丙烯酸酯，係指丙烯酸酯及/或甲基丙烯酸酯，本發明之(甲基)均為相同之含義。
上述丙烯酸系聚合物為了凝集力、耐熱性等之改質，視需要亦 可包含對應可與上述(甲基)丙烯酸烷基酯或環烷基酯共聚之其他單體成分的單元。作為此種單體成分，例如可列舉：丙烯酸、甲基丙烯酸、(甲基)丙烯酸羧基乙酯、(甲基)丙烯酸羧基戊酯、伊康酸、順丁烯二酸、反丁烯二酸、丁烯酸等含羧基單體；順丁烯二酸酐、伊康酸酐等酸酐單體；(甲基)丙烯酸2-羥基乙酯、(甲基)丙烯酸2-羥基丙酯、(甲基)丙烯酸4-羥基丁酯、(甲基)丙烯酸6-羥基己酯、(甲基)丙烯酸8-羥基辛酯、(甲基)丙烯酸10-羥基癸酯、(甲基)丙烯酸12-羥基月桂酯、(4-羥基甲基環己基)甲基(甲基)丙烯酸酯等含羥基單體；苯乙烯磺酸、烯丙基磺酸、2-(甲基)丙烯醯胺-2-甲基丙磺酸、(甲基)丙烯醯胺丙磺酸、(甲基)丙烯酸磺丙酯、(甲基)丙烯醯氧基萘磺酸等含磺酸基單體；2-羥基乙基丙烯醯基磷酸酯等含磷酸基單體；丙烯醯胺、丙烯腈等。該等可共聚之單體成分可使用一種或兩種以上。該等可共聚之單體之使用量較佳為全部單體成分之40重量%以下。
進而，上述丙烯酸系聚合物為了進行交聯，視需要亦可含有多官能性單體等作為共聚用單體成分。作為此種多官能性單體，例如可列舉：己二醇二(甲基)丙烯酸酯、(聚)乙二醇二(甲基)丙烯酸酯、(聚)丙二醇二(甲基)丙烯酸酯、新戊二醇二(甲基)丙烯酸酯、季戊四醇二(甲基)丙烯酸酯、三羥甲基丙烷三(甲基)丙烯酸酯、季戊四醇三(甲基)丙烯酸酯、二季戊四醇六(甲基)丙烯酸酯、環氧(甲基)丙烯酸酯、(甲基)丙烯酸聚酯、(甲基)丙烯酸胺基甲酸酯等。該等多官能性單體亦可使用一種或兩種以上。多官能性單體之使用量就黏著特性等方面而言，較佳為全部單體成分之30重量%以下。
上述丙烯酸系聚合物可藉由將單一單體或兩種以上單體混合物供於聚合而獲得。聚合亦可利用溶液聚合、乳化聚合、塊狀聚合、懸濁聚合等中任一種方式進行。就防止對潔淨之被接著體之污染等方面而言，較佳為低分子量物質之含量較小。就該方面而言，丙烯酸系聚 合物之數量平均分子量較佳為30萬以上，進而較佳為40萬~300萬左右。
又，上述黏著劑中，為了提高作為基礎聚合物之丙烯酸系聚合物等之數量平均分子量，亦可適當地採用外部交聯劑。作為外部交聯方法之具體方法，可列舉添加聚異氰酸酯化合物、環氧化合物、氮丙啶化合物、三聚氰胺系交聯劑等所謂之交聯劑而進行反應之方法。於使用外部交聯劑之情形時，其使用量係根據其與應交聯之基礎聚合物之平衡、進而根據作為黏著劑之使用用途而適當決定。一般而言，相對於上述基礎聚合物100重量份，較佳為調配約5重量份以下，進而較佳為調配0.1~5重量份。進而，黏著劑中，視需要除上述成分以外亦可使用先前公知之各種黏著賦予劑、抗老化劑等添加劑。
黏著劑層1b可由放射線硬化型黏著劑而形成。放射線硬化型黏著劑可藉由紫外線等放射線之照射而增大交聯度，從而容易地降低其黏著力。作為放射線，可列舉：X射線、紫外線、電子束、α射線、β射線、中子射線等。
放射線硬化型黏著劑可無特別限定地使用具有碳-碳雙鍵等放射線硬化性官能基、且顯示黏著性者。作為放射線硬化型黏著劑，例如可例示於上述丙烯酸系黏著劑、橡膠系黏著劑等通常之感壓性黏著劑中調配有放射線硬化性單體成分或低聚物成分的添加型放射線硬化性黏著劑。
作為調配之放射線硬化性之單體成分，例如可列舉：胺基甲酸酯低聚物、(甲基)丙烯酸胺基甲酸酯、三羥甲基丙烷三(甲基)丙烯酸酯、四羥甲基甲烷四(甲基)丙烯酸酯、季戊四醇三(甲基)丙烯酸酯、季戊四醇四(甲基)丙烯酸酯、二季戊四醇單羥基五(甲基)丙烯酸酯、二季戊四醇六(甲基)丙烯酸酯、1,4-丁二醇二(甲基)丙烯酸酯等。又，放射線硬化性之低聚物成分可列舉：胺基甲酸酯系、聚醚系、聚酯 系、聚碳酸酯系、聚丁二烯系等各種低聚物，較合適為其重量平均分子量為100~30000左右之範圍者。放射線硬化性之單體成分或低聚物成分之調配量可根據上述黏著劑層之種類而適當地決定可降低黏著劑層之黏著力之量。一般而言，相對於構成黏著劑之丙烯酸系聚合物等基礎聚合物100重量份，例如為5~500重量份，較佳為40~150重量份左右。
又，作為放射線硬化型黏著劑，除上述說明之添加型放射線硬化性黏著劑以外，亦可列舉使用在聚合物側鏈或主鏈中或主鏈末端具有碳-碳雙鍵者作為基礎聚合物的內在型放射線硬化性黏著劑。內在型放射線硬化性黏著劑無需含有作為低分子成分之低聚物成分等，或含量不大，故而並無低聚物成分等經過一段時間於黏著劑中移動，而可形成層結構穩定之黏著劑層，故而較佳。
上述具有碳-碳雙鍵之基礎聚合物可無特別限制地使用具有碳-碳雙鍵、且具有黏著性者。作為此種基礎聚合物，較佳為以丙烯酸系聚合物作為基本骨架者。作為丙烯酸系聚合物之基本骨架，可列舉上述例示之丙烯酸系聚合物。
向上述丙烯酸系聚合物導入碳-碳雙鍵之導入法並無特別限制，可採用各種方法，但將碳-碳雙鍵導入至聚合物側鏈中時分子設計較為容易。例如，可列舉如下方法：預先使具有官能基之單體共聚成丙烯酸系聚合物，此後使具有可與該官能基反應之官能基及碳-碳雙鍵之化合物維持碳-碳雙鍵之放射線硬化性而進行縮合或加成反應。
作為該等官能基之組合之例，可列舉：羧酸基與環氧基、羧酸基與氮丙啶基、羥基與異氰酸酯基等。於該等官能基之組合中，就追蹤反應之容易性而言，較佳為羥基與異氰酸酯基之組合。又，只要為如藉由該等官能基之組合而生成上述具有碳-碳雙鍵之丙烯酸系聚合物的組合，則官能基可位於丙烯酸系聚合物與上述化合物任一側，於 上述較佳之組合中，較佳為丙烯酸系聚合物具有羥基、上述化合物具有異氰酸酯基之情形。於該情形時，作為具有碳-碳雙鍵之異氰酸酯化合物，例如可列舉：甲基丙烯醯基異氰酸酯、2-甲基丙烯醯氧基乙基異氰酸酯、間異丙烯基-α,α-二甲基苄基異氰酸酯等。又，作為丙烯酸系聚合物，可使用使上述例示之含羥基單體或2-羥基乙基乙烯醚、4-羥基丁基乙烯醚、二乙二醇單乙烯醚之醚系化合物等共聚而成者。
上述內在型放射線硬化性黏著劑可單獨使用上述具有碳-碳雙鍵之基礎聚合物(尤其是丙烯酸系聚合物)，亦可以不使特性劣化之程度調配上述放射線硬化性之單體成分或低聚物成分。放射線硬化性之低聚物成分等通常相對於基礎聚合物100重量份為30重量份之範圍內，較佳為0~10重量份之範圍。
上述放射線硬化型黏著劑中，於藉由紫外線等進行硬化之情形時，較佳為含有光聚合起始劑。作為光聚合起始劑，例如可列舉：4-(2-羥基乙氧基)苯基(2-羥基-2-丙基)酮、α-羥基-α,α'-二甲基苯乙酮、2-甲基-2-羥基苯丙酮、1-羥基環己基苯基酮等α-酮醇系化合物；甲氧基苯乙酮、2,2-二甲氧基-2-苯基苯乙酮、2,2-二乙氧基苯乙酮、2-甲基-1-[4-(甲硫基)-苯基]-2-嗎啉基丙烷-1等苯乙酮系化合物；安息香乙醚、安息香異丙醚、茴香偶姻甲醚等安息香醚系化合物；苯偶醯二甲基縮酮等縮酮系化合物；2-萘磺醯氯等芳香族磺醯氯系化合物；1-苯酮-1,1-丙烷二酮-2-(o-乙氧基羰基)肟等光活性肟系化合物；二苯甲酮、苯甲醯苯甲酸、3,3'-二甲基-4-甲氧基二苯甲酮等二苯甲酮系化合物；噻噸酮、2-氯噻噸酮、2-甲基噻噸酮、2,4-二甲基噻噸酮、異丙基噻噸酮、2,4-二氯噻噸酮、2,4-二乙基噻噸酮、2,4-二異丙基噻噸酮等噻噸酮系化合物；樟腦醌；鹵代酮；醯基膦氧化物；醯基磷酸酯等。光聚合起始劑之調配量係相對於構成黏著劑之丙烯酸系聚合物等之基礎聚合物100重量份例如為約0.05~20重量份。
再者，於在放射線照射時由氧引起硬化阻礙之情形時，較理想為利用任意之方法自放射線硬化型之黏著劑層1b之表面阻斷氧(空氣)。例如，可列舉：以分隔件被覆上述黏著劑層1b之表面之方法、或於氮氣環境中進行紫外線等放射線之照射之方法等。
再者，黏著劑層1b中亦可包含各種添加劑(例如，著色劑、增黏劑、增量劑、填充劑、黏著賦予劑、塑化劑、抗老化劑、抗氧化劑、界面活性劑、交聯劑等)。
黏著劑層1b之厚度並無特別限定，例如為約1~50μm，較佳為2~30μm，進而較佳為5~25μm。
作為黏著帶1，可較佳地使用半導體晶圓之背面研削用帶、切割帶。
密封片10例如可藉由分別製作黏著帶1及底部填充膜2並於最後將該等貼合而製成。
於密封片10中，底部填充膜2自黏著劑層1b之剝離力較佳為0.03~0.10N/20mm。若剝離力為0.03N/20mm以上，則可防止切割時之晶片飛散。若剝離力為0.10N/20mm以下，則可獲得良好之拾取性。
[半導體裝置之製造方法]
本發明之半導體裝置之製造方法係製造具備被接著體、與上述被接著體電性連接之半導體元件、及填充上述被接著體與上述半導體元件之間之空間之底部填充膜的半導體裝置。
而且，本發明之半導體裝置之製造方法包括：準備步驟，其係準備於半導體元件貼合有底部填充膜之附底部填充膜之半導體元件；及連接步驟，其係以上述附底部填充膜之半導體元件之上述底部填充膜填充上述被接著體與上述半導體元件之間之空間且將上述被接著體與上述半導體元件電性連接。
本發明之半導體裝置之製造方法只要包括準備步驟及連接步 驟，則並無特別限定，但較佳為包括位置校準步驟，其係對上述附底部填充膜之半導體元件之上述底部填充膜之露出面照射斜光，而使上述半導體元件與上述被接著體之相對位置校準為相互之連接預定位置。藉此，可容易地進行半導體元件與被接著體向連接預定位置之位置校準。
以下，揭示實施形態，詳細地說明本發明之半導體裝置之製造方法，但本發明之半導體裝置之製造方法並不限定於該等實施形態。
(實施形態1)
對實施形態1之半導體裝置之製造方法進行說明。圖2係表示實施形態1之半導體裝置之製造方法之各步驟的圖。
於實施形態1中使用密封片10。
實施形態1之半導體裝置之製造方法包括：貼合步驟，其係將半導體晶圓3之形成有連接構件4之電路面3a與密封片10之底部填充膜2進行貼合；研削步驟，其係對半導體晶圓3之背面3b進行研削；晶圓固定步驟，其係於半導體晶圓3之背面3b貼附切割帶11；剝離步驟，其係將黏著帶1剝離；切割位置決定步驟，其係對附底部填充膜2之半導體晶圓3之底部填充膜2之露出面照射斜光L，而決定切割位置；切割步驟，其係將半導體晶圓3切割而形成附底部填充膜2之半導體元件5；及拾取步驟，其係將附底部填充膜2之半導體元件5自切割帶11剝離；位置校準步驟，其係對附底部填充膜2之半導體元件5之底部填充膜2之露出面照射斜光L，而使半導體元件5與被接著體6之相對位置校準為相互之連接預定位置；及連接步驟，其係以附底部填充膜2之半導體元件5之底部填充膜2填充被接著體6與半導體元件5之間之空間且將被接著體6與半導體元件5電性連接。
<貼合步驟>
於貼合步驟中，將半導體晶圓3之形成有連接構件4之電路面3a與 密封片10之底部填充膜2進行貼合(參照圖2A)。
於半導體晶圓3之電路面3a形成有複數個連接構件4(參照圖2A)。作為連接構件4之材質，並無特別限定，例如可列舉：錫-鉛系金屬材、錫-銀系金屬材、錫-銀-銅系金屬材、錫-鋅系金屬材、錫-鋅-鉍系金屬材等焊料類(合金)、或金系金屬材、銅系金屬材等。連接構件4之高度亦可根據用途而決定，通常為約15~100μm。當然，半導體晶圓3中之每個連接構件4之高度可相同亦可不同。
首先，將任意地設置於密封片10之底部填充膜2上之分隔件適當地剝離，如圖2A所示，使半導體晶圓3之形成有連接構件4之電路面3a與底部填充膜2對向，而將底部填充膜2與半導體晶圓3進行貼合(安裝)。
貼合之方法並無特別限定，較佳為利用壓接之方法。壓接之壓力較佳為0.1MPa以上，更佳為0.2MPa以上。若壓接之壓力為0.1MPa以上，則可良好地覆蓋半導體晶圓3之電路面3a之凹凸。又，壓接之壓力之上限並無特別限定，較佳為1MPa以下，更佳為0.5MPa以下。
貼合之溫度較佳為60℃以上，更佳為70℃以上。若貼合之溫度為60℃以上，則底部填充膜2之黏度降低，可無空隙地填充半導體晶圓3之凹凸。又，貼合之溫度較佳為100℃以下，更佳為80℃以下。若貼合之溫度為100℃以下，則可抑制底部填充膜2之硬化反應而進行貼合。
貼合較佳為於減壓下進行，例如為1000Pa以下，較佳為500Pa以下。下限並無特別限定，例如為1Pa以上。
<研削步驟>
於研削步驟中，對半導體晶圓3之與電路面3a相反側之面(即，背面)3b進行研削(參照圖2B)。作為用於半導體晶圓3之背面研削之薄型 加工機，並無特別限定，例如可例示研削機(背面研削機)、研磨墊等。又，亦可利用蝕刻等化學方法進行背面研削。背面研削係進行至半導體晶圓3成為所需厚度(例如，700~25μm)為止。
<晶圓固定步驟>
於研削步驟後，於半導體晶圓3之背面3b貼附切割帶11(參照圖2C)。再者，切割帶11具有在基材11a上積層有黏著劑層11b之構造。 作為基材11a及黏著劑層11b，可使用黏著帶1之基材1a及黏著劑層1b之項中所示之成分及製法而較佳地製作。
<剝離步驟>
繼而，將黏著帶1剝離(參照圖2D)。藉此，使底部填充膜2成為露出之狀態。
於將背面研削用帶1剝離時，於黏著劑層1b具有放射線硬化性之情形時，可藉由對黏著劑層1b照射放射線而使黏著劑層1b硬化，而容易地進行剝離。放射線之照射量係考慮使用之放射線之種類或黏著劑層之硬化度等而適當設定即可。
<切割位置決定步驟>
如圖2E及圖3所示，對附底部填充膜2之半導體晶圓3之底部填充膜2之露出面照射斜光L，而決定半導體晶圓3中之切割位置。藉此，可以高精度檢測半導體晶圓3之切割位置，可簡便且高效率地進行半導體晶圓3之切割。
具體而言，於固定於切割帶11之半導體晶圓3之上方，配置攝像裝置21及環狀照明(發光面呈圓狀之照明)22。繼而，自環狀照明22對底部填充膜2之露出面2a以特定之入射角α照射斜光L。進入至底部填充膜2且被半導體晶圓3反射之光被攝像裝置21接收為反射像。利用圖像識別裝置分析所接收之反射像，而決定應切割之位置。其後，藉由移動切割裝置(例如，切割刀片、雷射振盪器等)並校準為切割位置， 而完成本步驟(未圖示)。
作為用於斜光照射之照明，可如上所述較佳地使用環狀照明22，但並不限定於此，可使用：線狀照明(發光面呈直線狀之照明)或點狀照明(發光面呈點狀之照明)等。又，亦可為將複數個線狀照明組合成多邊形狀的照明、將點狀照明組合成多邊形狀或環狀的照明。
作為照明之光源，並無特別限定，可列舉：鹵素燈、LED(light-emitting diode，發光二極體)、螢光燈、鎢燈、金屬鹵化物燈、氙燈、黑光燈等。又，自光源所照射之斜光L可為平行光線或放射光線(非平行光線)中之任一者，若考慮照射效率或設定上述入射角α之容易性，則較佳為平行光線。其中，於以平行光線之形式照射斜光L時具有物理上之限度，故而只要為實質上之平行光線(半值角為30°以內)即可。又，斜光L亦可為偏振光。
於本實施形態中，較佳為自兩個以上之方向或全方向對底部填充膜2之露出面2a照射斜光L。藉由自多個方向或全方向(全周方向)之斜光照射，可增大來自半導體晶圓3之漫反射而提高位置檢測之精度，可進一步提高切割位置之檢測之精度。來自多個方向之照射可將上述線狀照明或點狀照明之一者或兩者組合等而進行。又，全方向或全周方向之照射可藉由將上述複數個線狀照明組合成多角形狀、或使用環狀照明而容易地進行。
作為上述入射角α，只要對底部填充膜2之露出面2a傾斜地照射斜光L，則並無特別限定，但較佳為5~85°，更佳為15~75°，尤佳為30~60°。藉由將入射角α設為上述範圍，可防止成為光暈現象之原因之來自半導體晶圓3之正反射光，而提高半導體晶圓3之切割位置之檢測精度。再者，若斜光L為放射光線(非平行光線)，則有因斜光L之照射起點與底部填充膜2之露出面2a上之到達點之關係而於入射角α產生某種程度之寬度的情形。於該情形時，只要斜光L之光量成為最大時之 角度處於上述入射角α之範圍內即可。
作為上述斜光L之波長，只要獲得來自半導體晶圓3之反射像、且不對半導體晶圓3造成損傷，則並無特別限定，較佳為400~550nm。若斜光L之波長為上述範圍，則可使斜光L良好地穿透底部填充膜2，故而可更容易地進行切割位置之檢測。
又，作為用於利用斜光照射之位置檢測的半導體晶圓3中之辨識對象，於圖2E及圖3中為形成於半導體晶圓3之連接構件(例如凸塊)4，但並不限定於此，亦可以對準標記、端子、電路圖案等任意之標記或構造物作為辨識對象。
<切割步驟>
於切割步驟中，如圖2F所示將半導體晶圓3及底部填充膜2切割而形成經切割之附底部填充膜2之半導體元件5。切割係根據常法自半導體晶圓3之貼合有底部填充膜2之電路面3a進行。例如，可採用進行切入直至切割帶11之被稱為全切之切斷方式等。作為用於本步驟之切割裝置，並無特別限定，可使用先前公知者。
再者，繼切割步驟後進行切割帶11之擴展之情形時，該擴展可使用先前公知之擴展裝置進行。
<拾取步驟>
為了回收接著固定於切割帶11之附底部填充膜2之半導體元件5，如圖2F所示，將附底部填充膜2之半導體元件5自切割帶11剝離(拾取附底部填充膜2之半導體元件5)。
作為拾取之方法，並無特別限定，可採用先前公知之各種方法。
此處，拾取係於切割帶11之黏著劑層11b為紫外線硬化型之情形時，對該黏著劑層11b照射紫外線後進行。藉此，黏著劑層11b對半導體元件5之黏著力降低，半導體元件5之剝離變得容易。其結果為，可 不損傷半導體元件5而進行拾取。
[位置校準步驟]
繼而，於位置校準步驟中，如圖2H及圖4所示，對附底部填充膜2之半導體元件5之底部填充膜2之露出面照射斜光L，而使半導體元件5與被接著體6之相對位置校準為相互之連接預定位置。藉此，可以高精度檢測半導體元件5之位置，可簡便且高效率地進行半導體元件5與被接著體6向連接預定位置之校準。
具體而言，以半導體元件5之形成有連接構件4之面(對應半導體晶圓3之電路面3a)與被接著體6對向之方式，將附底部填充膜2之半導體元件5配置於被接著體6之上方。繼而，將攝像裝置31及環狀照明32配置於附底部填充膜2之半導體元件5與被接著體6之間後，自環狀照明32朝向附底部填充膜2之半導體元件5對底部填充膜2之露出面2a以特定之入射角α照射斜光L。進入至底部填充膜2且被半導體元件5反射之光被攝像裝置31接收為反射像。繼而，利用圖像識別裝置分析所接收之反射像，求出與預先決定之連接預定位置之偏差，最後，使附底部填充膜2之半導體元件5僅移動所求出之偏差量，而使半導體元件5與被接著體6之相對位置校準為連接預定位置(未圖示)。
該位置校準步驟中之斜光照射之態樣與切割位置決定步驟中之斜光照射僅底部填充膜2之露出面2a與攝像裝置31及照明32之位置上下反轉。因此，作為用於斜光照射之各條件，例如，用於斜光照射之照明、照明之光源、照射方向、入射角α之範圍、斜光之波長、用於利用斜光照射之位置檢測之半導體元件中之辨識對象等，可較佳地採用切割位置決定步驟一項中所說明之條件，且可獲得相同之效果。
<連接步驟>
於連接步驟中，以附底部填充膜2之半導體元件5之底部填充膜2填充被接著體6與半導體元件5之間之空間，且將半導體元件5與被接 著體6電性連接(參照圖2I)。
具體而言，一面使形成於半導體元件5之連接構件4接觸被接著於被接著體6之連接墊的接合用導電材料7並進行推壓，一面使導電材料7熔融，藉此可使半導體元件5與被接著體6電性連接。於半導體元件5之形成有連接構件4之面貼附有底部填充膜2，故而將半導體元件5與被接著體6電性連接之同時，半導體元件5與被接著體6之間之空間被底部填充膜2填充。
連接步驟中之加熱條件並無特別限定，通常加熱條件為100~300℃，加壓條件為0.5~500N。
<硬化步驟>
較佳為，進行半導體元件5與被接著體6之電性連接後，藉由對底部填充膜2進行加熱而使其硬化。藉此，可保護半導體元件5之表面，並且可確保半導體元件5與被接著體6之間之連接可靠性。作為用以使底部填充膜2硬化之加熱溫度，並無特別限定，例如於150~200℃下進行10~120分鐘。再者，亦可藉由連接步驟中之加熱處理而使底部填充膜2硬化。
<密封步驟>
繼而，亦可進行密封步驟用以保護具備所安裝之半導體元件5之半導體裝置30整體。密封步驟係使用密封樹脂進行。作為此時之密封條件，並無特別限定，通常藉由在175℃下進行60秒~90秒之加熱，而進行密封樹脂之熱硬化，但本發明並不限定於此，例如可於165℃~185℃下進行數分鐘固化。
作為密封樹脂，較佳為具有絕緣性之樹脂(絕緣樹脂)，可自公知之密封樹脂中適當選擇而使用。
<半導體裝置>
於半導體裝置30中，將半導體元件5與被接著體6經由形成於半 導體元件5上之連接構件4及設置於被接著體6上之導電材料7而電性連接。又，於半導體元件5與被接著體6之間，以填充其空間之方式配置有底部填充膜2。半導體裝置30可利用採用藉由斜光照射之位置對準的製造方法而獲得，故而於半導體元件5與被接著體6之間達成良好之電性連接。
(實施形態2)
對實施形態2之半導體裝置之製造方法進行說明。圖5係表示實施形態2之半導體裝置之製造方法之各步驟的圖。
於實施形態2中使用密封片10。
實施形態2之半導體裝置之製造方法包括：貼合步驟，其係將兩面形成有具有連接構件44之電路面之半導體晶圓43與密封片10之底部填充膜2進行貼合；切割步驟，其係將半導體晶圓43切割而形成附底部填充膜2之半導體晶片45；拾取步驟，其係將附底部填充膜2之半導體晶片45自黏著帶1剝離；位置校準步驟，其係對附底部填充膜2之半導體元件45之底部填充膜2之露出面照射斜光L，而使半導體元件45與被接著體6之相對位置校準為相互之連接預定位置；及連接步驟，其係以附底部填充膜2之半導體元件45之底部填充膜2填充被接著體6與半導體元件45之間之空間且將被接著體6與半導體元件45電性連接。
<貼合步驟>
於貼合步驟中，如圖5A所示，將兩面形成有具有連接構件44之電路面之半導體晶圓43與密封片10之底部填充膜2進行貼合。再者，通常半導體晶圓43之強度較弱，故而有為了補強而將半導體晶圓43固定於支持玻璃等支持體之情況(未圖示)。於該情形時，亦可包括如下步驟：於半導體晶圓43與底部填充膜2貼合後，將支持體剝離。關於將半導體晶圓43之哪一電路面與底部填充膜2進行貼合，根據目標之半導體裝置之構造進行變更即可。
半導體晶圓43之兩面之連接構件44彼此可電性連接，亦可不連接。於連接構件44彼此之電性連接中，可列舉被稱為TSV(Through Silicon Via，矽通孔)形式之利用經由通孔之連接而進行者等。作為貼合條件，可採用實施形態1之貼合步驟中所例示之條件。
<切割步驟>
於切割步驟中，將半導體晶圓43及底部填充膜2切割而形成附底部填充膜2之半導體晶片45(參照圖45)。作為切割條件，可採用實施形態1之切割步驟中所例示之條件。
<拾取步驟>
於拾取步驟中，將附底部填充膜2之半導體晶片45自黏著帶1剝離(圖5C)。作為拾取條件，可採用實施形態1之拾取步驟中所例示之條件。
<位置校準步驟>
對附底部填充膜2之半導體元件45之底部填充膜2之露出面照射斜光L，而使半導體元件45與被接著體6之相對位置校準為相互之連接預定位置(圖5D)。具體之位置校準方法可採用與實施形態1相同之方法。
<連接步驟>
於連接步驟中，以附底部填充膜2之半導體元件45之底部填充膜2填充被接著體6與半導體元件45之間之空間，且將被接著體6與半導體元件45電性連接。具體之連接方法係與實施形態1之連接步驟中所說明之內容相同。
<硬化步驟及密封步驟>
硬化步驟及密封步驟係與實施形態1之硬化步驟及密封步驟中所說明之內容相同。藉此，可製造半導體裝置80。
(實施形態3)
對實施形態3之半導體裝置之製造方法進行說明。實施形態3中，使用於基材上設置有底部填充膜者代替密封片10，除此以外，與實施形態1相同。作為基材，可使用與基材1a相同者。
[實施例]
以下，例示性地詳細說明該發明之較佳實施例。然而，該實施例中所記載之材料或調配量等只要並無特別限定性之記載，則並非旨在將本發明之範圍僅限定於該等。
以下，對實施例及比較例中所使用之各種成分匯總進行說明。
丙烯酸系樹脂：根上工業股份有限公司製造之PARACRON W-197CM(以丙烯酸乙酯-甲基丙烯酸甲酯作為主成分之丙烯酸酯系聚合物)
環氧樹脂1：JER股份有限公司製造之Epikote 1004
環氧樹脂2：JER股份有限公司製造之Epikote 828
酚樹脂：三井化學股份有限公司製造之Milex XLC-4L
氧化鋁填料1：CIK NanoTek股份有限公司製造之ALMEK30WT%-N40(平均粒徑0.35μm，最大粒徑3.0μm，熱導率40W/mK)
氧化鋁填料2：昭和電工股份有限公司製造之AS-50(平均粒徑9.3μm，最大粒徑30μm，熱導率41W/mK)
氧化鋁填料3：電氣化學工業股份有限公司製造之DAW-07(平均粒徑8.2μm，最大粒徑27μm，熱導率40W/mK)
氧化鋁填料4：電氣化學工業股份有限公司製造之DAW-05(平均粒徑5.1μm，最大粒徑18μm，熱導率40W/mK)
有機酸：東京化成股份有限公司製造之鄰甲氧基苯甲酸(o-anisic acid)
咪唑觸媒：四國化成股份有限公司製造之2PHZ-PW(2-苯基-4,5- 二羥基甲基咪唑)
[實施例1~2及比較例1~3]
(底部填充膜之製作)
根據表1所示之調配比，將各成分溶解於甲基乙基酮中，製備固形物成分濃度成為23.6重量%之接著劑組合物之溶液。
將該接著劑組合物之溶液塗佈於經聚矽氧脫模處理之由厚度為50μm之聚對苯二甲酸乙二酯膜構成之脫模處理膜上後，於130℃下乾燥2分鐘，藉此製作厚度30μm之底部填充膜。
對於所獲得之底部填充膜進行以下評價。將結果示於表1。
(表面粗糙度(Ra))
底部填充膜之表面粗糙度(Ra)係基於JIS B 0601，使用Veeco公司製造之非接觸三維粗糙度測定裝置(NT3300)進行測定。測定條件係設為50倍，測定值係對測定資料應用Median filter而求出。測定係變更測定部位而進行5次，並將其平均值設為表面粗糙度(Ra)。
(熱導率)
將底部填充膜於乾燥機內以175℃、1小時進行熱處理，使其熱硬化。其後，藉由TWA法(溫度波熱分析法，測定裝置：ai-Phase Mobile，ai-Phase(股)製造)而測定底部填充膜之熱擴散率α(m2/s)。繼而，藉由DSC(Differential Scanning Calorimetry，差示掃描熱量測定)法測定底部填充膜之比熱Cp(J/g‧℃)。比熱測定係使用SII Nano Technology(股)製造之DSC6220，於升溫速度10℃/min、溫度20~300℃之條件下進行，並基於所獲得之實驗資料，根據JIS手冊(比熱容測定方法K-7123)而算出。進而，測定底部填充膜之比重。
基於熱擴散率α、比熱Cp及比重之值，根據下述式而算出熱導率。將結果示於表1。
[數1] 熱導率(W/m．K)=熱擴散率(m2/s)×比熱(J/g．℃)×比重(g/cm3)
(填充性)
(1)切割帶一體型底部填充膜之製作
使用手壓輥將底部填充膜貼合於切割帶(商品名「V-8-T」，日東電工股份有限公司製造)之黏著劑層上，製作切割帶一體型底部填充膜。
(2)半導體裝置之製作
準備單面形成有凸塊之單面附凸塊矽晶圓，於該單面附凸塊矽晶圓之凸塊形成面將切割帶一體型底部填充膜以底部填充膜作為貼合面進行貼合。作為單面附凸塊矽晶圓，使用以下者。又，貼合條件如下所述。底部填充材料之厚度Y(=30μm)相對於連接構件之高度X(=35μm)之比(Y/X)為0.86。
‧單面附凸塊矽晶圓
矽晶圓之直徑：8英吋
矽晶圓之厚度：0.2mm(使用研削裝置「DFG-8560，DISCO股份有限公司製造」自0.7mm進行背面研削至0.2mm者)
凸塊之高度：35μm
凸塊之間距：50μm
凸塊之材質：SnAg(錫銀)焊料+銅柱
‧貼合條件
貼附裝置：商品名「DSA840-WS」，日東精機股份有限公司製造
貼附速度：5mm/min
貼附壓力：0.25MPa
貼附時之載置台溫度：80℃
貼附時之真空度：150Pa
於貼合後，利用下述條件進行矽晶圓之切割。切割係以成為7.3 mm見方之晶片尺寸之方式進行全切。
‧切割條件
切割裝置：商品名「DFD-6361」，DISCO公司製造
切割環：「2-8-1」(DISCO公司製造)
切割速度：30mm/sec
切割刀片：
Z1：DISCO公司製造之「203O-SE 27HCDD」
Z2：DISCO公司製造之「203O-SE 27HCBB」
切割刀片轉數：
Z1：40,000rpm
Z2：40,000rpm
切割方式：階梯切割
晶圓晶片尺寸：7.3mm見方
繼而，自切割帶之基材側以針之頂出方式拾取底部填充膜與單面附凸塊半導體晶片之積層體(附底部填充膜之半導體晶片)。
對底部填充膜之露出面將入射角α設為45°而利用斜光照射進行位置校準，利用下述安裝條件，於使半導體晶片之凸塊形成面與BGA(Ball Grid Array，球柵陣列)基板於連接預定位置對向的狀態下進行半導體晶片向BGA基板之安裝。藉此，獲得BGA基板上安裝有半導體晶片之半導體裝置。再者，於本安裝步驟中，進行繼安裝條件1後進行安裝條件2之兩階段處理。
‧安裝條件1
拾取裝置：商品名「FCB-3」，Panasonic製造
加熱溫度：150℃
荷重：10kg
保持時間：10秒
‧安裝條件2
拾取裝置：商品名「FCB-3」，Panasonic製造
加熱溫度：260℃
荷重：10kg
保持時間：10秒
(3)填充性之評價
對所獲得之半導體裝置實施研磨直至與晶片平行之面上顯現連接端子。利用顯微鏡觀察該平行剖面，將空隙相對於面積為5%以下者評價為○，將超過5%者評價為×。
[實施例3~4及比較例4]
根據表2所示之調配比，及將厚度設為10μm，除上述方面以外，以與實施例1相同之方法製作底部填充膜。
對於所獲得之底部填充膜，以與實施例1相同之方法，評價表面粗糙度與熱導率。又，使用凸塊之高度為12μm之單面附凸塊矽晶 圓，除該方面以外，以與實施例1相同之方法，評價填充性。將結果示於表2。
1‧‧‧黏著帶
1a‧‧‧基材
1b‧‧‧黏著劑層
2‧‧‧底部填充膜
10‧‧‧密封片

Claims (16)

  1. 一種底部填充膜，其包含樹脂及熱導性填料，且上述熱導性填料之含量為50體積%以上，上述熱導性填料之平均粒徑相對於底部填充膜之厚度為30%以下之值，上述熱導性填料之最大粒徑相對於上述底部填充膜之厚度為80%以下之值。
  2. 如請求項1之底部填充膜，其熱導率為2W/mK以上。
  3. 如請求項1之底部填充膜，其中上述熱導性填料之含量為50~80體積%，且上述熱導性填料之平均粒徑相對於上述底部填充膜之厚度為10~30%之值，上述熱導性填料之最大粒徑相對於上述底部填充膜之厚度為40~80%之值。
  4. 如請求項1之底部填充膜，其表面粗糙度(Ra)為300nm以下。
  5. 如請求項1之底部填充膜，其包含平均粒徑不同之熱導性填料作為上述熱導性填料。
  6. 如請求項1至5中任一項之底部填充膜，其全光線透過率為50%以上。
  7. 一種密封片，其具備如請求項1至6中任一項之底部填充膜及黏著帶，且上述黏著帶具有基材及設置於上述基材上之黏著劑層，上述底部填充膜設置於上述黏著劑層上。
  8. 如請求項7之密封片，其中上述底部填充膜自上述黏著劑層之剝離力為0.03~0.10N/20mm。
  9. 如請求項7之密封片，其中上述黏著帶為半導體晶圓之背面研削用帶或切割帶。
  10. 一種半導體裝置之製造方法，其係具備被接著體、與上述被接著體電性連接之半導體元件、及填充上述被接著體與上述半導體元件之間之空間之底部填充膜的半導體裝置之製造方法，且包括：準備步驟，其係準備將如請求項1至6中任一項之底部填充膜貼合於半導體元件而成的附底部填充膜之半導體元件；及連接步驟，其係以上述附底部填充膜之半導體元件之上述底部填充膜填充上述被接著體與上述半導體元件之間之空間，且將上述被接著體與上述半導體元件電性連接。
  11. 如請求項10之半導體裝置之製造方法，其包括位置校準步驟，其係對上述附底部填充膜之半導體元件之上述底部填充膜之露出面照射斜光，使上述半導體元件與上述被接著體之相對位置校準為相互之連接預定位置。
  12. 如請求項11之半導體裝置之製造方法，其中對上述底部填充膜之露出面以5~85°之入射角照射斜光。
  13. 如請求項11之半導體裝置之製造方法，其中上述斜光包含400~550nm之波長。
  14. 如請求項11之半導體裝置之製造方法，其中對上述底部填充膜之露出面自兩個以上之方向或全方向照射上述斜光。
  15. 一種半導體裝置，其係使用如請求項1至6中任一項之底部填充膜而製作。
  16. 一種半導體裝置，其係利用如請求項10至14中任一項之方法而製作。
TW103112617A 2013-04-04 2014-04-03 底部塡充膜、密封片、半導體裝置之製造方法及半導體裝置 TW201501255A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013078907A JP2014203971A (ja) 2013-04-04 2013-04-04 アンダーフィルフィルム、封止シート、半導体装置の製造方法及び半導体装置

Publications (1)

Publication Number Publication Date
TW201501255A true TW201501255A (zh) 2015-01-01

Family

ID=51658271

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103112617A TW201501255A (zh) 2013-04-04 2014-04-03 底部塡充膜、密封片、半導體裝置之製造方法及半導體裝置

Country Status (6)

Country Link
US (1) US20160035640A1 (zh)
JP (1) JP2014203971A (zh)
KR (1) KR20150138266A (zh)
CN (1) CN105122444A (zh)
TW (1) TW201501255A (zh)
WO (1) WO2014162973A1 (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150371916A1 (en) * 2014-06-23 2015-12-24 Rohm And Haas Electronic Materials Llc Pre-applied underfill
JP6557960B2 (ja) * 2014-10-31 2019-08-14 日立化成株式会社 半導体装置製造用部材、及びそれを用いた半導体装置の製造方法
JP5976073B2 (ja) * 2014-11-07 2016-08-23 日東電工株式会社 半導体装置の製造方法
KR102313698B1 (ko) * 2017-09-01 2021-10-15 매그나칩 반도체 유한회사 유연성 있는 반도체 패키지 및 이의 제조 방법
CN110699000A (zh) * 2019-10-11 2020-01-17 上海固柯胶带科技有限公司 用于半导体研磨和封装的膜材料
JP6795673B2 (ja) * 2019-12-19 2020-12-02 日東電工株式会社 電子デバイス封止用シート、及び、電子デバイスパッケージの製造方法
WO2023021891A1 (ja) * 2021-08-19 2023-02-23 三井化学株式会社 紫外線硬化性組成物
WO2024075172A1 (ja) * 2022-10-03 2024-04-11 日本電信電話株式会社 光送信器
WO2024075168A1 (ja) * 2022-10-03 2024-04-11 日本電信電話株式会社 光送信器
WO2024075171A1 (ja) * 2022-10-03 2024-04-11 日本電信電話株式会社 光送信器

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030187117A1 (en) * 2002-03-29 2003-10-02 Starkovich John A. Materials and method for improving dimensional stability of precision electronic optical photonic and spacecraft components and structures
JP4382791B2 (ja) * 2006-05-16 2009-12-16 Ｎｅｃ液晶テクノロジー株式会社 光線方向制御素子の製造方法
US20090078458A1 (en) * 2007-09-21 2009-03-26 Ricoh Company, Ltd. Paste composition, insulating film, multilayer interconnection structure, printed-circuit board, image display device, and manufacturing method of paste composition
JP5088376B2 (ja) * 2007-11-29 2012-12-05 日立化成工業株式会社 回路部材接続用接着剤及び半導体装置
WO2009099191A1 (ja) * 2008-02-07 2009-08-13 Sumitomo Bakelite Company Limited 半導体用フィルム、半導体装置の製造方法および半導体装置
JP5417729B2 (ja) * 2008-03-28 2014-02-19 住友ベークライト株式会社 半導体用フィルム、半導体装置の製造方法および半導体装置
JP5379405B2 (ja) * 2008-05-27 2013-12-25 東レエンジニアリング株式会社 超音波接合装置
JP5367656B2 (ja) * 2010-07-29 2013-12-11 日東電工株式会社 フリップチップ型半導体裏面用フィルム及びその用途
JP5831122B2 (ja) * 2010-10-18 2015-12-09 三菱化学株式会社 三次元集積回路用の層間充填材組成物、塗布液及び三次元集積回路の製造方法
JP6047422B2 (ja) * 2013-02-21 2016-12-21 富士フイルム株式会社 感光性組成物、光硬化性組成物、化学増幅型レジスト組成物、レジスト膜、パターン形成方法、及び電子デバイスの製造方法

Also Published As

Publication number Publication date
JP2014203971A (ja) 2014-10-27
CN105122444A (zh) 2015-12-02
WO2014162973A1 (ja) 2014-10-09
US20160035640A1 (en) 2016-02-04
KR20150138266A (ko) 2015-12-09

Similar Documents

Publication Publication Date Title
JP6157890B2 (ja) アンダーフィル材、封止シート及び半導体装置の製造方法
US9368421B2 (en) Under-fill material and method for producing semiconductor device
TW201501255A (zh) 底部塡充膜、密封片、半導體裝置之製造方法及半導體裝置
US20160075871A1 (en) Thermosetting resin composition and method for producing a semiconductor device
JP2014003274A (ja) 半導体装置の製造方法及びアンダーフィル材
JP2013030766A (ja) 積層フィルム及びその使用
JP2013030765A (ja) 半導体装置の製造方法
KR20130069438A (ko) 반도체 장치의 제조 방법
US20160040045A1 (en) Adhesive film for underfill, adhesive film for underfill integrated with tape for grinding rear surface, adhesive film for underfill integrated with dicing tape, and semiconductor device
KR20130059292A (ko) 반도체 장치의 제조 방법
JP5961015B2 (ja) アンダーフィル材及び半導体装置の製造方法
JP5827878B2 (ja) 半導体装置の製造方法
WO2015174184A1 (ja) 半導体装置の製造方法
JP5656741B2 (ja) ダイシング・ダイボンドフィルムの製造方法
WO2015174183A1 (ja) シート状樹脂組成物、積層シート及び半導体装置の製造方法
JP5907717B2 (ja) 半導体装置の製造方法
TW201517181A (zh) 半導體裝置之製造方法
JP5889625B2 (ja) 半導体装置の製造方法
JP2013127997A (ja) 半導体装置の製造方法
US20160233184A1 (en) Semiconductor Device Manufacturing Method
TW201512380A (zh) 底部填充材、積層片及半導體裝置之製造方法
WO2015174185A1 (ja) シート状樹脂組成物及び半導体装置の製造方法