TW201419752A - 共源共柵放大器 - Google Patents

共源共柵放大器 Download PDF

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TW201419752A
TW201419752A TW102104767A TW102104767A TW201419752A TW 201419752 A TW201419752 A TW 201419752A TW 102104767 A TW102104767 A TW 102104767A TW 102104767 A TW102104767 A TW 102104767A TW 201419752 A TW201419752 A TW 201419752A
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gate
grounding
grounded
transistors
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Katsuya Kato
Miyo Miyashita
Toshihide Oka
Kenichi Horiguchi
Kazutomi Mori
Kenji Mukai
Takanobu Fujiwara
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Mitsubishi Electric Corp
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Abstract

複數源極接地電晶體(3)互相並聯連接，複數閘極接地電晶體(4)互相並聯連接。複數閘極接地電晶體(4)的源極(4s)分別連接至複數源極接地電晶體(3)的汲極(3d)。複數接地焊墊(5)連接至複數源極接地電晶體(3)的源極(3s)。複數接地電容器(6)在複數閘極接地電晶體(4)的閘極(4g)與接地焊墊(5)之間連接。接地焊墊(5)與複數閘極接地電晶體(4)之間，交互配置複數源極接地電晶體(3)與複數接地電容器(6)。

Description

共源共柵放大器
本發明主要係關於行動電話等的移動體通訊機器中使用的共源共柵放大器。
目前，以CDMA(分碼多重存取)為首的行動電話用電力放大器中，實現低成本的一手段，使用CMOS(互補金屬氧化半導體)的共源共柵放大器的開發變得活躍起來。
第6圖係顯示共源共柵放大器的基本構成之電路圖。點線框內係共源共柵放大器，除此以外係用以構成電力放大器所必需的電路元件。電晶體Tr1、Tr2係n通道MOS電晶體，共源共柵連接。使用共源共柵連接的電晶體之放大器稱作共源共柵放大器。
電晶體Tr1的閘極經由輸入整合電路連接至RF(射頻)輸入信號端子IN，且連接至閘極偏壓端子Vg1。電晶體Tr1的源極接地。即，電晶體Tr1係源極接地電晶體。
電晶體Tr2的閘極經由電容器C1接地，且連接至閘極偏壓端子Vg2。即，電晶體Tr2係閘極接地電晶體。電晶體Tr2的源極連接至電晶體Tr1的汲極。電晶體Tr2的汲極經由線路L1連接至共源共柵放大器的汲極電源端子Vd，且經由輸出整合電路，連接至RF(射頻)輸出信號端子OUT。線路L1 係具有特定的電長度，作用為電感器。
習知的共源共柵放大器中，一直使用增益與效率優異的GaAs(砷化鎵)等的化合物半導體。近年來，行動體通訊的領域中，為了對應通訊量的增加等，對應複數調變方式與複數頻帶之多模多頻帶技術受到重視。又，行動體終端中，實現多模多頻帶技術小型、低成本很重要。因此，針對行動體終端，使用在積體化與成本方面優異的矽元件之共源共柵放大器受到注目。
使用化合物半導體的共源共柵放大器中，源極接地電晶體的源極利用介層洞接地(例如，參照非專利文件1)。由於介層洞的電感小，元件的特性惡化小，還有介層洞的配置中，由於沒有大的限制，可以自由佈局。不過，矽元件的情況下，由於一般不能使用介層洞，矽基板上設置接地焊墊，經由金屬線連接至外部的接地。
[先行技術文件] [非專利文件]
[非專利文件1]高木、高山、石川、本城著，2011電子資訊通訊學會電子學會大會、電子學演講論文集，C-2-22
為了源極接地電晶體的源極最好充分接地，連接至源極的接地焊墊接近矽基板的邊緣配置，縮小金屬線電感。又，最好增加接地焊墊的數量，縮小電感。不過，接地焊墊的增加產生尺寸的擴大。
又，接地焊墊多，電晶體尺寸大時，閘極接地電晶體的閘極到接地電容器的距離根據閘極電晶體的位置而變得不均一。因此，根據閘極到接地電容器的配線的電阻與電感成分，具有產生不平衡動作的問題。
又，從閘極接地電晶體到接地電容器為止的配線的寄生電阻大時，閘極的高頻接地變得不充分，有共源共柵放大器的增益、輸出、效率產生惡化之問題。
由於本發明係用以解決上述的課題而形成，其目的係得到縮小晶片尺寸，防止不平衡動作，可以提高增益、輸出、效率的共源共柵放大器。
根據本發明的共源共柵放大器，包括複數源極接地電晶體，互相並聯連接；複數閘極接地電晶體，互相並聯連接，具有分別連接至上述複數源極接地電晶體的汲極之源極；接地焊墊，連接至上述複數源極接地電晶體的源極；以及複數接地電容器，在上述複數閘極接地電晶體的閘極與上述接地焊墊之間分別連接；上述接地焊墊與上述複數閘極接地電晶體之間，交互配置上述複數源極接地電晶體與上述複數接地電容器。
根據本發明，縮小晶片尺寸、防止不平衡動作，可以提高增益、輸出、效率。
1‧‧‧矽基板(半導體基板)
2‧‧‧共源共柵放大器
3‧‧‧源極接地電晶體
3d‧‧‧汲極
3g‧‧‧閘極
3s‧‧‧源極
4‧‧‧閘極接地電晶體
4d‧‧‧汲極
4g‧‧‧閘極
4s‧‧‧源極
5‧‧‧接地焊墊
6‧‧‧接地電容器
7‧‧‧接地焊墊
8‧‧‧配線
C1‧‧‧電容器
IN‧‧‧輸入信號端子
L1‧‧‧線路
OUT‧‧‧輸出信號端子
Tr1、Tr2‧‧‧電晶體
Vd‧‧‧汲極電源端子
Vg1‧‧‧閘極偏壓端子
Vg2‧‧‧閘極偏壓端子
[第1圖]係顯示根據本發明第一實施例的共源共柵放大器的上面圖；[第2圖]係顯示第1圖的放大上面圖；[第3圖]係顯示根據比較例的共源共柵放大器的放大上面圖；[第4圖]係顯示根據本發明第二實施例的共源共柵放大器的放大上面圖；[第5圖]係顯示根據本發明第三實施例的共源共柵放大器的放大上面圖；以及[第6圖]係顯示共源共柵放大器的基本構成之電路圖。
參照圖面，說明有關本發明的實施例的共源共柵放大器。相同或對應的構成要素係附與相同的符號，會省略重複的說明。
[第一實施例]
第1圖係顯示根據本發明第一實施例的共源共柵放大器的上面圖。第2圖係顯示第1圖的放大上面圖。矽基板1的主面上的一部分區域中設置共源共柵放大器2。
複數源極接地電晶體3互相並聯連接，複數閘極接地電晶體4互相並聯連接。源極接地電晶體3具有閘極3g、源極3s、汲極3d，閘極接地電晶體4具有閘極4g、源極4s、汲極4d。源極接地電晶體3的閘極3g係輸入端子IN，閘極接地電晶體4的汲極4d係輸出端子OUT。
複數閘極接地電晶體4的源極4s分別連接至複數 源極接地電晶體3的汲極3d。即，閘極接地電晶體4與源極接地電晶體3係共源共柵連接。複數接地焊墊5連接至複數源極接地電晶體3的源極3s。
複數接地電容器6在複數閘極接地電晶體4的閘極4g與接地焊墊5之間連接。接地焊墊5與複數閘極接地電晶體4之間，交互配置複數源極接地電晶體3與複數接地電容器6。
接著，比較比較例，說明本實施例的效果。第3圖係顯示根據比較例的共源共柵放大器的放大上面圖。比較例中，分別設置連接至源極接地電晶體3的源極之接地焊墊5與連接至接地電容器6之接地焊墊7。結果，接地焊墊數量增加，產生晶片尺寸的擴大。另一方面，本實施例中，由於共用連接至接地電容器6之接地焊墊與連接至源極接地電晶體3的源極之接地焊墊，可以縮小晶片尺寸。
又，本實施例中，接地焊墊5與複數閘極接地電晶體4之間，交互配置複數源極接地電晶體3與複數接地電容器6。因此，由於可以降低從閘極接地電晶體4到接地電容器6為止的距離不均，可以防止不平衡動作。於是，由於從閘極接地電晶體4的閘極4g到接地電容器6為止的距離變短，配線電阻變短，閘極接地電晶體4的閘極4g的高頻接地變得充分，可以提高共源共柵放大器的增益、輸出、效率。
又，矽基板1上，從矽基板1的邊緣往內側依序配置接地焊墊5、複數源極接地電晶體3、複數閘極接地電晶體4。因此，連接接地焊墊5與外部接地的金屬線長度可以縮 短。又，可以降低起因於從源極接地電晶體3的源極3s到接地焊墊5為止的配線之電感。結果，可以得到高增益。
又，源極接地電晶體3與閘極接地電晶體4係NMOS型電晶體、PMOS型電晶體、SiGe-HBT(鍺化矽-異質接面雙極電晶體)等。又，接地電容器6可以是MIM(金屬-絕緣-金屬)電容器也可以是MOS(金屬氧化半導體)。不限制源極接地電晶體3與閘極接地電晶體4的單位閘極寬度，為了可以交互配置源極接地電晶體3與接地電容器6，設定單位閘極寬度。
[第二實施例]
第4圖係顯示根據本發明第二實施例的共源共柵放大器的放大上面圖。與第一實施例相同，共用連接至接地電容器6之接地焊墊與連接至源極接地電晶體3的源極3s之接地焊墊。於是，不同於第一實施例，接地電容器6配置在接地焊墊5的下方。因此，可以比第一實施例更縮小晶片尺寸。
又，接地電容器6以複數配線8連接至複數閘極接地電晶體4的閘極4g。因此，由於可以降低從閘極接地電晶體4到接地電容器6為止的距離不均，可以防止不平衡動作。於是，由於可以從閘極接地電晶體4的閘極4g到接地電容器6為止的距離變短，配線電阻變小，閘極接地電晶體4的閘極4g的高頻接地變得充分，可以提高共源共柵放大器的增益、輸出、效率。
又，接地電容器6可以是MIM(金屬-絕緣-金屬電容器)也可以是MOS(金屬氧化半導體)，但MIM電容器的情況下，可以與閘極接地電晶體4的閘極4g共用其下電極，與接 地焊墊5共用上電極。
[第三實施例]
第5圖係顯示根據本發明第三實施例的共源共柵放大器的放大上面圖。不同於第一實施例，接地電容器6配置於複數源極接地電晶體3與複數閘極接地電晶體4之間。因此，由於可以降低從閘極接地電晶體4到電容器6為止的距離不均，可以防止不平衡動作。於是，由於從閘極接地電晶體4的閘極4g到接地電容器6為止的距離變短，配線電阻變小，閘極接地電晶體4的閘極4g的高頻接地變得充分，可以提高共源共柵放大器的增益、輸出、效率。
又，與第一實施例相同，由於共用連接至接地電容器6之接地焊墊與連接至源極接地電晶體3的源極3s之接地焊墊，可以縮小晶片尺寸。
又，接地電容器6可以是MIM(金屬-絕緣-金屬電容器)也可以是MOS(金屬氧化半導體)，但MIM電容器的情況下，可以與閘極接地電晶體4的閘極4g共用其上電極或下電極。
1‧‧‧矽基板(半導體基板)
3‧‧‧源極接地電晶體
3d‧‧‧汲極
3g‧‧‧閘極
3s‧‧‧源極
4‧‧‧閘極接地電晶體
4d‧‧‧汲極
4g‧‧‧閘極
4s‧‧‧源極
5‧‧‧接地焊墊
6‧‧‧接地電容器
7‧‧‧接地焊墊
IN‧‧‧輸入信號端子
OUT‧‧‧輸出信號端子

Claims (4)

  1. 一種共源共柵放大器，包括：複數源極接地電晶體，互相並聯連接；複數閘極接地電晶體，互相並聯連接，具有分別連接至上述複數源極接地電晶體的汲極之源極；接地焊墊，連接至上述複數源極接地電晶體的源極；以及複數接地電容器，在上述複數閘極接地電晶體的閘極與上述接地焊墊之間分別連接；其特徵在於：上述接地焊墊與上述複數閘極接地電晶體之間，交互配置上述複數源極接地電晶體與上述複數接地電容器。
  2. 一種共源共柵放大器，包括：複數源極接地電晶體，互相並聯連接；複數閘極接地電晶體，互相並聯連接，具有分別連接至上述複數源極接地電晶體的汲極之源極；接地焊墊，連接至上述複數源極接地電晶體的源極；以及接地電容器，在上述複數閘極接地電晶體的閘極與上述接地焊墊之間連接；其特徵在於：上述接地電容器配置於上述接地焊墊下方，以複數配線連接至上述複數閘極接地電晶體的閘極。
  3. 一種共源共柵放大器，包括：複數源極接地電晶體，互相並聯連接；複數閘極接地電晶體，互相並聯連接，具有分別連接至上 述複數源極接地電晶體的汲極之源極；接地焊墊，連接至上述複數源極接地電晶體的源極；接地電容器，在上述複數閘極接地電晶體的閘極與上述接地焊墊之間連接；以及半導體基板；其特徵在於：上述接地電容器配置於上述複數源極接地電晶體與上述複數閘極接地電晶體之間；以及上述半導體基板上，從上述半導體基板的邊緣往內側依序配置上述接地焊墊、上述複數源極接地電晶體、上述複數閘極接地電晶體。
  4. 如申請專利範圍第1或2項所述的共源共柵放大器，更包括：半導體基板；其特徵在於：上述半導體基板上，從上述半導體基板的邊緣往內側依序配置上述接地焊墊、上述複數源極接地電晶體、上述複數閘極接地電晶體。
TW102104767A 2012-11-09 2013-02-07 共源共柵放大器 TW201419752A (zh)

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