CN104769840A - 共源共栅放大器 - Google Patents

共源共栅放大器 Download PDF

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CN104769840A
CN104769840A CN201280076909.4A CN201280076909A CN104769840A CN 104769840 A CN104769840 A CN 104769840A CN 201280076909 A CN201280076909 A CN 201280076909A CN 104769840 A CN104769840 A CN 104769840A
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ground
grid
transistor
source
common
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嘉藤胜也
宫下美代
冈俊英
堀口健一
森一富
向井谦治
藤原孝信
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Mitsubishi Electric Corp
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Abstract

多个源极接地晶体管(3)相互并联连接，多个栅极接地晶体管(4)相互并联连接。多个栅极接地晶体管(4)的源极(4s)分别与多个源极接地晶体管(3)的漏极(3d)连接。多个接地焊盘(5)与多个源极接地晶体管(3)的源极(3s)连接。多个接地电容(6)连接在多个栅极接地晶体管(4)的栅极(4g)和接地焊盘(5)之间。在接地焊盘(5)与多个栅极接地晶体管(4)之间交替配置有多个源极接地晶体管(3)和多个接地电容(6)。

Description

共源共栅放大器
技术领域
本发明主要涉及在移动电话等移动通信设备中使用的共源共栅(cascode)放大器。
背景技术
当前，作为在以CDMA为代表的移动电话用功率放大器中实现低成本化的1个手段，人们正在积极开发使用了CMOS工艺的共源共栅放大器。
图6是示出共源共栅放大器的基本结构的电路图。虚线框内是共源共栅放大器，除此以外是构成功率放大器所需的电路元件。晶体管Tr1、Tr2是n沟道MOS晶体管，进行了共源共栅连接。将使用了进行共源共栅连接的晶体管的放大器称作共源共栅放大器。
晶体管Tr1的栅极经由输入匹配电路与RF输入信号端子IN连接，且与栅极偏置端子Vg1连接。晶体管Tr1的源极接地。即，晶体管Tr1是源极接地晶体管。
晶体管Tr2的栅极经由电容C1接地，且与栅极偏置端子Vg2连接。即，晶体管Tr2是栅极接地晶体管。晶体管Tr2的源极与晶体管Tr1的漏极连接。晶体管Tr2的漏极经由线路L1与共源共栅放大器的漏极电源端子Vd连接，且经由输出匹配电路与RF输出信号端子OUT连接。线路L1具有特定的电气长度，作为电感器发挥作用。
在以往的共源共栅放大器中，采用了增益和效率优异的GaAs等的化合物半导体。近年来，在移动通信的领域中，为了应对通信量的增加等，与多个调制方式以及多个频带对应的多模式多频段技术受到了重视。并且，在移动终端中，重要的是小型且低成本地实现多模式多频段技术。因此，面向移动终端，正在关注使用了在集成化和成本方面优异的硅器件的共源共栅放大器。
在使用了化合物半导体的共源共栅放大器中，源极接地晶体管的源极使用过孔而接地(例如参照非专利文献1)。由于过孔的电感小，因此，器件的特性劣化较少，并且对过孔的配置没有大的制约，因此能够进行自由布局。但是，在硅器件的情况下，通常无法使用过孔，因此，要在硅基板上设置接地焊盘，借助线与外部的地连接。
现有技术文献
非专利文献
非专利文献1：高木、高山、石川、本城著、2011電子情報通信学会エレクトロニクスソサイエティ大会、エレクトロニクス講演論文集、C－2－22
发明内容
发明要解决的课题
由于优选源极接地晶体管的源极被充分接地，因此，将与源极连接的接地焊盘配置在硅基板的边缘附近来减小线电感。并且，优选增加接地焊盘的数量来减小合成电感。但是，接地焊盘的增加会导致芯片尺寸的扩大。
此外，在接地焊盘多、且晶体管尺寸大的情况下，从栅极接地晶体管的栅极到接地电容的距离根据栅极晶体管的位置而变得不均匀。因此，存在以下问题：由于从栅极到接地电容的布线的电阻和电感成分而产生不平衡动作。
并且，在从栅极接地晶体管到接地电容的布线的寄生电阻大的情况下，栅极的高频接地变得不充分，从而存在以下问题：产生共源共栅放大器的增益、输出、效率的劣化。
本发明是为了解决上述那样的课题而完成的，其目的在于得到能够缩小芯片尺寸、防止不平衡动作、提高增益、输出、效率的共源共栅放大器。
用于解决课题的手段
本发明的共源共栅放大器的特征在于，具有：相互并联连接的多个源极接地晶体管；多个栅极接地晶体管，它们相互并联连接，具有分别与所述多个源极接地晶体管的漏极连接的源极；与所述多个源极接地晶体管的源极连接的接地焊盘；以及多个接地电容，它们分别连接在所述多个栅极接地晶体管的栅极和所述接地焊盘之间，在所述接地焊盘与所述多个栅极接地晶体管之间，交替配置有所述多个源极接地晶体管和所述多个接地电容。
发明的效果
通过本发明，能够缩小芯片尺寸，防止不平衡动作，提高增益、输出、效率。
附图说明
图1是示出本发明实施方式1的共源共栅放大器的俯视图。
图2是放大图1的一部分后的俯视图。
图3是示出比较例的共源共栅放大器的放大俯视图。
图4是示出本发明实施方式2的共源共栅放大器的放大俯视图。
图5是示出本发明实施方式3的共源共栅放大器的放大俯视图。
图6是示出共源共栅放大器的基本结构的电路图。
具体实施方式
参照附图对本发明实施方式的共源共栅放大器进行说明。有时对相同或对应的结构要素标注相同标号，省略重复说明。
实施方式1.
图1是示出本发明实施方式1的共源共栅放大器的俯视图。图2是放大图1的一部分后的俯视图。在硅基板1的主面上的部分区域中设置有共源共栅放大器2。
多个源极接地晶体管3相互并联连接，多个栅极接地晶体管4相互并联连接。源极接地晶体管3具有栅极3g、源极3s、漏极3d，栅极接地晶体管4具有栅极4g、源极4s、漏极4d。源极接地晶体管3的栅极3g是输入端子IN，栅极接地晶体管4的漏极4d是输出端子OUT。
多个栅极接地晶体管4的源极4s分别与多个源极接地晶体管3的漏极3d连接。即，栅极接地晶体管4和源极接地晶体管3进行共源共栅连接。多个接地焊盘5与多个源极接地晶体管3的源极3s连接。
多个接地电容6连接在多个栅极接地晶体管4的栅极4g和接地焊盘5之间。在接地焊盘5与多个栅极接地晶体管4之间，交替配置有多个源极接地晶体管3和多个接地电容6。
接着，与比较例进行比较来说明本实施方式的效果。图3是示出比较例的共源共栅放大器的放大俯视图。在比较例中，分别设置有与源极接地晶体管3的源极连接的接地焊盘5以及与接地电容6连接的接地焊盘7。其结果，接地焊盘的数量增加，从而导致芯片尺寸的扩大。另一方面，在本实施方式中，共用了与接地电容6连接的接地焊盘以及与源极接地晶体管3的源极连接的接地焊盘，因此能够缩小芯片尺寸。
此外，在本实施方式中，在接地焊盘5与多个栅极接地晶体管4之间，交替配置有多个源极接地晶体管3和多个接地电容6。由此，能够减少从栅极接地晶体管4到接地电容6的距离的偏差，因此能够防止不平衡动作。并且，从栅极接地晶体管4的栅极4g到接地电容6的距离缩短，因此布线电阻减小，栅极接地晶体管4的栅极4g的高频接地变得充分，能够提高共源共栅放大器的增益、输出、效率。
此外，在硅基板1上，从硅基板1的边缘朝内侧依次配置有接地焊盘5、多个源极接地晶体管3、多个栅极接地晶体管4。由此，能够缩短对接地焊盘5和外部的地进行连接的线的长度。并且，能够减小由于从源极接地晶体管3的源极3s到接地焊盘5的布线而引起的电感。其结果，能够得到高增益。
另外，源极接地晶体管3和栅极接地晶体管4是NMOS型晶体管、PMOS型晶体管、SiGe－HBT等。此外，接地电容6可以是MIM(Metal-Insulation-Metal：金属绝缘金属)电容，也可以是MOS(Metal Oxide Semiconductor：金属氧化物半导体)。源极接地晶体管3和栅极接地晶体管4的单位栅极宽度没有限制，以能够交替配置源极接地晶体管3和接地电容6的方式设定单位栅极宽度。
实施方式2.
图4是示出本发明实施方式2的共源共栅放大器的放大俯视图。与实施方式1同样，共用了与接地电容6连接的接地焊盘以及与源极接地晶体管3的源极3s连接的接地焊盘。并且，与实施方式1不同，接地电容6被配置在接地焊盘5的下方。由此，相比于实施方式1，能够进一步缩小芯片尺寸。
此外，接地电容6利用多个布线8与多个栅极接地晶体管4的栅极4g连接。由此，能够减少从栅极接地晶体管4到接地电容6的距离的偏差，因此能够防止不平衡动作。并且，从栅极接地晶体管4的栅极4g到接地电容6的距离缩短，因此布线电阻减小，栅极接地晶体管4的栅极4g的高频接地变得充分，能够提高共源共栅放大器的增益、输出、效率。
另外，接地电容6可以是MIM电容，也可以是MOS，在MIM电容的情况下，能够与栅极接地晶体管4的栅极4g共用其底层电极，能够与接地焊盘5共用上层电极。
实施方式3.
图5是示出本发明实施方式3的共源共栅放大器的放大俯视图。与实施方式1不同，接地电容6被配置在多个源极接地晶体管3与多个栅极接地晶体管4之间。由此，能够减少从栅极接地晶体管4到接地电容6的距离的偏差，因此能够防止不平衡动作。并且，从栅极接地晶体管4的栅极4g到接地电容6的距离缩短，因此布线电阻减小，栅极接地晶体管4的栅极4g的高频接地变得充分，能够提高共源共栅放大器的增益、输出、效率。
此外，与实施方式1同样，共用了与接地电容6连接的接地焊盘以及与源极接地晶体管3的源极3s连接的接地焊盘，因此，能够缩小芯片尺寸。
另外，接地电容6可以是MIM电容，也可以是MOS，在MIM电容的情况下，能够与栅极接地晶体管4的栅极4g共用其上层电极或底层电极。
标号说明
1：硅基板(半导体基板)；2：共源共栅放大器；3：源极接地晶体管；4：栅极接地晶体管；5：接地焊盘；6：接地电容。

Claims (4)

1.一种共源共栅放大器，其特征在于，其具有：
相互并联连接的多个源极接地晶体管；
多个栅极接地晶体管，它们相互并联连接，具有分别与所述多个源极接地晶体管的漏极连接的源极；
与所述多个源极接地晶体管的源极连接的接地焊盘；以及
多个接地电容，它们分别连接在所述多个栅极接地晶体管的栅极和所述接地焊盘之间，
在所述接地焊盘与所述多个栅极接地晶体管之间，交替配置有所述多个源极接地晶体管和所述多个接地电容。
2.一种共源共栅放大器，其特征在于，其具有：
相互并联连接的多个源极接地晶体管；
多个栅极接地晶体管，它们相互并联连接，具有分别与所述多个源极接地晶体管的漏极连接的源极；
与所述多个源极接地晶体管的源极连接的接地焊盘；以及
接地电容，其连接在所述多个栅极接地晶体管的栅极和所述接地焊盘之间，
所述接地电容被配置在所述接地焊盘的下方，通过多个布线与所述多个栅极接地晶体管的栅极连接。
3.一种共源共栅放大器，其特征在于，其具有：
相互并联连接的多个源极接地晶体管；
多个栅极接地晶体管，它们相互并联连接，具有分别与所述多个源极接地晶体管的漏极连接的源极；
与所述多个源极接地晶体管的源极连接的接地焊盘；以及
接地电容，其连接在所述多个栅极接地晶体管的栅极和所述接地焊盘之间，
所述接地电容被配置在所述多个源极接地晶体管与所述多个栅极接地晶体管之间。
4.根据权利要求1～3中的任意一项所述的共源共栅放大器，其特征在于，
所述共源共栅放大器还具有半导体基板，
在所述半导体基板上，从所述半导体基板的边缘朝内侧依次配置有所述接地焊盘、所述多个源极接地晶体管和所述多个栅极接地晶体管。
CN201280076909.4A 2012-11-09 2012-11-09 共源共栅放大器 Pending CN104769840A (zh)

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TW201419752A (zh) 2014-05-16

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