TW201417237A - 立體堆疊式封裝結構及其製作方法 - Google Patents
立體堆疊式封裝結構及其製作方法 Download PDFInfo
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Abstract
一種立體堆疊式封裝結構,其包括:第一單元、模封單元、導電單元及第二單元。第一單元包括一第一基板及至少一第一電子元件,且第一基板具有至少一通道及至少一第一導電焊墊。模封單元具有一頂部覆蓋第一電子元件、一框體設置在第一基板的下表面、及至少一連接體設置於通道內且連接於頂部與框體之間。導電單元包括至少一導電體貫穿框體且電性連接於第一導電焊墊。藉此,第一單元可通過框體以堆疊在第二單元上,且第一單元可通過導電體以電性連接於第二單元。
Description
本發明係有關於一種封裝結構及其製作方法,尤指一種立體堆疊式封裝結構及其製作方法。
由於積體電路(Integrated Circuit,IC)的製程技術發展迅速,使得晶片內部電路的積集度(integration)愈來愈高,且導線面積愈來愈小。隨著晶片的銲墊與金屬導線的面積縮小,晶片封裝技術也需要不斷改良以適用於更加微小化的晶片。例如球柵陣列式(BGA)、覆晶式(Flip Chip)、晶片尺寸封裝(Chip Size Package,CSP)、以及晶圓級晶片尺寸封裝(Wafer Level Chip Scale Package,WLCSP)等半導體封裝技術,已經成為主流。系統級封裝(System In a Package,SIP)則是提供可以整合多種功能晶片的封裝技術,例如用來整合邏輯電路的記憶元件。
堆疊式封裝技術(或稱為3維封裝技術)是將晶片堆疊起來,或是具有多個晶片、電子元件的多個基板進行堆疊,然後再電性連接各層的晶片或基板。這樣的封裝方式可將晶片密度大幅提昇,目前已經成為封裝的重要技術。
本發明其中一實施例,在於提供一種立體堆疊式封裝結構,其包括:第一單元、模封單元、導電單元及第二單元。第一單元包括第一基板及至少一第一電子元件,且第一基板具有至少一通道及至少一第一導電焊墊。模封單元具有頂部、框體、及至少一連接體連接於頂部與框體之間。導電單元包括至少一導電體貫穿框體且電性連接於第一
導電焊墊。因此,本發明實施例所提供的立體堆疊式封裝結構可透過“模封單元”及“導電單元”的設計,以使得第一單元可通過模封單元的框體以堆疊在第二單元上,並且第一單元可通過導電單元的導電體以電性連接於第二單元。
本發明另外一實施例,在於提供一種立體堆疊式封裝結構的製作方法,其包括下列步驟:首先,將至少一第一單元放置在一模具結構內,第一單元包括一第一基板及至少一第一電子元件,且第一基板具有至少一第一導電焊墊及至少一通道;接著,將模封材料填充於模具結構內,以形成一模封單元,其中模封單元具有頂部、框體、及至少一連接體連接於頂部與框體之間;然後,移除模具結構;接下來,形成至少一開口貫穿框體;然後,將導電體填充於開口內;最後,通過框體以將第一單元堆疊在一第二單元上,其中第一單元通過導電體以電性連接於第二單元。因此,本發明實施例所提供的立體堆疊式封裝結構可透過“形成模封單元”及“形成至少一導電體”的設計,以使得第一單元可通過模封單元的框體以堆疊在第二單元上,並且第一單元可通過導電體以電性連接於第二單元。再者,由於本發明可以在封裝第一電子元件的封裝步驟中,順便將用於連接第一單元與第二單元的框體製作出來,所以本發明可以不用另外製作框體而有效降低整體的製作成本。
為使能更進一步瞭解本發明之特徵及技術內容,請參閱以下有關本發明之詳細說明與附圖,然而所附圖式僅提供參考與說明用,並非用來對本發明加以限制者。
請參閱圖1至圖4所示,關於本發明的立體堆疊式封
裝結構Z的製作程序,大致如下所述,但其並非用來限定本發明:
首先,配合圖1所示,提供電路基板模組1’,其包括多個依序相連的第一單元1,其中圖1顯示每兩個第一單元1之間可由1條假想線來作為區隔。再者,每一個第一單元1包括第一基板10及至少一第一電子元件11設置且電性連接於第一基板10。本發明實施例以多個第一電子元件11為例子來作說明。另外,第一基板10的周邊100具有至少一通道101貫穿第一基板10,且第一基板10具有至少一第一導電焊墊102設置於第一基板10的下表面且鄰近第一基板10的周邊100。本發明實施例以多個通道101與多個第一導電焊墊102為例子來作說明。更進一步來說,第一基板10具有兩個對向設置的第一側邊100A及兩個對向設置的第二側邊100B。此外,每一個通道101設置在兩個相鄰近的第一側邊100A與第二側邊100B的交界處,且多個第一導電焊墊102可以沿著兩個第一側邊100A與兩個第二側邊100B排列成圍繞狀。另外,值得注意的是,本發明也可以增設通道101位於每兩個相鄰的第一導電焊墊102之間,第一基板10的四個轉角處具有4個較大尺寸的通道101,且相鄰第一基板10的兩個通道101彼此可以相通。
接著,配合圖2所示,將電路基板模組1’放置在上模具M1與下模具M2之間,並將模封材料2’填充於上模具M1與下模具M2之間,以形成多個模封單元2依序相連且分別對應於多個第一單元1,其中圖2顯示每兩個模封單元2之間可由1條X-X切割線來作為區隔。其中,上模具
M1與下模具M2可組成模具結構M,上模具M1包括上殼體M10、至少一貫穿上殼體M10的輸入孔M11、及容置空間M12位於在上殼體M10內,且模封材料2’可從輸入孔M11流入上模具M1與下模具M2之間。下模具M2包括下殼體M20、多個排氣通道M21貫穿下殼體M20、及多個圍繞通道M23位於大約對應第一基板周邊100的位置,其中多個圍繞通道M23可以彼此相通,且每個通道101可連通於容置空間M12與圍繞通道M23之間。當模封材料2’從輸入孔M11流入上模具M1與下模具M2之間時,下模具M2的排氣通道M21可以用來排除多餘的氣泡,以使得模封材料2’可以更緊密地填滿於上模具M1與下模具M2之間。值得一提的是,下模具M2可進一步包括多個凸塊M22位於下殼體M20與電路基板模組1’之間且分別接觸對應的第一基板10,並且為圍繞通道M23所環繞,其目的在於與另一基板堆疊時,提供空間容置另一基板上的電子元件。在實際應用上也可以不使用此凸塊M22,而改用雷射(laser scribing)方式去除此空間中的模封材料2’。
然後,配合圖2、圖3A及圖3B(其中圖3B為圖3A的底視示意圖)所示。移除上模具M1與下模具M2後,沿著圖2的X-X切割線切割電路基板模組1’與模封材料2’,以使得多個第一單元1彼此分離且使得多個模封單元2彼此分離,其中每一個模封單元2具有頂部20A、框體20B及多個連接體20C,其中頂部20A覆蓋多個第一電子元件11,框體20B形成於第一基板10的下表面且大致對應於周邊100,多個連接體20C分別形成於多個通道101內且同時連接於頂部20A與框體20B之間。更進一步來說,由
於頂部20A、框體20B及連接體20C三者可經由一體成型的方式來製作,所以頂部20A、框體20B及連接體20C三者可結合成單一構件。另外,由於本發明可以在第一電子元件11的封裝步驟中,順便將框體20B製作出來,所以本發明的製作流程與成本可以被有效降低。
接下來,在框體20B對應於第一導電焊墊102的位置形成開口200B,以曝露第一導電焊墊102。例如由雷射鑽孔(laser drill)的方式來形成開口200B。
緊接著,以導電體30分別填滿多個開口200B,其中多個導電體30分別電性連接於第一單元1的多個第一導電焊墊102。
最後,配合圖4所示,將第一單元1堆疊在第二單元4的上表面,其中第一單元1通過第一導電焊墊102與導電體30以電性連接於第二單元4。其中,第二單元4包括第二基板40、多個第二導電焊墊402設置於周邊400、及至少一個第二電子元件41,且第二電子元件41被框體20B所圍繞。如此,每一個第二導電焊墊402可通過相對應的導電體30以電性連接於相對應的第一導電焊墊102。關於上述第一單元1與第二單元4的連接方法,例如:先將多個焊錫S分別印刷在多個第二導電焊墊402上,然後再透過框體20B以將第一單元1堆疊在第二單元4的上表面,以使得多個導電體30分別接觸多個焊錫S,最後再進行迴銲(Reflow)。因此,每一個導電體30可通過焊錫S電性接觸每一個相對應的第二導電焊墊402,由於第一、二導電焊墊102、402分別經由第一、二基板10、40的電路走線連接至基板上方的電子元件(圖未示),所以第一電子元
件11可通過導電體30電性連接至相對應的第二電子元件41。
請參閱圖4所示,經由上述本發明所提供的製作程序,本發明的第一實施例可提供一種立體堆疊式封裝結構Z,其包括:第一單元1、模封單元2、導電單元3及第二單元4。
首先,第一單元1包括第一基板10及多個第一電子元件11設置於第一基板10的上表面且電性連接於第一基板10,其中第一基板10的周邊100上具有多個通道101貫穿第一基板10,且第一基板10具有多個第一導電焊墊102設置於第一基板10的下表面且鄰近第一基板10的周邊100。舉例來說,第一電子元件11可為電阻、電容、電感、具有一預定功能的功能晶片、具有一預定功能的半導體晶片等等。
再者,模封單元2具有頂部20A設置在第一基板10的上表面且覆蓋多個第一電子元件11的、框體20B設置在第一基板10的下表面且鄰近第一基板10的周邊100、及多個連接體20C分別設置於多個通道101內且同時連接於頂部20A與框體20B之間。頂部20A、框體20B及連接體20C三者可結合成單一構件。
另外,導電單元3包括多個導電體30貫穿框體20B且分別電性連接於多個第一導電焊墊102。第一單元1可通過模封單元2的框體20B以堆疊在第二單元4上,且第一單元1可通過導電單元3的多個導電體30以電性連接於第二單元4。第二單元4包括第二基板40及多個第二電
子元件41設置於第二基板40的上表面且電性連接於第二基板40。其中,第二基板40具有多個第二導電焊墊402設置於第二基板40的上表面且鄰近第二基板40的周邊400,多個第二導電焊墊402可分別通過多個焊錫S以分別電性連接於多個導電體30,且多個第二電子元件41可被框體20B所圍繞。
請參閱圖5所示,本發明第二實施例可提供一種立體堆疊式封裝結構Z,其包括:第一單元1、模封單元2、導電單元3及第二單元4。由圖5與圖4的比較可知,本發明第二實施例與第一實施例最大的差別在於:在第二實施例中,第一單元1包括至少一第三電子元件12設置於第一基板10的下表面且電性連接於第一基板10,且第三電子元件12被框體20B所圍繞。換言之,由於第二實施例可另外增加設置於第一基板10的下表面的第三電子元件12,所以本發明可以在第一基板10所能夠提供的有限空間內設置更多的電子元件。
請參閱圖6A及圖6B所示,本發明第三實施例提供一種立體堆疊式封裝結構Z,其包括:第一單元1、模封單元2、導電單元3及第二單元4。由圖6A與圖2的比較、及圖6B與圖4的比較可知,本發明第三實施例與第一實施例最大的差別在於:在第三實施例中,第一單元1包括至少一第三電子元件12設置於第一基板10的下表面且電性連接於第一基板10,且下模具M2包括多個流道M24及多個圍繞通道M23位於下殼體M20與電路基板模組1’
之間,每一個流道M24形成於相對應的凸塊M22與相對應的第一基板10之間,且多個流道M24與多個圍繞通道M23彼此相通。因此,通過第三實施例的流道M24設計,模封單元2具有底部封裝體20D,其設置在第一基板10的下表面且覆蓋第三電子元件12,且底部封裝體20D連接於框體20B且被框體20B所圍繞。由於頂部20A、框體20B、連接體20C及底部封裝體20D四者可經由一體成型的方式來製作,所以頂部20A、框體20B、連接體20C及底部封裝體20D四者可結合成單一構件。
請參閱圖7所示,本發明提供一種立體堆疊式封裝結構Z的製作方法,其包括下列步驟:(以下舉至少一第一單元為例子來作說明)
步驟S100:首先,將至少一第一單元1放置在模具結構M內,其中第一單元1包括第一基板10及至少一第一電子元件11設置在第一基板10的上表面上,且第一基板10具有至少一第一導電焊墊102及至少一通道101。
步驟S102:接著,將模封材料2’填充於模具結構M內,以形成模封單元2,其中模封單元2具有一頂部20A、一框體20B及至少一連接體20C,頂部20A覆蓋第一電子元件11、框體20B設置在第一基板10的下表面上,連接體20C設置於通道101內且連接於頂部20A與框體20B之間。
步驟S104:然後,移除模具結構M。
步驟S106:接下來,形成至少一開口200B貫穿框體20B,開口200B裸露出第一導電焊墊102。
步驟S108:緊接著,將導電體30填充於開口200B內,以使導電體30電性連接於第一導電焊墊102。
步驟S110:最後,通過框體20B以將第一單元1堆疊在第二單元4上,其中第一單元1通過多個導電體30以電性連接於第二單元4。
綜上所述,由於本發明可以在第一電子元件11(或第一電子元件11與第三電子元件12)的封裝步驟中,順便將框體20B製作出來,所以本發明可以有效降低製作成本。
以上所述僅為本發明之較佳可行實施例,非因此侷限本發明之專利範圍,故舉凡運用本發明說明書及圖式內容所為之等效技術變化,均包含於本發明之範圍內。
Z‧‧‧立體堆疊式封裝結構
1’‧‧‧電路基板模組
1‧‧‧第一單元
10‧‧‧第一基板
100‧‧‧周邊
100A‧‧‧第一側邊
100B‧‧‧第二側邊
101‧‧‧通道
102‧‧‧第一導電焊墊
11‧‧‧第一電子元件
2’‧‧‧模封材料
2‧‧‧模封單元
20A‧‧‧頂部
20B‧‧‧框體
200B‧‧‧開口
20C‧‧‧連接體
20D‧‧‧底部封裝體
3‧‧‧導電單元
30‧‧‧導電體
4‧‧‧第二單元
40‧‧‧第二基板
400‧‧‧周邊
402‧‧‧第二導電焊墊
41‧‧‧第二電子元件
M‧‧‧模具結構
M1‧‧‧上模具
M10‧‧‧上殼體
M11‧‧‧輸入孔
M12‧‧‧容置空間
M2‧‧‧下模具
M20‧‧‧下殼體
M21‧‧‧排氣通道
M22‧‧‧凸塊
M23‧‧‧圍繞通道
M24‧‧‧流道
S‧‧‧焊錫
X-X‧‧‧切割線
圖1為本發明電路基板模組的上視示意圖。
圖2為本發明將電路基板模組放置於模具結構內且填充模封材料的側視示意圖。
圖3A為本發明將多個導電體分別填滿多個開口的側視示意圖。
圖3B為本發明將多個導電體分別填滿多個開口的底視示意圖。
圖4為本發明第一實施例所揭露的立體堆疊式封裝結構的側視示意圖。
圖5為本發明第二實施例所揭露的立體堆疊式封裝結構的側視示意圖。
圖6A為本發明將電路基板模組放置於另外一種模具結構
內且填充模封材料的側視示意圖。
圖6B為本發明第三實施例所揭露的立體堆疊式封裝結構的側視示意圖。
圖7為本發明立體堆疊式封裝結構的製作方法的流程圖。
Z‧‧‧立體堆疊式封裝結構
1‧‧‧第一單元
10‧‧‧第一基板
100‧‧‧周邊
101‧‧‧通道
102‧‧‧第一導電焊墊
11‧‧‧第一電子元件
2‧‧‧模封單元
20A‧‧‧頂部
20B‧‧‧框體
200B‧‧‧開口
20C‧‧‧連接體
3‧‧‧導電單元
30‧‧‧導電體
4‧‧‧第二單元
40‧‧‧第二基板
400‧‧‧周邊
402‧‧‧第二導電焊墊
41‧‧‧第二電子元件
S‧‧‧焊錫
Claims (10)
- 一種立體堆疊式封裝結構,其包括:一第一單元,其包括一第一基板及至少一第一電子元件設置並電性連接於所述第一基板,其中所述第一基板的周邊上具有至少一通道貫穿所述第一基板,且所述第一基板具有至少一第一導電焊墊設置於所述第一基板的下表面且鄰近所述第一基板的周邊;一模封單元,其具有一頂部設置在所述第一基板的上方且覆蓋所述第一電子元件、一框體設置在所述第一基板的下表面且鄰近所述第一基板的周邊、及至少一連接體設置於所述通道內且連接於所述頂部與所述框體之間;一導電單元,其包括至少一導電體貫穿所述框體且電性連接於所述第一導電焊墊;以及一第二單元,所述第一單元堆疊在所述第二單元上,且所述第一單元通過所述導電體以電性連接於所述第二單元。
- 如申請專利範圍第1項所述之立體堆疊式封裝結構,其中所述頂部、所述框體及所述連接體三者結合成單一構件。
- 如申請專利範圍第1項所述之立體堆疊式封裝結構,其中所述第二單元包括一第二基板及至少一第二電子元件設置並電性連接於所述第二基板,所述第二基板具有至少一第二導電焊墊設置於所述第二基板的上表面且鄰近所述第二基板的周邊,所述第二導電焊墊電性連接於所述導電體。
- 如申請專利範圍第1項所述之立體堆疊式封裝結構,其中所述第一單元更包括至少一第三電子元件設置並電性連接於所述第一基板的下表面。
- 如申請專利範圍第1項所述之立體堆疊式封裝結構,其中所述導電體通過焊錫以電性接觸所述第二導電焊墊。
- 一種立體堆疊式封裝結構的製作方法,其包括下列步驟:將至少一第一單元放置在一模具結構內,所述第一單元包括一第一基板及至少一第一電子元件設置在所述第一基板上,且所述第一基板具有至少一第一導電焊墊及至少一通道;將模封材料填充於所述模具結構內,以形成一模封單元,其中所述模封單元具有一頂部覆蓋所述第一電子元件、一框體設置在所述第一基板的下表面、及至少一連接體設置於所述通道內且連接於所述頂部與所述框體之間;移除所述模具結構;形成至少一開口貫穿所述框體,其中所述開口裸露出所述第一導電焊墊;將導電體填充於所述開口內,其中所述導電體電性連接於所述第一導電焊墊;以及通過所述框體以將所述第一單元堆疊在一第二單元上,其中所述第一單元通過所述導電體以電性連接於所述第二單元。
- 如申請專利範圍第6項所述之製作方法,其中所述第二單元包括一第二基板及至少一第二電子元件設置於所述 第二基板上,且所述第二電子元件被所述框體所圍繞。
- 如申請專利範圍第6項所述之製作方法,其中將所述第一單元堆疊在一第二單元上的步驟中,更進一步包括:所述導電體通過焊錫以電性連接於所述第二單元的至少一第二導電焊墊。
- 如申請專利範圍第6項所述之製作方法,其中將所述模封材料填充於所述模具結構內的步驟中,更進一步包括:所述模封材料從所述模具結構的一輸入孔流入,且所述模封材料在填充過程中所產生的氣泡從所述模具結構的多個排氣通道排出。
- 如申請專利範圍第6項所述之製作方法,其中在形成多個所述開口的步驟中,多個所述開口是經由雷射鑽孔的方式來形成。
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FR (1) | FR2996955B1 (zh) |
TW (1) | TWI581396B (zh) |
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WO2014171225A1 (ja) * | 2013-04-16 | 2014-10-23 | 株式会社村田製作所 | 高周波部品およびこれを備える高周波モジュール |
WO2016166811A1 (ja) * | 2015-04-14 | 2016-10-20 | オリンパス株式会社 | 接続構造体および撮像装置 |
DE102015212092A1 (de) * | 2015-06-29 | 2016-12-29 | Conti Temic Microelectronic Gmbh | Elektronische Komponente und Verfahren zu deren Herstellung |
US10129979B2 (en) * | 2016-09-23 | 2018-11-13 | Apple Inc. | PCB assembly with molded matrix core |
US10455707B1 (en) | 2018-08-10 | 2019-10-22 | Apple Inc. | Connection pad for embedded components in PCB packaging |
US11721639B2 (en) * | 2020-06-29 | 2023-08-08 | Qualcomm Incorporated | Multi-component modules (MCMs) including configurable electro-magnetic isolation (EMI) shield structures, and related methods |
CN113410193B (zh) * | 2021-05-27 | 2024-05-03 | 元成科技(苏州)有限公司 | 一种8+1堆叠式芯片封装装置 |
US20230420351A1 (en) * | 2022-06-28 | 2023-12-28 | Applied Materials, Inc. | Substrate frame design for three-dimensional stacked electronic assemblies |
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US6404043B1 (en) * | 2000-06-21 | 2002-06-11 | Dense-Pac Microsystems, Inc. | Panel stacking of BGA devices to form three-dimensional modules |
US20040173894A1 (en) * | 2001-09-27 | 2004-09-09 | Amkor Technology, Inc. | Integrated circuit package including interconnection posts for multiple electrical connections |
SG118103A1 (en) * | 2001-12-12 | 2006-01-27 | Micron Technology Inc | BOC BGA package for die with I-shaped bond pad layout |
US7053476B2 (en) * | 2002-09-17 | 2006-05-30 | Chippac, Inc. | Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages |
US7049691B2 (en) * | 2002-10-08 | 2006-05-23 | Chippac, Inc. | Semiconductor multi-package module having inverted second package and including additional die or stacked package on second package |
TWI228784B (en) | 2003-12-18 | 2005-03-01 | Advanced Semiconductor Eng | Mold for semiconductor packages |
KR100619469B1 (ko) * | 2005-08-08 | 2006-09-06 | 삼성전자주식회사 | 스페이서를 갖는 보드 온 칩 패키지 및 그를 이용한 적층패키지 |
JP5598787B2 (ja) * | 2006-04-17 | 2014-10-01 | マイクロンメモリジャパン株式会社 | 積層型半導体装置の製造方法 |
TWI312569B (en) | 2006-10-12 | 2009-07-21 | Siliconware Precision Industries Co Ltd | Semiconductor package on which a semiconductor device is stacked and production method thereof |
US7635914B2 (en) * | 2007-05-17 | 2009-12-22 | Texas Instruments Incorporated | Multi layer low cost cavity substrate fabrication for pop packages |
KR20100033012A (ko) * | 2008-09-19 | 2010-03-29 | 주식회사 하이닉스반도체 | 반도체 패키지 및 이를 갖는 적층 반도체 패키지 |
FR2939963B1 (fr) * | 2008-12-11 | 2011-08-05 | St Microelectronics Grenoble | Procede de fabrication d'un support de composant semi-conducteur, support et dispositif semi-conducteur |
KR20120007840A (ko) | 2010-07-15 | 2012-01-25 | 삼성전자주식회사 | 두 개의 패키지 기판 사이에 배치된 스페이서를 가진 pop 반도체 패키지 |
TW201227922A (en) | 2010-12-30 | 2012-07-01 | Chipsip Technology Co Ltd | Stacked package structure with covers |
JP2012147403A (ja) | 2011-01-14 | 2012-08-02 | Mitsumi Electric Co Ltd | 高周波モジュール |
US8531021B2 (en) | 2011-01-27 | 2013-09-10 | Unimicron Technology Corporation | Package stack device and fabrication method thereof |
TWI433618B (zh) * | 2012-02-08 | 2014-04-01 | Universal Scient Ind Shanghai | 堆疊式基板結構 |
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US20140104799A1 (en) | 2014-04-17 |
TWI581396B (zh) | 2017-05-01 |
FR2996955B1 (fr) | 2016-08-19 |
DE102013103580A1 (de) | 2014-04-17 |
US9167686B2 (en) | 2015-10-20 |
FR2996955A1 (fr) | 2014-04-18 |
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