TWI228784B - Mold for semiconductor packages - Google Patents

Abstract

A mold for semiconductor packages includes a top mold, a bottom mold, and a middle mold. The middle mold is disposed between the top mold and the bottom mode. The top mold has a lower surface, the bottom mold has an upper surface, and the middle mold has a first surface and a second surface. The first surface and the upper surface are disposed opposite so as to define a first cavity for forming a first semiconductor package. The second surface and the bottom surface are disposed opposite so as to define a second cavity for forming a second semiconductor package.

Description

1228784 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a tracing packaging mold. Species, and in particular a semiconductor [Previous technology] With the rapid development of electronic technology, the high-tech world. In recent years, the development of electronic products has become thinner, lighter and shorter, which has led to high-density sounds. At the same speed, the two east and west regions gradually dominated the need for two-input and seven-output semiconductor packages. Similarly, in terms of semiconductor packaging, in a limited time, a large number of and σ is also pursued in high-conductor packages with the same quality.面面 ΐΐίphase = Increase production in time, the traditional system is to flatten the entire set of molds, such as: Figure -1: The traditional semiconductor packaging mold A is shown Γ ^ / No, the semiconductor packaging mold 10 is used to manufacture Λ Of the stencil. The semiconductor package mold 10 includes an upper mold 110, ♦, and 116. The values M, and U further include a plurality of lower surfaces of the cavity 1 1 2 and ^, and the stamping process for washing the semiconductor package mold 10 is as follows: First, the substrate 132 configured with a plurality of wafers is placed in the upper mold 12 〇 The lower surface is made up of 22; 0, and the upper surface 124 makes the packaging material from the runner 116 to be filled with H; it flows into the cavity to be filled, and finally the semiconductor packages 134, 136, 138 are formed. However, the mold used in the package is very large. If the traditional method is used to expand the entire group of molds in a planar manner, a relatively large area needs to be used. Furthermore, as the mold area becomes larger, it is easy for the packaging material to harden before it flows to the positioning, resulting in the failure to complete the potting within the mold flow time, which in turn makes the product good.

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Rate decreases. [Summary of the invention] There is a bell in this body packaging mold, which performs the glue filling operation, and the degree is further increased. The object of the present invention is to provide a three-dimensional semiconductor with a stacked design, which can not only advance the molds of each layer at the same time, but also effectively shorten The overall pouring time improves the stable production capacity and product yield of the process. Three books :: Purpose: To propose a three-dimensional semiconductor package mold, the second intermediate mold. The middle mold is configured on the upper mold and-

ίί: The lower surface mold has an upper surface, and the middle surface is opposite to the upper surface, and the mouth forms a first cavity for configuring a first semiconductor package. , Opposite to the lower surface and combined to form the first: cavity, using a semiconductor package. -置 第-According to the object of the present invention, a three-dimensional semiconductor device is further provided, which includes a lower mold and a plurality of upper molds. Several upper molds are stacked on the lower mold. A plurality of cavities are respectively formed between the upper molds adjacent to each other, and between the lower mold and the adjacent corresponding upper molds to form a plurality of semiconducting components.

According to the object of the present invention, another three-dimensional semiconductor package mold is provided, which includes an upper mold, a lower mold, and a plurality of intermediate molds. Several intermediate modes are acoustically stacked between the upper and lower molds. A first cavity is formed between the lower mold and its adjacent corresponding middle ^, and a plurality of cavities are formed by combining the two adjacent adjacent intermediate molds and between the upper mold and its adjacent corresponding intermediate mold. Match

1228784 V. Description of the invention (3) Several semiconductor packages are installed. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible ', a preferred embodiment is given below, and in conjunction with the accompanying drawings, the detailed description is as follows: [Embodiment]

(2) Referring to FIGS. 2 to 3, a schematic diagram of a solid-state semiconductor package mold according to a first embodiment of the present invention is shown. The three-dimensional semiconductor package mold 2 0 'includes an upper mold 21 0, a lower mold 2 2 0, and an intermediate mold 2 3 0. The middle mold 2 3 0 is disposed between the upper mold 210 and the lower mold 220. As shown in Fig. 2, the upper mold 210 has a lower surface 212, the intermediate mold 230 has a first surface 232 and a second surface 234, and the lower mold 220 has an upper surface 224. The intermediate mold 230 further has a first upper cavity 238 disposed on the first surface 232. The upper mold 210 has a second upper mold cavity 218 and is disposed on the lower surface 212. The first surface 232 of the intermediate mold 230 and the upper surface 224 of the lower mold 220 are oppositely disposed and combined to form a first cavity for configuring a carrier plate with a wafer to form a first semiconductor package 332. The second surface 234 of the intermediate mold 230 is opposite to the lower surface 212 of the upper mold 210 and combined to form a second cavity for configuring another carrier plate with a wafer to form a second semiconductor package 312. Packaging molds can continue to expand upwards. Therefore, the assembly can be formed between two adjacent upper molds. As shown in Fig. 3, the upper ′ makes the upper die 21 〇 and the other upper

The three-dimensional semiconductor of the first embodiment has a plurality of cavities in a stacked configuration, and a plurality of cavities corresponding to the lower mold and its adjacent ones. Mod 24〇

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A substrate 344 on which a wafer is disposed may be disposed between the molds 240. The three-dimensional semiconductor packaging molds 20 and 30 are molds for manufacturing substrate-type packages. Therefore, the first semiconductor package 332, the second semiconductor package 312, and the third semiconductor package 342 are substrate-type packages. The stamping process of the three-dimensional semiconductor package mold 20 is as follows: First, a plurality of substrates 314, 334, and 344 on which wafers are arranged are simultaneously placed on the upper surfaces of the intermediate mold 230, the lower mold 220, and the upper mold 210, respectively. Then, the lower surfaces of the upper mold 2 10, the middle mold 2 30, and the other upper mold 2 40 are pressed to the substrates 314, 334, and 344, respectively, by pressing. At the same time, the packaging material is directly flowed from the runners 216, 23 6, 246 into the corresponding cavity to fill it, and finally the semiconductor packages 312, 332'342 are formed. It should be noted that the position of the washing channel is limited to the top of the cavity, as shown in Figure 1, the washing channel is located at the bottom of the cavity. 1 Please refer to FIGS. 4 to 5, which are schematic diagrams of a solid-state semiconductor packaging mold according to a second embodiment of the present invention. The three-dimensional semiconductor package mold 40 includes an upper mold 410, a lower mold 420, and an intermediate mold 430. Intermediate mold 430 series

It is arranged between the upper mold 410 and the lower mold 420. As shown in Fig. 4, the upper mold 41 () has a lower surface 412, the middle mold 430 has a first surface 432 and a second surface ... 434, and the lower mold 420 has an upper surface 424. The intermediate mold 430 further includes a first upper mold eight 438 and a first upper mold cavity 439, which are respectively disposed on the first surface 432 and the second surface 434. The upper die 41 has a second lower die cavity 418 and is disposed on the lower surface 412 ′. The lower die 420 further has a first lower die cavity 429 and is disposed on the upper surface 424. The first surface 432 of the intermediate mold 430 is opposite to the upper surface 424 of the lower mold 42 and is combined to form a first cavity. The first cavity includes a first upper mold cavity 43 8

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V. Description of the invention (5) ". The next two 'cavities are used to form the first semiconductor package oppositely arranged and combined to form the second cavity. The first-*: surface 412 Λ: used to form the second semiconductor package 512. The module can be expanded, and it has sound Π = can continue to increase the number of intermediate modes in the medium μ η λ 'layer configuration, inserted between and between the lower mold 420. Therefore, it can be in two adjacent intermediate modes. Zhi, Jian's upper die and the adjacent one of the corresponding upper die and Yongxi Φ Μ @ > Μ between the former die, and the lower die and its semi-conducting two-born two chus are combined to form several Cavity with the number of configurations: 'the upper mold 410 and the middle surface = 2: ί, so that another upper mold 44 ° and the middle mold ν form a second semiconductor package 542. Three-dimensional semiconductor packaging mold 0 and 50 is a mold for manufacturing lead frame packages. Therefore, the first half mu2: the second semiconductor package 512 and the third semiconductor package 542 are lead frame packages. The three-dimensional semiconductor package mold 50 is a stamper. The process is as follows: First, a plurality of lead frames 514, 534, and 544 configured with a chip are simultaneously corresponded. It is placed on the upper surface of the other middle mold 440, the lower mold 420, and the middle mold 430. Then, the lower surface of the upper mold 410, the middle mold 430, and the other middle mold 44 is pressed with the lead frame 514, 534, and 544, respectively At the same time, the packaging material is directly flowed from the runners 416, 436, and 446 into the corresponding mold cavity to fill it, and finally the semiconductor packages 512, 532, and 542 are formed. The three-dimensional semiconductor package disclosed in the above embodiment of the present invention The mold has a layered structure, and multiple substrates TW1292F (sun and moon light) can be used in the vertical direction to increase the number of substrates TW1292F (sun and moon light). Ptd page 14 1228784 V. Description of the invention (6) or the lead frame is simultaneously filled with the traditional plane filling time reduction Product yield. This is a relatively small volume mold and die operation. In summary, it is not used to load / load (10) (j / uni 〇acj), the plastic 'process is easier to control the environmental factors. The packaging mold adopts the method of expanding the area. The short' effectively shortens the mold flow time and improves the verticality of the three-dimensional semiconductor packaging mold outside the process. The intermediate mold can also be used at the same time. Mold, adjacent middle and lower mold, and only need to press once to complete the description 'Although the present invention has been limited to the present invention with a preferred embodiment, anyone skilled in this art, and within the scope, can be used for a variety of The range of changes and compliance should be in accordance with the scope of the attached patent application. And each layer can also be in a condition. Compared with the above, it can make the overall mold and the design of the production model design required, or the disclosure of the next multi-layer mold is as above. Retouched, so the definition is TW1292F (Sun Moonlight) .ptd Page 15 1228784

Brief Description of Drawings [Simple Description of Drawings] Conductor Figure 1 shows a schematic diagram of a conventional semiconductor packaging mold. Figures 2 to 3 show the three-dimensional packaging molds according to the first embodiment of the present invention. 4 to 5 are schematic diagrams of a three-dimensional packaging mold according to a second embodiment of the present invention. > Explanation of reference symbols of thousand conductor pattern I 0: Semiconductor package mold II 0, 21 0, 41 〇 · Upper mold 11 2, 21 2 · Lower surface 11 6: Sprue 11 8, 11 9 · Channel 120 , 220, 420: Lower molds 124, 224Upper surfaces 132, 314, 334, 344: Substrates 134, 136, 138, 312, 332, 342: Substrate-type semiconductor packages 512, 532, 542: Lead-frame semiconductor packages 20, 30, 40, 50: three-dimensional semiconductor package molds 216, 416: second runners 218, 418: second upper mold cavity 230, 430: intermediate molds 232, 432: first surface

TW1292F (sun and moonlight). Ptd Page 16 1228784 Simple illustration of the drawings 234, 434: second surface 236, 436: first runner 238, 438: first upper die cavity 240: another upper die 429: first lower die Cavity 439: Second lower mold cavity 440: Another middle mold 514, 534, 544: Lead frame

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Claims (1)

228784 ^ 'Application for patent scope 1. A three-dimensional semiconductor packaging mold, comprising: an upper mold, which has a lower surface and a lower mold, has an upper surface and an intermediate mold, and is disposed thereon with a first surface and a second surface; It is set and combined to form a first component, and the second surface and the cavity below are used to configure a second semiconductor 2. If the scope of patent application is the first! It also has: a first upper mold cavity, which is arranged at 3 · if the patent application scope, the second cavity includes the first upper mold cavity. 4 · If the second scope of the patent application has a second upper mold cavity, it is arranged at 5 · If the fourth scope of the patent application scope includes the second upper mold cavity. 6 · If the scope of the patent application is the fourth conductor package and the second semiconductor 7 · If the scope of the patent application is the fourth with a first lower mold cavity and is arranged at 8 · If the scope of the patent application is in the 7th cavity including the first upper mold cavity And the ninth, such as the scope of patent application 7: between the mold and the lower mold, the intermediate mold, wherein the first surface and the upper surface cavity are used to configure a first semiconductor cover oppositely arranged and combined to form a第二 包装 件 The second package. The mold according to the item, wherein the intermediate mold is the first surface. The mold according to item 1, wherein the mold according to the first item, wherein the upper mold is further changed to the lower surface. The mold according to the item, wherein the mold according to the second item, wherein the first half package is a substrate package. The mold according to the item, wherein the lower mold further changes the upper surface. The mold described in the item, wherein the first cavity is hollowed. The mold of item, wherein the intermediate mold 1228784 6. The scope of patent application has: a second lower mold cavity, ιο · If the application cavity includes the second 11. Semiconductor seal 0 If the application package and 12. If the application mold includes a first pouring first cavity Cavity. 13. Includes the first cavity, the second cavity, the second cavity, and the like. 14. A stand down and a plurality of adjacent components. 15. Table below the mold 16. The cavity includes the 17. mold; several upper molds are combined to form if the application side is more like applying some mold cavities if applying to be disposed on the second surface. The mold according to item 7 of the patent, wherein the second upper mold cavity and the second lower mold cavity. The mold described in item 10 of the patent scope, wherein the _ the second semiconductor package is the mold described in item 1 of the leadframe package patent scope, wherein the middle lane 'causes a packaging material to flow through the The runner is injected with the mold described in item 1 of the patent scope, wherein the upper mold 'injects the packaging material through the second runner and is injected into the bulk semiconductor packaging mold, including: a mold' is arranged in the lower layer A plurality of cavities between two of them, and between the lower mold and an adjacent corresponding upper mold, for configuring a plurality of molds described in item 14 of the semiconductor package patent scope, wherein There are multiple mold cavities. The molds described in item 15 of the patent scope, which are empty. The molds described in item 14 of the patent scope, which are described in «HI page 19 1228784. There are several ways to inject-encapsulate material through these detours and inject 18: three-dimensional semiconductor packaging molds, including: an upper mold, a lower mold; and a plurality of intermediate wedges, s worm bucket w where the lower mold and Between the adjacent pair of upper molds and the lower mold, a cavity is formed between the two adjacent adjacent intermediate molds-the-the intermediate molds of the upper mold, and a plurality of corresponding ones of the upper mold and the adjacent ones The semiconductor package ^ forms a plurality of cavities for matching and has a mold as described in 9. A range of item 18, in which the upper mold and the boy's chess hole are arranged on the lower surface. Middle: Please refer to the molds described in item 19 of the patent scope. Each of the plurality of first lower mold cavities is arranged on the upper surface of the middle molds; the plurality of second upper mold cavities are arranged on the middle Under the mold surface. ^ 21. The molds described in item 20 of the patent application scope, wherein the lower molds further have a plurality of second lower mold cavities, which are arranged on the upper molds. 2 2. The mold according to item 21 of the scope of patent application, wherein the semiconductor packages are lead frame packages. 23. The mold as described in item a of the patent application range, wherein the upper mold and the intermediate molds include a plurality of washing channels, and a packaging material is caused to flow through the washing channels to be injected into the cavities. TW1292F (Sun and Moonlight) .ptd Page 20