TW201409609A - 一種電子裝置 - Google Patents

一種電子裝置 Download PDF

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TW201409609A
TW201409609A TW101130491A TW101130491A TW201409609A TW 201409609 A TW201409609 A TW 201409609A TW 101130491 A TW101130491 A TW 101130491A TW 101130491 A TW101130491 A TW 101130491A TW 201409609 A TW201409609 A TW 201409609A
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core
electronic device
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TWI469251B (zh
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Ta-Hsun Yeh
Tay-Her Tsaur
Cheng-Cheng Yen
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Realtek Semiconductor Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
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    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/06155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0616—Random array, i.e. array with no symmetry
    • H01L2224/06163—Random array, i.e. array with no symmetry with a staggered arrangement
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0616—Random array, i.e. array with no symmetry
    • H01L2224/06164—Random array, i.e. array with no symmetry covering only portions of the surface to be connected
    • H01L2224/06165—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices

Abstract

一種電子裝置，包含核心電路與複數個焊墊單元。核心電路包含有複數個核心金氧半導體，而複數個焊墊單元則分別與該核心電路電連接，每個焊墊單元又包含至少一個焊墊金氧半導體。每個核心金氧半導體的核心閘極，與每個焊墊金氧半導體的焊墊閘極，都具有相同之延伸方向。

Description

一種電子裝置
本發明有關於一種電子裝置。特別是，本發明關於一種具有核心電路(core circuit)與焊墊單元(pad unit)電連接的電子裝置。在核心金氧半導體(core MOS)中的核心閘極，與焊墊金氧半導體(pad MOS)中的焊墊閘極，都具有相同或是彼此平行之延伸方向。
一般以半導體製程來製造具有積體電路(integrated circuit)的晶片。此等晶片會設計具有輸出/輸入(I/O)用之焊墊單元，以接收輸入訊號及傳送輸出訊號等連接功能，也可用以控制或是驅動訊號，亦即晶片透過焊墊與其他電路溝通。
此外，積體電路(IC)晶片在製造過程及系統應用時，都可能會遭受到靜電放電(ESD)的情況，靜電放電訊號可能會由晶片的焊墊傳送到晶片中，而損壞晶片的內部電路。因此，晶片的焊墊電路也需防止靜電放電的情況。
然而，在進入了40奈米(nm)以下的先進製程後，元件的不匹配(device dismatch)的問題，使得積體電路的核心電路以及焊墊單元之元件的元件特性遭遇許多的挑戰。
因此，本發明的目的之一在於提出一種電子裝置(如積體電路)，其將核心電路以及焊墊單元之金氧半導體(MOS)元件擺放同一方向，以克服習知技術元件不匹配的問題；並進一步提出多種焊墊單元的不同擺放方式，其可最佳化面積使用率，並增加與核心電路或焊線(bonding wire)連接的方便性與多樣性。
本發明首先提出一種電子裝置，包含核心電路與複數個焊墊單元。核心電路包含有複數個核心金氧半導體，而複數個焊墊單元則分別與核心電路電連接，每個焊墊單元又包含有至少一個焊墊金氧半導體。每個核心金氧半導體的核心閘極與每個焊墊金氧半導體的焊墊閘極，都具有相同之延伸方向。
本發明其次提出另一種電子裝置，包含核心電路與複數個焊墊單元。核心電路包含有複數個核心金氧半導體，而複數個焊墊單元則分別與核心電路電連接，每個焊墊單元又包含有至少一個焊墊金氧半導體。每個核心金氧半導體的核心閘極與每個焊墊金氧半導體的焊墊閘極，都具有彼此平行之延伸方向。
根據本發明實施例之電子裝置，其所有金氧半導體的閘極，無論是來自核心電路或是焊墊單元，都具有相同或是彼 此平行之延伸方向。另外，焊墊單元還可以多種不同的方式，排列在核心電路的四個側邊區域。
第1圖至第7圖繪示本發明電子裝置的多種實施例。第1圖繪示本發明電子裝置的焊墊單元群(pad unit group)中，單排的焊墊單元排列在核心電路四個側邊附近的實施態樣。請參閱第1圖，本發明電子裝置100位於晶片101上，至少包含有核心電路110與複數個焊墊單元120。核心電路110是晶片101執行主要功能的區域，在核心電路110中會包含有複數個核心金氧半導體，例如核心金氧半導體111/112/113。
另一方面，複數個焊墊單元120則位於核心電路110的周邊區域，負責控制、驅動、電連接晶片，或是防止靜電放電傷害核心電路110。複數個焊墊單元120分別與核心電路電連接。例如，焊墊單元120中包含N型金氧半導體區域121、焊墊區域122與P型金氧半導體區域123。在一實施例中，焊墊區域122為具銲墊下電路(circuit under pad,CUP)之銲墊，因此其下可具有金氧半導體。因而焊墊金氧半導體124則可能位於N型金氧半導體區域121、焊墊區域122與P型金氧半導體區域123其中之至少一者中。較佳者，N型金氧半導體區域121、焊墊區域122與P型金氧半導體區域123中均有焊墊金氧半導體124。
一方面，每個核心金氧半導體111/112/113中都會有核心閘極114。另一方面，由於焊墊單元120中包含N型金氧 半導體區域121、焊墊區域122與P型金氧半導體區域123，而N型金氧半導體區域121、焊墊區域122與P型金氧半導體區域123中都可能有焊墊金氧半導體124，所以焊墊單元120中一定會有焊墊閘極125。請參考第2圖，所有的核心閘極114與焊墊閘極125均具有相同之延伸方向。或請參考第3圖，所有的核心閘極114與焊墊閘極125均具有彼此平行之延伸方向。於第2圖及第3圖中，所有的核心閘極114與焊墊閘極125均於垂直方向延伸或平行，而其對應之源極與汲極則在其兩側(於平行方向)。
在本發明的一個實施方式中，如第1圖所繪示，複數個焊墊單元120可以分成多個焊墊單元群126，而每個焊墊單元群126即沿著與核心電路110相鄰之側邊區域的其中一者排列。在本發明的另一個實施方式中，如第4圖或第5圖所繪示，複數個焊墊單元120亦可以分成多個焊墊單元群126，沿著核心電路110的相鄰側邊排列，而且位於核心電路110的四個側邊其中的一個側邊的焊墊單元群126的複數個焊墊單元120，可以是單排之焊墊單元120，如第1圖所繪示，或是具有至少兩排之焊墊單元120，如第4圖、第5圖、第6圖或第7圖所繪示。換言之，在多個焊墊單元群126中，可以有一個焊墊單元群126具有至少兩排之焊墊單元120。
本發明焊墊單元群126中的焊墊單元120，可以依據不同的需要，多樣化的安排在核心電路110的四個側邊附近。 以下將提出多種焊墊單元群126與焊墊單元120安排在核心電路110的四個側邊附近的可能排列方式。
首先，在本發明的一種實施例中，如第1圖或第4圖所繪示，某個焊墊單元群126中所有焊墊單元120的焊墊區域122都夾至於N型金氧半導體區域121與P型金氧半導體區域之間123(排列方式210)。或是，焊墊單元120中的N型金氧半導體區域121係夾至於焊墊區域122與P型金氧半導體區域之間123(排列方式211)。也可以是，焊墊單元120中的P型金氧半導體區域123係夾至於N型金氧半導體區域121與焊墊區域之間122(排列方式212)。
其次，在本發明的另一個實施例中，如第1圖或第6圖所繪示，焊墊單元120中的焊墊區域122夾至於相鄰焊墊單元120中的焊墊區域122之間(排列方式220)。在本發明的又一個實施例中，如第1圖或第4圖所繪示，相鄰焊墊單元120中的焊墊區域122呈交錯排列(排列方式230)。
還有，在本發明的一個實施例中，如第5圖或第7圖所繪示，在相鄰兩排中之焊墊單元120彼此呈交錯排列(排列方式240)。
或是，在本發明的另一個實施例中，如第4圖、第5圖、第6圖或第7圖所繪示，同一排焊墊單元中的焊墊區域呈交錯排列(排列方式250)。在本發明的又一個實施例中，如第1圖或第5圖所繪示，同一排焊墊單元120中的焊墊區域122具有相同之排序(order)(排列方式260)，例如均位於第一 個位置、第二個位置或第三個位置。另外，在本發明的再一個實施例中，第1圖、第6圖或第7圖所繪示，同一排焊墊單元具有相同之排序(排列方式270)。
還有，在本發明的一個實施例中，如第6圖或第7圖所繪示，焊墊單元群126中還可以具有三排或以上之焊墊單元120。以簡化圖示之故，第6圖或第7圖僅僅繪示三排作為範例。如果焊墊單元群126中還可以具有三排或以上之焊墊單元120時，焊墊單元120中的焊墊區域122有可能會夾至於相鄰焊墊中的焊墊區域之間(排列方式280)。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
100‧‧‧電子裝置
101‧‧‧晶片
110‧‧‧核心電路
111/112/113‧‧‧核心金氧半導體
114‧‧‧核心閘極
120‧‧‧焊墊單元
121‧‧‧N型金氧半導體區域
122‧‧‧焊墊區域
123‧‧‧P型金氧半導體區域
124‧‧‧焊墊金氧半導體
125‧‧‧焊墊閘極
126‧‧‧焊墊單元群
210/211/212/220/230/240/250/260/270/280‧‧‧排列方式
第1圖至第7圖繪示本發明電子裝置的多種實施例。
第1圖繪示本發明電子裝置的焊墊單元群中，單排的焊墊單元排列在核心電路四個側邊附近的實施態樣。
第2圖繪示核心閘極與焊墊閘極都具有相同之延伸方向。
第3圖繪示核心閘極與焊墊閘極都具有彼此平行之延伸方向。
101‧‧‧晶片
110‧‧‧核心電路
114‧‧‧核心閘極
120‧‧‧焊墊單元
125‧‧‧焊墊閘極

Claims (12)

  1. 一種電子裝置，包含：一核心電路(core circuit)，其包含複數個核心金氧半導體(core MOS)；以及複數個焊墊單元(pad unit)，分別與該核心電路電連接，而且每個焊墊單元包含至少一個焊墊金氧半導體(pad MOS)；其中，每個核心金氧半導體的一核心閘極，與每個焊墊金氧半導體的一焊墊閘極，都具有相同之延伸方向。
  2. 如請求項1的電子裝置，其中該焊墊金氧半導體位於該焊墊單元之一N型金氧半導體(NMOS)區域、一焊墊區域與一P型金氧半導體(PMOS)區域之至少一者中。
  3. 如請求項1的電子裝置，其中每個該焊墊單元中的該焊墊區域都夾至於該N型金氧半導體區域與該P型金氧半導體區域之間。
  4. 如請求項1的電子裝置，其中相鄰之該焊墊單元中的該焊墊區域呈交錯排列。
  5. 如請求項1的電子裝置，其中該焊墊單元中的該焊墊區域夾至於相鄰該焊墊單元中的該焊墊區域之間。
  6. 如請求項1的電子裝置，其中位於該核心電路的四側邊其中一側 邊的複數個焊墊單元具有至少兩排之焊墊單元。
  7. 如請求項6的電子裝置，其中在相鄰兩排中之該些焊墊單元彼此呈交錯排列。
  8. 一種電子裝置，包含：一核心電路，其包含複數個核心金氧半導體；以及複數個焊墊單元，分別與該核心電路電連接，而且每個焊墊單元包含至少一個焊墊金氧半導體；其中，每個核心金氧半導體的一核心閘極，與每個焊墊金氧半導體的一焊墊閘極，都具有彼此平行之延伸方向。
  9. 如請求項8的電子裝置，其中該焊墊金氧半導體位於該焊墊單元之一N型金氧半導體區域、一焊墊區域與一P型金氧半導體區域之至少一者中。
  10. 如請求項9的電子裝置，其中位於該核心電路的四側邊其中一側邊的複數個焊墊單元具有至少兩排之焊墊單元。
  11. 如請求項10的電子裝置，其中在相鄰兩排中之該些焊墊單元彼此呈交錯排列。
  12. 如請求項10的電子裝置，其中同一排之該些焊墊單元中的該些 焊墊區域呈交錯排列。
TW101130491A 2012-08-22 2012-08-22 一種電子裝置 TWI469251B (zh)

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Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5698873A (en) * 1996-03-08 1997-12-16 Lsi Logic Corporation High density gate array base cell architecture
US6559055B2 (en) * 2000-08-15 2003-05-06 Mosel Vitelic, Inc. Dummy structures that protect circuit elements during polishing
JP4091838B2 (ja) * 2001-03-30 2008-05-28 富士通株式会社 半導体装置
US6900528B2 (en) * 2001-06-21 2005-05-31 Micron Technology, Inc. Stacked mass storage flash memory package
JP4624660B2 (ja) * 2003-10-09 2011-02-02 ルネサスエレクトロニクス株式会社 半導体装置
TW200625641A (en) * 2004-09-24 2006-07-16 Koninkl Philips Electronics Nv Field effect transistor
KR100981658B1 (ko) * 2005-05-23 2010-09-13 후지쯔 세미컨덕터 가부시키가이샤 반도체 장치의 제조 방법
TWI370515B (en) * 2006-09-29 2012-08-11 Megica Corp Circuit component
JP5054359B2 (ja) * 2006-12-01 2012-10-24 パナソニック株式会社 半導体集積回路及びその製造方法
TW201010043A (en) * 2008-08-29 2010-03-01 Advanced Analog Technology Inc ESD protection device
TWI399844B (zh) * 2009-11-24 2013-06-21 Nuvoton Technology Corp 晶片及其靜電放電保護元件
US8368468B2 (en) * 2010-05-20 2013-02-05 Himax Analogic, Inc. Error amplifier and LED circuit comprising the same
JP2012119383A (ja) * 2010-11-29 2012-06-21 Renesas Electronics Corp 半導体装置およびその製造方法
US9117677B2 (en) * 2011-10-13 2015-08-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor integrated circuit having a resistor and method of forming the same

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