TW201401519A - 積體電路裝置及其製造方法 - Google Patents

積體電路裝置及其製造方法 Download PDF

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TW201401519A
TW201401519A TW102120060A TW102120060A TW201401519A TW 201401519 A TW201401519 A TW 201401519A TW 102120060 A TW102120060 A TW 102120060A TW 102120060 A TW102120060 A TW 102120060A TW 201401519 A TW201401519 A TW 201401519A
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TWI542005B (zh
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Chi-Feng Huang
Chia-Chung Chen
Victor Chiang Liang
Mingo Liu
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Taiwan Semiconductor Mfg
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Abstract

一種積體電路裝置之製造方法，包括：形成具有一第一導電類型之一深井區於一基板之內；佈植該深井區之一部，以形成一第一閘極；以及佈植該深井區，以形成一井區。該井區與該第一閘極具有相反於該第一導電類型之一第二導電類型。施行一離子佈植，形成具有該第一導電類型之一通道區於該第一閘極之上；佈植覆蓋該通道區之該深井區之一部，以形成具有該第二導電類型之一第二閘極。施行一第一源極/汲極佈植，以形成位於該第二閘極相對側之一第一源極區與一第二汲極區。該第一源極區與該第一汲極區連結於該通道區且覆蓋該通道區與該第一閘極。

Description

積體電路裝置及其製造方法
本發明係關於積體電路製作，且特別是關於一種積體電路裝置及其製造方法。
積體電路包括金氧半導體裝置(MOS devices)、二極體、電容、電感、電阻或相似物等眾多裝置。此些裝置的製程需經過整合以於同一個半導體晶片之內形成此些裝置。
依據一實施例，本發明提供了一種積體電路裝置之製造方法，包括：形成具有一第一導電類型之一深井區於一基板之內；佈植該深井區之一部，以形成一第一閘極；佈植該深井區，以形成一井區，其中該井區與該第一閘極具有相反於該第一導電類型之一第二導電類型，且其中該深井區包括連結於該第一閘極之一端之一部；施行一離子佈植，形成一通道區於該第一閘極之上，其中該通道區具有該第一導電類型；佈植覆蓋該通道區之該深井區之一部，以形成具有該第二導電類型之一第二閘極；以及施行一第一源極/汲極佈植，以形成位於該第二閘極相對側之一第一源極區與一第二汲極區，其中該第一源極區與該第一汲極區具有該第一導電類型並連結於該通道區，而其中該第一源極區與該第一汲極區係覆蓋該通道區與 該第一閘極。
依據另一實施例，本發明提供了一種積體電路裝 置之製造方法，包括：形成具有一第一導電類型之一深井區於一基板內；佈植該深井區之一部，以形成一底閘極；佈植該深井區，以形成自該基板之一頂面延伸至該底閘極之一環狀井區，其中該環狀井區與該底閘極具有相反於該第一導電類型之一第二導電類型，且其中該環狀井區環繞該底閘極；佈植覆蓋與接觸該底閘極區之該深井區之一部，以形成具有該第一導電類型之一通道區；佈植覆蓋該通道區之該深井區之一部，以形成具有該第二導電類型之一頂閘極；施行一第一源極/汲極佈植，以形成位於該頂閘極之相對側之一第一源極區與一第二汲極區，其中該第一源極區與該第一汲極區具有該第一導電類型並連結於該通道區，而其中該第一源極區與該第一汲極區係覆蓋該通道區與該底閘極；於該第一源極/汲極佈植之後，形成一金氧半導體裝置之一閘堆疊物於該基板之上；以及於形成該閘堆疊物之後，施行一第二源極/汲極佈植，以形成該金氧半導體裝置之一第二源極區與一第二汲極區。
依據又一實施例，本發明提供了一種積體電路裝置，包括：一第一導電類型之一深井區，位於一基板內；一底閘極，位於該深井區內；一井區，自該基板之一頂面延伸至該底閘極，其中該井區與該底閘極具有相反於該第一導電類型之一第二導電類型；一通道區，具有該第一導電類型，覆蓋與接觸該底閘極區；一頂閘極，具有該第二導電類型，覆蓋該通道區且與該通道區形成了一P-N接面；以及一源極區與一汲極 區，位於該頂閘極之相對側，其中該源極區與該汲極區具有該第一導電類型並連結於該通道區，且其中該源極區與該汲極區覆蓋了該通道區與該底閘極。
為讓本發明之上述目的、特徵及優點能更明顯易 懂，下文特舉一較佳實施例，並配合所附的圖式，作詳細說明如下。
10‧‧‧晶圓
20‧‧‧基板
22‧‧‧隔離區/淺溝槽隔離區
24‧‧‧深N型井區
26‧‧‧光阻
28‧‧‧埋設井區
30‧‧‧光阻
32‧‧‧P型井區
34‧‧‧光阻
35‧‧‧光阻
36‧‧‧P型接觸區
40‧‧‧光阻
42‧‧‧通道區
46‧‧‧光阻
48‧‧‧N型源極/汲極加強區
49‧‧‧深N型井區接觸區
52‧‧‧光阻
53‧‧‧頂閘極
54‧‧‧光阻
56‧‧‧源極/汲極區
56A‧‧‧源極區
56B‧‧‧汲極區
58‧‧‧電阻保護氧化物區
100‧‧‧N型金氧半導體裝置
102‧‧‧閘介電層
104‧‧‧閘電極
106‧‧‧硬罩幕層
108‧‧‧閘間隔物
110‧‧‧閘堆疊物
112‧‧‧輕度摻雜汲極區
114‧‧‧環型/口袋區
116‧‧‧源極/汲極區
200‧‧‧P型金氧半導體裝置
202‧‧‧閘介電層
204‧‧‧閘電極
206‧‧‧硬罩幕層
208‧‧‧閘間隔物
210‧‧‧閘堆疊物
212‧‧‧輕度摻雜汲極區
214‧‧‧環型/口袋區
215‧‧‧井區
216‧‧‧源極/汲極區
220‧‧‧接面場效電晶體
302、304、306‧‧‧變容器
402、404‧‧‧電阻
502、504、506‧‧‧二極體
602、604‧‧‧雙極接面電晶體
D1‧‧‧距離
VG1、VG2‧‧‧電壓
I‧‧‧電流
S1、S2‧‧‧間距
第1-10圖為一系列剖面圖，顯示了依據本發明之一實施例之一積體電路結構之製造方法之多個中間階段；第11-15圖為一系列剖面圖，顯示了依據本發明之多個實施例之一半導體裝置；以及第16-23圖顯示了依據本發明之多個實施例之一佈局情形。
本發明提供了適用於形成多種裝置之積體電路結構及其製造方法之多個實施例。於以下圖式中顯示了於形成此些積體電路結構的中間階段。下文中也討論了此些實施例之變化情形。於以下不同之圖式與圖示實施例之中，相同標號係代表相同元件。雖然圖示之實施例中提供了形成具有P型底閘極與頂閘極與N型通道之一積體電路結構，可以理解的是，本發明亦適用於形成具有N型底閘極與頂閘極與P型通道之一積體電路結構，其具有相反於上述實施例之摻雜半導體區域。
第1圖顯示了於基板20之頂面上形成數個隔離區 22，其可為晶圓10之一部。基板20為一半導體基板，其可為一矽基板，雖然亦可使用如鍺、矽鍺、III-V族半導體材料或相似物之其他半導體材料。此些隔離區22可為淺溝槽隔離(STI)區，故因此於下文中將此些隔離區稱為淺溝槽隔離區22。隔離區22亦可為如為場氧化物之其他實施情形。於基板20內形成有一深N型井區24。於部份實施例中，深N型井區24的形成包括了形成光阻26以及佈值如磷、銦或相似物之N型摻質至基板20之內。接著移除光阻26。深N型井區(deep N well)24之底面係低於淺溝槽隔離區22之底面。深N型井區24內之摻質濃度例如為介於1E13/每立方公分與1E15/每立方公分之間。
請參照第2圖，形成一P型之埋設井區(buried well region)28。於本文中，由於其於部份實施例中之可做為最終得到之場效電晶體裝置的一底閘極，故此埋設井區28亦可稱為一底閘極(bottom gate)28。其形成包括了光阻30的形成與圖案化，以及於深N型井區24之一中間位置處佈值一P型井區。接著移除光阻30。於部份實施例中，底閘極28係與淺溝槽隔離區22之底部係相分隔並具有一距離D1，其例如介於0.1-1微米。然而，值得注意的是，於本文中所描述數據僅為解說之用，且其可為其他數值。
接著，請參照第3圖，藉由一佈值步驟，形成數個 P型井區(p-well region)32，其中係採用光阻34做為一佈值罩幕。佈值能量可經過控制，使得此些P型井區32接觸了底閘極28。此些P型井區32可自基板20之頂面延伸至深N型井區24之內。雖然P型井區32可具有多種形態，當自如第3圖所示結構之 上視情形中，圖示之此些P型井區32可為同一連續之P型井區32的數個部份，以形成上視情形中之一完整的環狀物(full ring)。於部份實施例中，P型井區32之環狀物與底閘極的結合隔離了位於環狀物內側之N型區域與位於環狀物外側且低於底閘極28之基板20之其他部份。於部份實施例中，此些P型井區32具有相似於底閘極28之一P型摻質濃度，雖然此P型摻質濃度亦可大於或小於底閘極28之P型摻質濃度。
第4圖顯示了數個P型接觸區(p-type pickup region)36的形成，其可再次採用一佈值步驟而形成，且可使用光阻35做為一佈值罩幕。此些P型接觸區36於如第4圖所示結構之上視情形中亦可形成為一環狀物(ring)。於部份實施例中，P型接觸區36具有介於約1019/立方公分-1021/立方公分之一P型摻質濃度。
第5圖顯示了一通道區42的形成，其可藉由佈值所形成，並可使用光阻40做為一佈值罩幕。通道區42的形成可採用形成底閘極28之相同光罩。如此，通道區42可重疊並對準底閘極28。於此佈值步驟中，可於覆蓋底閘極28之區域內佈值額外之N型摻質，因此通道區42之摻質濃度可調整至一期望值，例如介於約1E13/立方公分-1E14/立方公分。通道區42與下方之底閘極28之間形成了一P-N接面(p-n junction)。
請參照第6圖，藉由一佈值步驟以形成數個N型源極/汲極加強區(n-type source/drain enhancement regions)48(亦稱為源極/汲極區(source/drain regions))，其中形成光阻46以做為一佈值罩幕。N型源極/汲極加強區48可具有介於約1E13/立 方公分至約1E15/立方公分之N型摻質濃度。於此同時，可形成了數個深N型井區接觸區(deep n-well pickup regions)49。
接著，如第7圖所示，形成了一N型金氧半導體裝 置(NMOS device)100與一P型金氧半導體裝置(PMOS device)200的部份構件。NMOS裝置100包括了一閘堆疊物110，其包括了閘介電層102、閘電極104、硬罩幕層106與數個閘間隔物108。於基板20內亦形成有數個N型的輕度摻雜汲極區(LDD regions)112，其例如藉由佈值所形成。亦可形成有數個P型之環型/口袋(halo/pocket)區114。PMOS裝置200包括一閘堆疊物210，其包括了閘介電層202、閘電極204、硬罩幕層206與數個閘間隔物208。於基板20內亦形成有數個P型的輕度摻雜汲極區(LDD regions)212，其例如藉由佈值所形成。亦可形成有數個N型之環型/口袋(halo/pocket)區域214。此外，亦可形成用於PMOS裝置200之一井區215。此些閘介電層102/202、閘電極104/204與硬罩幕層106/206的形成可包括坦覆地沈積一閘介電層、一閘電極層與一硬罩幕層，並接著圖案化上述膜層所形成。
於此些實施例中，N型源極/汲極區48(第6圖)及/或 通道區42(第5圖)的形成可於形成如第7圖所示之MOS裝置的構件之前形成。由於MOS裝置100與200的形成包括了如回火之數道熱製程，因此於此些熱製程之中，N型源極/汲極加強區48與通道區42內的摻質便會向外擴散，而因此N型源極/汲極加強區48內的摻質將擴散至下方區域內。如此便可改善了介於源極/汲極加強區48與通道區42之間的連結情形，並造成了各別的電阻值的降低。
第8圖顯示了PMOS裝置200之數個源極/汲極區216 的形成。形成光阻52以罩幕不想被佈值之區域。於形成此些源極/汲極區216時，可再次佈值P型接觸區36以增加其摻質濃度。而於其他實施例中，當形成源極/汲極區216時，則並未佈值此些P型接觸區36。再者，位於通道區42之上之一區域於經過佈值之後形成一頂閘極53，其為P型區域。頂閘極53接觸了通道區42並與通道區42形成了一P-N接面。
第9圖顯示了NMOS裝置100之源極/汲極區116的 形成。形成光阻54以罩幕不想被佈值之區域。於形成此些源極/汲極區116時，可再次佈植源極/汲極加強區48以增加其摻質濃度。而於其他實施例中，當形成源極/汲極區116時，則並未佈值此些源極/汲極加強區48。於最終結構中，源極/汲極加強區48的摻質濃度可更為增加。源極/汲極加強區48於下文中將稱為源極/汲極區56，其包括了源極區56A與汲極區56B。
接著，如第10圖所示，形成數個電阻保護氧化物 區(resistive protection oxide region)58，以覆蓋介於摻雜區36、49、53、56之間介面與其各別之鄰近淺溝槽隔離物區22之介面。電阻保護氧化物區58可保護此些介面區域免於形成後續之接觸插栓(未顯示)時受到不期望之蝕刻情形，因而可幫助降低於介面區內漏電流的發生。於後續製程步驟中，移除了硬罩幕層106與206。可接著形成如矽化物區、接觸插栓、層間介電層、金屬層及相似物等額外構件。
如第10圖所示，包括了源極區56A與汲極區56B之 此些源極/汲極區56可具有相同於通道區42之導電特性並可耦 接通道區42。源極區56A與汲極區56B為頂閘極53更相分隔，頂電極53具有相反於源極/汲極區56之導電特性。可透過P型接觸區36與P型井區32而啟動底閘極28。舉例來說，可藉由施加一電壓至P型接觸區36處而於底閘極28處施加此電壓。
可使用如第10圖所示結構以形成如接面場效電晶 體裝置(JFET device)、變容器(varactors)、電阻(resistors)、雙極接面電晶體(BJT)、二極體或相似物等之多種積體電路裝置。由於此些裝置之形成製程共享了相同步驟，因此可降低製造成本。第11-15圖顯示了採用如第10圖所示結構所形成之裝置之數個範例。如第11-15圖所示之裝置的形成可啟始於如第10圖所示之結構，除了所採用之包括接觸插栓、金屬導線、介層物以及相似物等電性連結物的實施情形可為不同的，進而使得如第11-15圖所示之最終裝置為不同的。於第11-15圖內所示之數個電性連結物係採用線段(line)表示。
請參照第11圖，形成了一接面場效電晶體 (JFET)220，且其包括了一源極區56A、一汲極區56B、一頂閘極53與一底閘極28。通道區42係藉由頂閘極53與底閘極52所控制。藉由調整施加於頂閘極53與底閘極52之電壓VG1與VG2，可藉由形成於頂閘極53與通道區42之間的空乏區以及形成於底閘極28與通道區42之間的空乏區以開啟(turn on)或夾止(pinch off)通道區42內之通道。於圖式中繪室了流過通道之電流I。雖然未顯示，可於頂閘極53與底閘極28處耦接一電壓源，藉以提供此些電壓VG1與VG2。
請參照第12圖，形成了數個變容器(varactors) 302、304、306。舉例來說，可短接源極區56A與汲極區56B。因此，可於頂閘極53與通道區42之間形成一變容器302，其中此些源極/汲極區56與通道區42係作為一電容電極，而頂閘極53係作為另一電容電極。於底閘極28/P型井區32與通道區42之間則形成有數個變容器304，其中源極/汲極區56與通道區42係作為一電容電極，而底閘極28或P型井區32係作為另一電容電極。再者，底閘極28/P型井區32亦可形成具有深N型井區24之變容器306，其中接觸區49係作為存取(access)此變容器306之用。
請參照第13圖，形成了電阻(resistor)402及/或 404。舉例來說，通道區42形成了電阻402，其係耦接於源極區56A與汲極區56B。再者，底電極28亦可形成電阻404，其係耦接於分隔之兩P型接觸區36。然而，於此些實施例中，連結於電阻404之兩端之此些P型井區302為相分隔之數個P型井區而非前述之一環狀P型井區。再者，連結於電阻404之兩端之P型接觸區36亦為分隔之P型井區而非一環狀P型井區。
請參照第14圖，形成了數個二極體502、504與 506。二極體502係形成於頂閘極53與通道區42之間，其中源極/汲極區56可做為陰極接觸區(cathode pickup)。二極體504係形成於底電極28與通道區42之間，其中源極/汲極區56係作為一陰極接觸區，而P型井區接觸區36係作為陽極接觸區(anode pickup)。二極體506係形成於底閘極28與深N型井區24之間，其中P型接觸區36可做為一陽極接觸區，而深N型井區接觸區49可做為一陰極接觸區。
請參照第15圖，形成了一PNP雙極接面電晶體 (PNP BJT)602，其中通道區42係作為一基極(base)，而源極/汲極區56係作為基極接觸區(base pickup)。頂閘極53與底閘極28之一係作為此PNP雙極接面電晶體602之一射極(emitter)，而其另一則作為一集極(collector)。亦可形成有NPN雙極接面電晶體(NPN BJT)604，其中P型井區32與底閘極28係作為一基極。 源極/汲極區56係作為射極與集極其中之一者，而深N型井區24係作為射極與集極其中之另一者。
第16-23圖顯示了如第10-15圖所示積體電路結構 之佈局的數個範例。值得注意的是，實際上此些積體電路的佈局存在有更多的變化情形，而非以此些圖示情形而加以限定本發明之範疇。於第16-23圖之內，通道區42與底閘極28係採用虛線標示。
請參照第16與17圖，顯示了數個非對稱佈局 (asymmetric layout)情形，具有介於汲極區56B與頂閘極53間之一間距S1不同於介於源極區56A與頂閘極53間之一間距S2。頂閘極53與P型井區接觸區36之間為斷開的，且因此與底閘極28為斷開的，雖然頂閘極53於其他實施例中可連結於一P型接觸區36，如第18-19圖所示。請參照第16圖，形成有一頂閘極53、一源極區56A與一汲極區56B。請參照第17圖，則形成有兩頂閘極53、兩源極區56A與一汲極區56B。
請參照第18與19圖，顯示了數個對稱佈局情形， 具有介於汲極區56B與頂閘極53間之間距S1相同於介於源極區56A與頂閘極53間之間距S2。於此些實施例中，頂閘極53係連 結於P型井區接觸區36，且因此其連結於底閘極28，雖然於其他實施例中頂閘極53可斷開於P型接觸區36，如第16-17圖所示。請參照第18圖，形成有一頂閘極53、一源極區56A與一汲極區56B。請參照第19圖，形成有兩頂閘極53、兩源極區56A與一汲極區56B。
於第20-23圖中，頂閘極53、源極區56A、與P型井 區接觸區36分別形成了環繞汲極區56B之一環狀物，且具有環繞內部環狀物之外部環狀物之實施情形。第20圖顯示了一對稱結構，具有介於汲極區56B與頂閘極53間之間距S1大體相同於介於源極區56A與頂閘極53間之間距S2。第21圖顯示了一非對稱結構，其具有介於汲極區56B與頂閘極53間之間距S1不同於介於源極區56A與頂閘極53間之間距S2。第22圖顯示了介由數個淺溝槽隔離物區22所相分隔之數個汲極區56B。此些汲極區56B可經過內部連結以做為一單一汲極區，或互為斷開的以內部連結於不同之電壓與節點。第23圖顯示了一雙重閘結構(dual gate structure)，其中兩頂閘極53A與53B處可施加不同電壓及/或內部連結於不同之節點。此兩頂閘極53A與53B可影響各別之積體電路結構的操作。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可作更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10‧‧‧晶圓
20‧‧‧基板
22‧‧‧淺溝槽隔離區
24‧‧‧深N型井區
28‧‧‧埋設井區
32‧‧‧P型井區
36‧‧‧P型接觸區
42‧‧‧通道區
49‧‧‧深N型井區接觸區
53‧‧‧頂閘極
56‧‧‧源極/汲極區
56A‧‧‧源極區
56B‧‧‧汲極區
58‧‧‧電阻保護氧化物區
100‧‧‧N型金氧半導體裝置
106‧‧‧硬罩幕層
110‧‧‧閘堆疊物
116‧‧‧源極/汲極區
200‧‧‧P型金氧半導體裝置
206‧‧‧硬罩幕層
210‧‧‧閘堆疊物
216‧‧‧源極/汲極區

Claims (12)

  1. 一種積體電路裝置之製造方法，包括：形成具有一第一導電類型之一深井區於一基板之內；佈植該深井區之一部，以形成一第一閘極；佈植該深井區，以形成一井區，其中該井區與該第一閘極具有相反於該第一導電類型之一第二導電類型，且其中該深井區包括連結於該第一閘極之一端之一部；施行一離子佈植，形成一通道區於該第一閘極之上，其中該通道區具有該第一導電類型；佈植覆蓋該通道區之該深井區之一部，以形成具有該第二導電類型之一第二閘極；以及施行一第一源極/汲極佈植，以形成位於該第二閘極相對側之一第一源極區與一第二汲極區，其中該第一源極區與該第一汲極區具有該第一導電類型並連結於該通道區，而其中該第一源極區與該第一汲極區係覆蓋該通道區與該第一閘極。
  2. 如申請專利範圍第1項所述之積體電路裝置之製造方法，於該第一源極/汲極佈植之後，更包括形成用於一金氧半導體裝置之一閘堆疊物於該基板之上。
  3. 如申請專利範圍第2項所述之積體電路裝置之製造方法，於形成該閘堆疊物之後，更包括施行一第二源極/汲極佈植，以形成用於該金氧半導體裝置之數個源極/汲極區，其中該第一源極區與第一汲極區於該第二源極/汲極佈植中再次受到佈植。
  4. 一種積體電路裝置之製造方法，包括：形成具有一第一導電類型之一深井區於一基板內；佈植該深井區之一部，以形成一底閘極；佈植該深井區，以形成自該基板之一頂面延伸至該底閘極之一環狀井區，其中該環狀井區與該底閘極具有相反於該第一導電類型之一第二導電類型，且其中該環狀井區環繞該底閘極；佈植覆蓋與接觸該底閘極區之該深井區之一部，以形成具有該第一導電類型之一通道區；佈植覆蓋該通道區之該深井區之一部，以形成具有該第二導電類型之一頂閘極；施行一第一源極/汲極佈植，以形成位於該頂閘極之相對側之一第一源極區與一第二汲極區，其中該第一源極區與該第一汲極區具有該第一導電類型並連結於該通道區，而其中該第一源極區與該第一汲極區係覆蓋該通道區與該底閘極；於該第一源極/汲極佈植之後，形成一金氧半導體裝置之一閘堆疊物於該基板之上；以及於形成該閘堆疊物之後，施行一第二源極/汲極佈植，以形成該金氧半導體裝置之一第二源極區與一第二汲極區。
  5. 如申請專利範圍第4項所述之積體電路裝置之製造方法，其中該通道區與該底閘極係採用同一微影光罩所佈植形成。
  6. 一種積體電路裝置，包括：一第一導電類型之一深井區，位於一基板內； 一底閘極，位於該深井區內；一井區，自該基板之一頂面延伸至該底閘極，其中該井區與該底閘極具有相反於該第一導電類型之一第二導電類型；一通道區，具有該第一導電類型，覆蓋與接觸該底閘極區；一頂閘極，具有該第二導電類型，覆蓋該通道區且與該通道區形成了一P-N接面；以及一源極區與一汲極區，位於該頂閘極之相對側，其中該源極區與該汲極區具有該第一導電類型並連結於該通道區，且其中該源極區與該汲極區覆蓋了該通道區與該底閘極。
  7. 如申請專利範圍第6項所述之積體電路裝置，其中該井區形成了環繞該通道區、該頂閘極、該源極區與該汲極區之一環狀物。
  8. 如申請專利範圍第6項所述之積體電路裝置，其中該頂閘極、該井區、該源極區、該汲極區與該底閘極形成了一接面場效電晶體，而該其中該頂電極與該底電極係用以夾止該通道區。
  9. 如申請專利範圍第6項所述之積體電路裝置，更包括數個電性連結物，電性連結於該頂閘極、該井區、該源極區、該汲極區與該底閘極，以形成一變容器，該變容器具有內部連結之該源極區與汲極區以形成該變容器之一電容電極。
  10. 如申請專利範圍第6項所述之積體電路裝置，更包括數個電性連結物，電性連結於該頂閘極、該井區、該源極區、該汲極區與該底閘極，以形成一電阻，該電阻具有形成了該 電阻之該底閘極或該通道區。
  11. 如申請專利範圍第6項所述之積體電路裝置，更包括數個電性連結物，電性連結於該頂閘極、該井區、該源極區、該汲極區、與該底閘極，以形成一二極體，該二極體具有作為一陰極或一陽極之一之該通道區以及做為該陰極或該陽極之另一之頂閘極。
  12. 如申請專利範圍第6項所述之積體電路裝置，更包括數個電性連結物，電性連結於該頂閘極、該井區、該源極區、該汲極區與該底閘極，以形成一雙極接面電晶體。
TW102120060A 2012-06-29 2013-06-06 積體電路裝置及其製造方法 TWI542005B (zh)

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