TW201351486A - 二極體、雙極接面電晶體及於鰭型場效電晶體裝置內二極體之製造方法 - Google Patents

二極體、雙極接面電晶體及於鰭型場效電晶體裝置內二極體之製造方法 Download PDF

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TW201351486A
TW201351486A TW102118581A TW102118581A TW201351486A TW 201351486 A TW201351486 A TW 201351486A TW 102118581 A TW102118581 A TW 102118581A TW 102118581 A TW102118581 A TW 102118581A TW 201351486 A TW201351486 A TW 201351486A
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Chia-Hsin Hu
Sun-Jay Chang
Jaw-Juinn Horng
Chung-Hui Chen
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Taiwan Semiconductor Mfg
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    • H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L27/0814—Diodes only

Abstract

本發明揭示了利用鰭型場效電晶體製程之多個製程步驟以於包括場效電晶體之積體電路裝置內形成二極體與雙極接面電晶體。上述二極體或雙極接面電晶體包括具有不同深度之N型井區之一隔離鰭區與一鰭陣列區，以及鰭陣列區內之一部內的一P型井區環繞隔離鰭區內之該N型井區。用於二極體或雙極接面電晶體之此些N型井區與P型井區係與鰭型場效電晶體之N型井區與P型井區同時佈值形成。

Description

二極體、雙極接面電晶體及於鰭型場效電晶體裝置內二極體之製造方法
本發明係關於積體電路裝置，且特別是關於半導體裝置內具鰭型場效電晶體(FinFET)之二極體結構及其製造方法。
於快速演進之半導體製造工業中，於眾多邏輯及其他應用中使用了互補型金氧半導體場效電晶體(CMOS FinFET)，並將之整合成為多種不同型態之半導體裝置。鰭型場效電晶體裝置包括了多個半導體鰭狀物，其為電晶體之通道區以及源極/汲極區所形成之處。閘極係形成於此些半導體鰭狀物之上並沿著此些半導體鰭狀物之一部的側面形成。相較於具有相同裝置面積之一平面型電晶體而言，於一鰭型場效電晶體內之通道區與源極/汲極區之的表面積增加情形形成了對於半導體裝置之較快、較為可靠與較佳控制等情形。
具有互補型金氧半導體鰭型場效電晶體之積體電路裝置亦需要其他半導體結構以及電晶體，例如二極體(diodes)與雙極接面電晶體(BJT)。此些其他之半導體結構與電晶體係採用相同材料與製程，以於形成鰭型場效電晶體時同時沿著於 其側邊上形成。於熱感測器應用之一範例中，二極體採用磊晶成長於介於數個隔離元件間之N型摻雜矽上之一P型接面之矽鍺以及跨過該P型接面之隔離元件之一N型接面碳化矽。可採用共享一N接面之上述兩二極體以形成一NPN型雙極接面電晶體(NPN BJT)。
二極體與雙極接面電晶體結構可採用相同製程而沿著鰭型場效電晶體之側邊形成，上述製程採用了形成鰭型場效電晶體之鰭狀物結構，故需持續地探討如何減少額外製程步驟並具有較佳之電性特性。
依據本發明之不同目的，本發明揭示了新穎之一種二極體或雙極接面電晶體，其可利用鰭型場效電晶體製程所形成而避免了額外的製造步驟。
上述二極體包括一種半導體基板，具有位於一隔離鰭區內之複數個鰭狀物以及位於一鰭陣列區內之複數個鰭陣列物；一N型井區，位於該隔離鰭區內，具有一N型井區深度；一P型井區，位於該隔離鰭區內，且位於該N型井區下方；以及一P型井區，位於該鰭陣列區內，具有一P型井區深度大於該N型井區深度，且接觸該隔離鰭區內之該P型井區。該隔離鰭區內之一鰭間距係大於約0.3微米。位於該鰭陣列區內之一陣列內鰭間距係少於約50奈米。
上述雙極接面電晶體包括一半導體基板，具有位於一隔離鰭區內之複數個鰭狀物以及位於一鰭陣列區內之複數個鰭陣列物；複數個淺溝槽隔離構件，橫向地環繞該隔離鰭 區內之該些鰭狀物；一N型井區，位於該隔離鰭區內，部份地位於該些淺溝槽隔離構件之下；一P型井區，位於該隔離鰭區內，位於該N型井區之下方並具有至少35奈米之一最小厚度；一P型井區，位於該鰭陣列區內，具有大於該N型井區深度之一P型井區深度，且接觸於該隔離鰭區內之該P型井區；一或多個淺溝槽隔離構件，位於該鰭陣列區內之該些鰭陣列物之間；一N型井區，橫向地環繞該鰭陣列區內之該P型井區；以及一深N型井區，位於該鰭陣列區內之該P型井區與該N型井區之下，並接觸該鰭陣列區內之該N型井區，其中位於該隔離鰭區內之該些淺溝槽隔離物具有大於位於該鰭陣列區內之該些淺溝槽隔離物深度之一深度。
依據本發明之其他目的，本發明揭示了一種於鰭型場效電晶體裝置內二極體之製造方法，包括：提供一半導體基板；形成具有鰭圖案之一硬罩幕層，該鰭圖案包括具有低鰭密度之一隔離鰭區、具有較高鰭密度之一鰭陣列物區、以及一鰭型場效電晶體區；使用該鰭圖案，於該半導體基板內蝕刻形成複數個鰭狀物；沉積一介電材料於該半導體基板上，以填入該些鰭狀物間之空間；平坦化該半導體基板，露出該硬罩幕層；佈植一P型摻質至該鰭陣列物區內以及部分之該鰭型場效電晶體區內，以形成複數個P型井區；佈植一N型摻質至該隔離鰭區、環繞該P型井區之該鰭陣列物區之一部以及部分之該鰭型場效電晶體區內，以形成複數個N型井區；以及回火該半導體基板，其中該隔離鰭區內之該N型井區以及該鰭陣列物區內之該部內之該N型井區具有不同深度。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉一較佳實施例，並配合所附的圖式，作詳細說明如下。
100‧‧‧雙極接面電晶體/二極體
101‧‧‧矽基板
102‧‧‧線段
103‧‧‧深N型井區
104‧‧‧鰭狀物
105‧‧‧N型井區
106‧‧‧隔離鰭區
107、107A、107B‧‧‧P型井區
108、120‧‧‧鰭狀物
109‧‧‧N型井區
110‧‧‧鰭陣列物
111‧‧‧深度
112‧‧‧鰭陣列區
113‧‧‧寬度
114‧‧‧方框
115‧‧‧寬度
116‧‧‧P型井區
117‧‧‧淺溝槽隔離構件
118‧‧‧N型井區
121‧‧‧淺溝槽隔離構件
122‧‧‧切線
123‧‧‧虛線
201‧‧‧鰭高度
203‧‧‧陣列物內鰭高度
205‧‧‧陣列物內鰭高度
300‧‧‧流程圖
301、303、305、307、309、311、312、313、314、315、317、319、321、323‧‧‧操作
401‧‧‧光阻圖案
402‧‧‧隔離鰭區
403‧‧‧光阻圖案
404‧‧‧鰭陣列區
405‧‧‧光阻圖案
406‧‧‧罩幕圖案
407‧‧‧半導體基板
409‧‧‧黏著層
411‧‧‧硬罩幕層
412‧‧‧溝槽
413‧‧‧深度
414‧‧‧陣列內溝槽
415‧‧‧深度
416‧‧‧陣列內溝槽
417‧‧‧深度
421‧‧‧鰭狀物
423‧‧‧鰭狀物
425‧‧‧介電材料/隔離之淺溝槽格離物
427‧‧‧介電材料/陣列內之淺溝槽隔離物
429‧‧‧介電材料/陣列內之淺溝槽隔離物
431‧‧‧摻質
433‧‧‧深N型井區
435‧‧‧基板之剩餘部份
437‧‧‧光阻層
439‧‧‧光阻層
441‧‧‧P型井區
443‧‧‧N型井區
445‧‧‧佈值
447‧‧‧佈值
449‧‧‧高能量
451‧‧‧P型井區
453‧‧‧N型井區
455‧‧‧N型井區
457‧‧‧N型井區下方之區域
459‧‧‧P型井區
461‧‧‧上蓋物
463‧‧‧上蓋物
471‧‧‧正極接觸物/基極接觸物
473‧‧‧負極接觸物/射極接觸物
475‧‧‧集極接觸物
500‧‧‧二極體/雙極接面電晶體
501‧‧‧接觸物
503‧‧‧接觸物
505‧‧‧接觸物
511‧‧‧N型井區
521‧‧‧深N型井區
第1A圖為一上視圖，顯示了依據本發明之一實施例之採用鰭型場效電晶體製程所形成之一部分製造的雙極接面電晶體(BJT)；第1B圖為一剖面圖，顯示了依據本發明之一實施例內之如第1A圖內所示之部分製造的雙極接面電晶體；第2A圖為一剖面圖，顯示了依據本發明之一實施例之一種隔離鰭狀區；第2B圖為一剖面圖，顯示了依據本發明之一實施例之一種鰭陣列區；第3圖為一流程圖，顯示了依據本發明之一實施例之一種二極體與雙極接面電晶體之製造方法；第4A-4L圖為一系列剖面圖，顯示了依據本發明之多個實施例內之如第3圖所示方法的多個步驟；第5圖為一立體圖，顯示了依據本發明之一實施例之一種二極體或雙極接面電晶體。
可以理解的是，於下文中提供了用於施行本發明之不同特徵之多個不同實施例，或範例。基於簡化本發明之目的，以下描述了元件與設置情形之特定範例。然而，此些元件 與設置情形僅作為範例之用而非用於限制本發明。此外，本發明於不同實施例中可能重複使用標號及/或文字。如此之重複情形係基於簡化與清楚之目的，而非用於限定不同實施例及/或討論形態內的相對關係。再者，於描述中關於於一第二元件之上或上之第一元件的形成可包括了第一元件與第二元件係為直接接觸之實施情形，且亦包括了於第一元件與第二元件之間包括了額外元件之實施情形，因而使得第一元件與第二元件之間並未直接接觸。基於簡化與清楚之目的，不同元件將參照不同尺寸而簡單地繪示。
於下文中將描述鰭型場效電晶體(FinFET)及其製程之基本概念，以描述二極體與雙極接面電晶體(BJT)結構及其製程。鰭型場效電晶體採用矽之大體長方形鰭結構。此常方形鰭結構為長且窄的，具有一寬側與一窄側。此矽鰭可藉由圖案化罩幕層而蝕刻一塊狀矽基板所形成。可沉積如淺溝槽隔離物(STI)之介電材料以填滿介於鰭間之空隙。於後續製程中，可露出介於淺溝槽隔離物間之鰭之一頂部。鰭可藉由N型摻質或P型摻質的佈植而於源極/汲極區以及通道區內形成N型井區或P型井區。閘介電層與閘電極層可沉積於鰭與淺溝槽隔離物之上，並經過圖案化形成了位於鰭之通道區上之閘堆疊物。閘電極層係形成於閘介電層之上且可藉由如摻雜多晶矽、金屬或金屬氮化物之導電材料所形成。接著選擇地摻雜未位於閘堆疊物下之鰭部以形成輕度摻雜汲極與源極區域。此些區域可藉由離子佈植或介由離子摻雜所形成，摻質矽沉積於鰭之上並經過回火。
依據本發明之多個實施例，二極體或雙極接面電晶體包括一隔離鰭區(isolated fin area)與一鰭陣列區(fin array area)，其包括具有不同深度之N型井區以及位於鰭陣列區內且環繞位於隔離鰭區內之N型井區之一P型井區。此些二極體與雙極接面電晶體之N型井區與P型井區係與鰭型場效電晶體之N型井區與P型井區同時佈植而成，因而避免了用於形成二極體與雙極接面電晶體之額外製程步驟。藉由利用鰭密度相關的蝕刻局部負載效應(localized loading effect)，鄰近不同鰭密度區域內之鰭的淺溝槽隔離元件形成並具有不同深度。如此之淺溝槽隔離物的不同深度反倒是達成了摻雜劑量的控制，因而不需要額外光罩步驟以形成具有不同深度之N型井區。
第1A圖為一上視圖，顯示了採用一鰭型場效電晶體製程所形成之部分製作之一種雙極接面電晶體(BJT)或二極體(diode)100。第1B圖為一示意圖，顯示了如第1A圖內雙極接面電晶體100沿著線段102之切面情形。此雙極接面電晶體100包括分隔成為兩個區域之數個鰭狀物(fin)。隔離鰭區(isolated fin area)106包括隔離之數個鰭狀物(fin)104，而鰭陣列區(fin array area)112則包括了群聚成為數個鰭陣列物(fin array)110之鰭狀物108或120。如圖所示，隔離鰭區106包括了三個鰭狀物。依據多個實施例，隔離鰭區包括至少兩個或至少三個之鰭狀物。位於隔離鰭區內之鰭狀物間距大於約0.3微米。介於鄰近之隔離的鰭狀物之間的距離可約為0.3-1.2微米。於部分實施例中，此些隔離之鰭狀物可包括2行或更多行之隔離的鰭狀物。
如第1A圖所示，鰭陣列物110包括了每陣列物中之兩鰭狀物，但於每陣列物中可使用更多之鰭狀物。舉例來說，一鰭陣列物可包括3-5個鰭狀物。每一陣列物內之鰭狀物的數量可基於所需要之淺溝槽隔離物厚度而定，以達到期望之佈植深度。相較於隔離鰭區106，鰭陣列區112具有較高之鰭密度(fin density)。陣列物內鰭間距，即於一陣列物內介於相鄰鰭狀物中心間之一距離，係少於約50奈米。介於鰭陣列物之間或介於鄰近陣列物之最鄰近鰭狀物間之距離可大於約60奈米。於第1A圖內雖顯示了位於雙極接面電晶體100之中心處之隔離鰭區106，然而隔離鰭區域106亦可位於非中心處或位於雙極接面電晶體100之一邊緣處。鰭陣列區112則可為一方框114而分隔成為兩個區域，其一為具有數個鰭狀物120之P型井區116，而另一為具有數個鰭狀物108之N型井區118。
第1B圖內顯示了隔離鰭區106與鰭陣列區112。第1B圖顯示了形成於一矽基板101上之一雙極接面電晶體100，矽基板101為一P型基板。於P型基板101內形成有一深N型井區103以及一N型井區105作為隔離P型井區107以降低基板雜訊問題。虛線123顯示了N型井區的連結以及環繞P型井區107之情形。N型井區105橫向地環繞了P型井區107。P型井區107包括了兩個區域107A與107B。P型井區107A係形成於鰭陣列區112之內並環繞了N型井區109。N型井區109係位於隔離鰭區106之內。P型井區107b係位於N型井區109與深N型井區103之間並鄰近P型井區107A。
依據多個實施例，P型井區107B具有大於約35 奈米之一深度111。介於N型井區109與深N型井區103間之如P型井區107B之P型區避免了於操作時貫穿情形(punch-through)，其可使得二極體或雙極接面電晶體失效。N型井區109之頂部係為分隔之數個淺溝槽隔離物117所環繞，且具有相同於鰭狀物104長度之一寬度115。N型井區109之一底部具有一寬度113，其大於N型井區109之頂部的寬度115。此寬度113係為N型井區109之最大值，且為約0.2-5微米。N型井區109之底部具有一厚度119，其可介於約35-100奈米。此些淺溝槽隔離構件121於鰭陣列區112內分隔了數行之鰭狀物且亦分隔了鰭陣列區112內之P型井區116與N型井區118。隔離之淺溝槽隔離構件117較淺溝槽隔離構件121具有較大之一厚度或深度，其可由局部蝕刻負載效應(localized etch loading effects)所形成且可更藉由圖案化蝕刻而加強。當此些淺溝槽隔離構件121與117具有不同的厚度時，此些鰭狀物108、120與104具有相同之整體高度。當採用圖案化蝕刻以加強此些淺溝槽隔離物之厚度時，此些鰭狀物108、120與104的露出部可具有不同高度。
於鰭狀物形成技術中，局部蝕刻負載效應於較低鰭密度區域內造成了較多蝕刻情形。於一範例中，由於窄構件內質量傳輸因素便具有較低蝕刻劑濃度，因而限制了於高密度區域內之蝕刻率。於低密度區域之內，較高的蝕刻劑濃度並不會限制蝕刻速率，因此便移除了較多的矽。於如第2A與2B圖所圖示之測試中，於如第2A圖所示之隔離區中可形成具有170奈米的一鰭高度201，以及於如第2B圖所示之具有兩鰭狀 物之數個陣列物之一鰭陣列區內形成具有100奈米之一陣列物內鰭高度205。當此陣列物內鰭高度205遠短於隔離之鰭高度201時，於整個陣列物內鰭高度203約為165奈米，其約相同於隔離之鰭高度201。可藉由調整製程改變介於鰭間的距離以及於鰭陣列中之鰭狀物的數量以達成不同的高度比例，例如鰭高度201：205或201：203或203：205間的比例。
依據本發明之多個實施例，二極體或雙極接面電晶體係採用一製程所形成，例如為第3圖內流程圖300內所示之一方法。第3圖將與第4A-4L圖一併討論，第4A-4L圖示了對應於如第3圖內之一或多個操作之多個部分製造之剖面圖。如第4A-4L圖之剖面圖為沿著如第1A圖內切線122之平面的數個部分。第1A圖內之切線122係垂直於切線102，而切線104為形成了如第1B圖內所示之一剖面圖。第4A-4L圖之平面包括了此些鰭狀物的窄側，而不是如第1B圖所示之寬側。如第4A-4L圖內之各圖式中，包括了具有一P型井區以及一N型井區之一隔離鰭區、一鰭陣列區。於操作301中，提供一半導體基板。依據不同實施例，半導體基板可為一矽晶圓、一矽鍺晶圓、或一絕緣層上覆矽(SOI)晶圓。此半導體基板可經過摻雜。依據部分實施例，半導體基板可為一P型矽基板。可於半導體基板上施行多個操作，而於部分製造裝態中具有多個膜層之半導體基板係稱為一工件(workpiece)。
於第3圖所示之操作303中，形成包括一隔離鰭區、一鰭陣列區與一鰭型場效電晶體區之一鰭圖案之一硬罩幕層。隔離鰭區具有低鰭密度。鰭陣列區較隔離鰭區具有較高之 鰭密度。鰭型場效電晶體區為鰭型場效電晶體所形成之處且通常包括高鰭密度之數個鰭狀物。第4A圖顯示了具有一隔離鰭區402與一鰭陣列區404之一半導體基板407。於鰭陣列區404內，鰭狀物可群聚成為兩群之鰭陣列物。於部分實施例中，鰭狀物可群聚成為兩群以上之鰭陣列物。於每一陣列物內之鰭狀物的間距係少於鰭陣列物之間的空間。隔離鰭區402內之鰭狀物的間距至少且通常大於鰭陣列之間的距離。可先沉積一黏著層409於半導體基板上，並接著形成一硬罩幕層411。黏著層409可為氧化矽層，其可極佳地黏著半導體基板407與硬罩幕層411，硬罩幕層411可為氮化矽層或氧化矽層。於部分實施例中，於硬罩幕層之上沉積一光阻層且使之曝光形成前述鰭圖案，例如光阻圖案401、403與405。接著蝕刻硬罩幕層411以轉移此些鰭圖案至硬罩幕層411之內。於其他實施例中，罩幕圖案406可為沉積並環繞被移除之光阻材料之作為間隔物之另一硬罩幕層(未顯示)。
請繼續參照第3圖，於操作305中，採用此鰭圖案以於半導體基板內蝕刻形成了數個鰭狀物。第4B圖顯示了如此蝕刻結果。此蝕刻製程消耗了至少部分之罩幕圖案406，且僅黏著層409與硬罩幕層411殘留於此些鰭狀物之上。於隔離鰭區402內，形成有具有位於其間之一溝槽412之數個鰭狀物421。溝槽412具有一深度413。於鰭陣列區404內，此些鰭狀物423係形成兩鰭狀物之數個陣列物。由於局部負載效應，介於此些鰭狀物間之溝槽具有不同之深度。陣列內溝槽414具有深度415。陣列內溝槽416具有深度417。上述之溝槽深 度413與417係大於陣列內溝槽深度415。如前所述，可調整此蝕刻製程與鰭圖案尺寸以形成溝槽深度間之較大或較小差異情形。
於第3圖內之操作307中，於基板上沉積一介電材料以填滿介於鰭狀物之間的空間。於部分實施例中，介電材料為使用包括化學氣相沉積、熱氧化沉積、或原子層沉積之常用製程所沉積之氧化矽。本領域之通常技術者可選擇一沉積製程，其可有效地填滿介於鰭狀物間的空間。於介於鰭狀物間具有高深寬比之空間之至少一範例中，可使用一高密度電漿加強型化學氣相沉積(HDP CVD)製程。介電材料填滿了介於鰭狀物間的空間並覆蓋了鰭狀物之頂部，以確保完全填入情形。
請參照第3圖內之下一操作309，此工件經過平坦化，以移除高於鰭狀物之多餘介電材料並露出了硬罩幕層，例如第4C圖內之硬罩幕層411。此平坦化製程牽涉了對於工件表面的化學機械研磨，且可額外地或取而代之牽涉到對於工件的蝕刻。第4C圖繪示了經平坦化後之部分製造的雙極接面電晶體之剖面情形。於隔離鰭區402中，介電材料425填滿了隔離之鰭結構間的空間，上述鰭結構包括了鰭狀物421、黏著層409與硬罩幕層411。介電材料425係稱為隔離之淺溝槽隔離物425。於鰭陣列區404內，介電材料429則填入於介於鰭陣列物405間的空間，鰭陣列物405包括了於圖示實施例中之兩個鰭狀物423、黏著層409與硬罩幕層411。介電材料429稱為陣列內淺溝槽隔離物429。於位於鰭陣列區404之一鰭陣列物405內之鰭結構之間，介電材料427係填入介於此些鰭結 構間之空間，其包括鰭狀物423、黏著層409與硬罩幕411。介電材料427亦稱為陣列內之淺溝槽隔離物。隔離之淺溝槽格離物425、陣列內之淺溝槽隔離物429與陣列內之淺溝槽隔離物427通稱為淺溝槽隔離構件。當隔離之淺溝槽隔離物425與陣列內之淺溝槽隔離物429具有相似厚度時，其厚度係大於陣列內之淺溝槽隔離物427之厚度。
請再次參照第3圖，於操作311中，移除鰭陣列區上介電材料之一部。第4D圖為一剖面圖，顯示了具有位於鰭陣列區404上之一部之介電材料(形成陣列內淺溝槽隔離物429與陣列內淺溝槽隔離物427)被移除之部分製造的雙極接面電晶體。此操作牽涉到首先遮蔽隔離鰭狀區402免於接觸一蝕刻製程，其可為乾蝕刻或濕蝕刻。於至少一實施例中，於部分製造之雙極接面電晶體上沉積與圖案化一光阻層，以露出鰭陣列區404。接著於一蝕刻製程中蝕刻此部分製造之雙極接面電晶體，並選擇地移除了位於硬罩幕材料411上之淺溝槽隔離物的材料。於下一操作施行之前，移除此光阻層。
於第3圖所示之操作312中，移除硬罩幕層。依據部份實施例，硬罩幕層為氮化矽、氮氧化矽或碳摻雜之氮化矽。可使用一蝕刻程序以選擇地移除位於淺溝槽隔離物上之通常使用氧化矽之硬罩幕材料。第4E圖為一剖面圖，顯示了此部份製造之雙極接面電晶體於移除硬罩幕層後之情形。在此，於半導體基板407上只殘留有具有鰭圖案之一黏著層409與淺溝槽隔離構件。
請再次參照第3圖，於操作313中，於半導體基 板內形成了一深N型井區。此深N型井區藉由於高能量下佈植如磷與砷之N型摻質於半導體基板之內所形成，進而於低於雙極接面電晶體之N型井區與P型井區之一深度處形成高摻質濃度。依據多個實施例，深N型井區位於鰭狀物之頂部下至少為250奈米，且可能為400-1600奈米。第4F圖繪示了形成深N型井區之製程與結果。將摻質431佈值進入了部份製造之雙極接面電晶體，以形成位於特定深度處之一深N型井區433。因此，第4A-4E圖所示之半導體基板407之一部便轉變成為此深N型井區433，而其餘部份435仍保持為P型導電性。半導體基板407之介於鰭狀物421/423與深N型井區433間之另一剩餘部份亦維持了P型導電性。
請再次參照第3圖，於下一操作314中，於鰭陣列區與鰭型場效電晶體區內之一部中佈值如硼之一P型摻質，以形成數個P型井區。如形成鰭型場效電晶體的相關討論中，係於鰭型場效電晶體之源極與汲極區內形成P型井區與N型井區。於形成鰭型場效電晶體內之P型井區之同時，亦可於部份製作之雙極接面電晶體內形成一P型井區，如第4G圖所示。可沈積光阻層437以遮蔽隔離鰭區402以及鰭陣列區404之一部，使之免於受到P型摻質之佈值445。光阻層437將鰭陣列區404分隔成為一P型井區441與一N型井區443。僅P型井區441暴露於P型摻質之佈值445之下。此佈值牽涉到較做為一P型基板部份407之劑量相對較高劑量之摻質，以形成一P型井區451，而最終摻質濃度的差異約為一或二個次方。P型井區451之深度可為約40-240奈米。於P型摻質之佈值 445後，便移除了光阻層437。
請參照第3圖，於下一操作315中，佈值如磷之一N型摻質至鰭陣列區、隔離鰭區以及鰭型場效電晶體區之一部內，以形成N型井區。如形成鰭型場效電晶體的相關討論中，係於鰭型場效電晶體之源極與汲極區內形成P型井區與N型井區。於形成鰭型場效電晶體內之N型井區之同時，亦可於部份製作之雙極接面電晶體內形成N型井區，如第4H圖所示。可沈積一光阻層439以保護P型井區441免於受到N型摻質的佈值447。因此，於鰭陣列區404與隔離鰭區域402內之N型井區443係暴露於此N型摻質之佈值447中。相較於形成深N型井區433之劑量，此佈值牽涉到使用相對高劑量，以形成N型井區453與455。縱使N型井區453與455係暴露於相同之佈值製程中，仍可形成具有不同深度之N型井區。由於位於井區上的鰭狀物與材料膜層為相同的，N型井區453具有如P型井區451之相同深度，其約為40-240奈米深。N型井區453與P型井區451則相似於形成於鰭型場效電晶體區內之井區。另一方面，N型井區455具有一較少深度。由於離子佈值係於不同速率下穿透如淺溝槽隔離物與矽等不同材料，故具有不同厚度之淺溝槽隔離構件便可造成了相較於抵達N型井區453之抵達N型井區455之一不同摻質離子劑量。換句話說，相較於為陣列內之淺溝槽隔離物429以及陣列內之淺溝槽隔離物427所吸收之摻質離子，隔離之淺溝槽隔離物425吸收了較多之摻質離子。此些N型井區深度的差異情形可藉由淺溝槽隔離物材料的類型與數量以及佈值劑量與能量而得到控制。此些 N型井區的深度差異造成了一區域457具有低於相對沒有N型摻質之摻雜情形。於N型摻質之佈值447後，接著移除了光阻層439。
於下一操作317中，回火半導體基板。此回火活化了於操作313、314與315中佈值之不同摻質並促進了部份之此些摻質的聚集。由於位於N型井區455下方之區域457為輕度地摻雜有P型摻質，其P型摻質可能來自高度摻雜P型井區451。第4I圖為一剖面圖，顯示了此部份製造之雙極接面電晶體置於一高能量449下並於N型井區455之下形成一P型井區459之情形。於此回火中，來自於橫向地環繞了N型井區455之P型井區451之P型摻質遷移至於N型井區455下之區域，並形成了一連續且環繞之P型井區455，其包括了P型井區451與P型井區459。因此，P型井區459之摻質濃度係低於P型井區451之摻質濃度。
於此回火之前或之後，可蝕刻此些淺溝槽隔離構件，以露出鰭狀物之一部，如第4J圖所示。針對淺溝槽隔離物的蝕刻亦移除了位於鰭狀物上之黏著層409。於此淺溝槽隔離物的蝕刻之後，鰭狀物421與423之一頂部為露出的並位於淺溝槽隔離物之上，而鰭狀物421與423之一底部則埋入於淺溝槽隔離物之下。
請繼續參照第3圖，於操作319內，於此些鰭狀物之上磊晶成長矽鍺或碳化矽之上蓋物。如第4K圖所示，上蓋物461係成長於鰭狀物421之頂部，而上蓋物463係成長於鰭狀物423之頂部上，於具有高密度之鰭狀物423造成了每一 鰭陣列物的上蓋成長與聚合情形。此上蓋之特殊情形係依據成長條件以及露出之鰭狀物的數量而定。於部份實施例中，此些鰭狀物之上沈積一多晶矽材料，並圖案化之。
請參照第3圖，接著依照所形成之裝置為二極體或雙極接面電晶體而選擇操作321與323。操作321係形成了用於二極體之一正極接觸物(positive contact)以及一負極接觸物(negative contact)。第4L圖繪示了具有一正極接觸物473與一負極接觸物471之二極體。或者，可選擇操作423以形成一雙極接面電晶體之一基極接觸物(base contact)、一集極接觸物(collector contact)以及一射極接觸物(emitter contact)。如第4L圖所示，此雙極接面電晶體400包括了一基極接觸物471、一集極接觸物475與一射極接觸物473。
第5圖為一立體圖，顯示了依據本發明之多個實施例之二極體或雙極接面電晶體500。沿著x-z平面之剖面情形如第1B圖所示。沿著y-z平面之剖面情形如第4A-4L圖所示。當接觸物503與505為二極體之正極端與負極端時，接觸物501可接地以降低基板躁訊。接觸物501、N型井區511、深N型井區521形成了環繞了二極體之一N型摻雜外殼。為雙極接面電晶體500時，接觸物501為集極、接觸物503為基極以及接觸物505為射極。可使用更多之隔離情形以環繞整個雙極接面電晶體。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可作更動與潤飾，因此本發明之保護範圍當視 後附之申請專利範圍所界定者為準。
407‧‧‧半導體基板
421‧‧‧鰭狀物
423‧‧‧鰭狀物
433‧‧‧深N型井區
451‧‧‧P型井區
453‧‧‧N型井區
455‧‧‧N型井區
459‧‧‧P型井區

Claims (10)

  1. 一種二極體，包括：一種半導體基板，具有位於一隔離鰭區內之複數個鰭狀物以及位於一鰭陣列區內之複數個鰭陣列物；一N型井區，位於該隔離鰭區內，具有一N型井區深度；一P型井區，位於該隔離鰭區內，且位於該N型井區下方；以及一P型井區，位於該鰭陣列區內，具有一P型井區深度大於該N型井區深度，且接觸該隔離鰭區內之該P型井區，其中該隔離鰭區內之一鰭間距係大於約0.3微米，以及位於該鰭陣列區內之一陣列內鰭間距係少於約50奈米。
  2. 如申請專利範圍第1項所述之二極體，更包括：一深N型井區，位於該隔離鰭區與該鰭陣列區之該P型井區之下；以及至少一N型井區，橫向地環繞該鰭陣列區內之該P型井區。
  3. 如申請專利範圍第1項所述之二極體，其中於該鰭陣列區內之該些鰭陣列物分別具有兩個鰭狀物，以及更包括一或多個淺溝槽隔離構件，位於該鰭陣列區內之該些鰭陣列物之間。
  4. 一種雙極接面電晶體，包括：一半導體基板，具有位於一隔離鰭區內之複數個鰭狀物以及位於一鰭陣列區內之複數個鰭陣列物；複數個淺溝槽隔離構件，橫向地環繞該隔離鰭區內之該些鰭狀物； 一N型井區，位於該隔離鰭區內，部份地位於該些淺溝槽隔離構件之下；一P型井區，位於該隔離鰭區內，位於該N型井區之下方並具有至少35奈米之一最小厚度；一P型井區，位於該鰭陣列區內，具有大於該N型井區深度之一P型井區深度，且接觸於該隔離鰭區內之該P型井區；一或多個淺溝槽隔離構件，位於該鰭陣列區內之該些鰭陣列物之間；一N型井區，橫向地環繞該鰭陣列區內之該P型井區；以及一深N型井區，位於該鰭陣列區內之該P型井區與該N型井區之下，並接觸該鰭陣列區內之該N型井區，其中位於該隔離鰭區內之該些淺溝槽隔離物具有大於位於該鰭陣列區內之該些淺溝槽隔離物深度之一深度。
  5. 如申請專利範圍第4項所述之雙極接面電晶體，其中該隔離鰭區之該N型井區約位於該些淺溝槽隔離物構件下方約為35-105奈米處，而該隔離鰭區域內之該N型井區之一最大寬度約介於0.2-5微米。
  6. 一種於鰭型場效電晶體裝置內二極體之製造方法，包括：提供一半導體基板；形成具有鰭圖案之一硬罩幕層，該鰭圖案包括具有低鰭密度之一隔離鰭區、具有較高鰭密度之一鰭陣列物區、以及一鰭型場效電晶體區；使用該鰭圖案，於該半導體基板內蝕刻形成複數個鰭狀物；沉積一介電材料於該半導體基板上，以填入該些鰭狀物間 之空間；平坦化該半導體基板，露出該硬罩幕層；佈植一P型摻質至該鰭陣列物區內以及部分之該鰭型場效電晶體區內，以形成複數個P型井區；佈植一N型摻質至該隔離鰭區、環繞該P型井區之該鰭陣列物區之一部以及部分之該鰭型場效電晶體區內，以形成複數個N型井區；以及回火該半導體基板，其中該隔離鰭區內之該N型井區以及該鰭陣列物區內之該部內之該N型井區具有不同深度。
  7. 如申請專利範圍第6項所述之於鰭型場效電晶體裝置內二極體之製造方法，於平坦化該半導體基板後，更包括移除位於該鰭陣列物區上之該介電材料之一部。
  8. 如申請專利範圍第6項所述之於鰭型場效電晶體裝置內二極體之製造方法，更包括形成一深N型井區於該半導體基板內。
  9. 如申請專利範圍第6項所述之於鰭型場效電晶體裝置內二極體之製造方法，其中位於該隔離鰭區內之該N型井區與位於該鰭陣列物區內之該部之該N型井區具有至少為35奈米之深度差，而該鰭陣列物區具有少於約50微米之一陣列物內鰭狀物間距以及大於60奈米之一陣列間距離。
  10. 如申請專利範圍第6項所述之於鰭型場效電晶體裝置內二極體之製造方法，更包括：磊晶成長矽鍺或碳化矽之一上蓋物於該隔離鰭區內之該些鰭狀物上以及於該鰭陣列區內之該些鰭陣列物之上； 形成二極體之一正極接觸物於該鰭陣列物區內之該P型井區之該些鰭陣列物之上；以及形成該二極體之一負極接觸物於該隔離鰭區內之該鰭狀物之上。
TW102118581A 2012-06-12 2013-05-27 二極體、雙極接面電晶體及於鰭型場效電晶體裝置內二極體之製造方法 TWI500075B (zh)

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