TW201340274A - 半導體封裝 - Google Patents
半導體封裝 Download PDFInfo
- Publication number
- TW201340274A TW201340274A TW102110822A TW102110822A TW201340274A TW 201340274 A TW201340274 A TW 201340274A TW 102110822 A TW102110822 A TW 102110822A TW 102110822 A TW102110822 A TW 102110822A TW 201340274 A TW201340274 A TW 201340274A
- Authority
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- Taiwan
- Prior art keywords
- semiconductor package
- wire
- conductive
- metal pad
- wafer
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 145
- 229910052751 metal Inorganic materials 0.000 claims abstract description 120
- 239000002184 metal Substances 0.000 claims abstract description 120
- 239000000758 substrate Substances 0.000 claims abstract description 86
- 230000008878 coupling Effects 0.000 claims abstract 2
- 238000010168 coupling process Methods 0.000 claims abstract 2
- 238000005859 coupling reaction Methods 0.000 claims abstract 2
- 239000010410 layer Substances 0.000 claims description 121
- 229910000679 solder Inorganic materials 0.000 claims description 48
- 239000000463 material Substances 0.000 claims description 22
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 20
- 229910052802 copper Inorganic materials 0.000 claims description 20
- 239000010949 copper Substances 0.000 claims description 20
- 239000011241 protective layer Substances 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 8
- 239000002356 single layer Substances 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 description 78
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 238000004804 winding Methods 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 238000012536 packaging technology Methods 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 2
- 241000557258 Lathys Species 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 238000005272 metallurgy Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 229920003192 poly(bis maleimide) Polymers 0.000 description 2
- 229920002577 polybenzoxazole Polymers 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012778 molding material Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Abstract
本發明提供一種半導體封裝。上述半導體封裝包括一基板,具有一晶片貼附面;以及一晶片,藉由一導電柱狀凸塊固接於上述晶片貼附面上,其中上述晶片包括一金屬焊墊,電性耦接至上述導電柱狀凸塊,其中上述金屬焊墊具有一第一邊緣和垂直於上述第一邊緣的一第二邊緣,其中於一俯視圖中,上述第一邊緣的長度不等於上述第二邊緣的長度。
Description
本發明係關於一種半導體封裝,特別係關於一種高密度的覆晶封裝。
為了確保電子產品或通信設備的小型化和多功能性,會要求半導體封裝具有小尺寸,多針連接,高速和高功能。輸入/輸出(I/O)引腳數的增加再加上對高性能積體電路(IC)的需求增加,導致了覆晶封裝體的發展。
覆晶技術係使用芯片上凸塊以與例如一封裝基板的封裝介質互連。正面朝下的覆晶接合至封裝基板係經過最短的路徑。這些技術可以不僅適用於單一晶片封裝技術,也可以適用於更高層數或集成層數的封裝技術,在更高層數或集成層數的封裝技術中的封裝體更大,且這些技術可以適用於容納數個晶片的更複雜的基板,以形成較大的功能單元。使用一區域陣列的上述覆晶技術的優點為實現連接至元件的內連接結構具有更高的密度和使內連接結構對封裝體具有非常低的電感。然而,多功能晶片封裝因增加了輸入/輸出(I/O)連接數量會導致熱電特性問題,舉例來說,散熱問題、串音(crosstalk)、訊號傳輸延遲(Propagation Delay)或射頻(RF)電路的電磁干擾等問題。上述熱電特性問題會影響產品的可靠度和品質。
因此,在此技術領域中,有需要一種高密度的覆晶封裝,以改善上述缺點。
有鑑於此,本發明之目的在於提供改良式的半導體封裝,以提升覆晶封裝的內連接結構的密度。
本發明之一實施例係提供一種半導體封裝。上述半導體封裝包括一基板,具有一晶片貼附面。一晶片,藉由一導電柱狀凸塊固接於上述晶片貼附面上,其中上述晶片包括一金屬焊墊,電性耦接至上述導電柱狀凸塊,其中上述金屬焊墊具有一第一邊緣和垂直於上述第一邊緣的一第二邊緣,其中於一俯視圖中,上述第一邊緣的長度不等於上述第二邊緣的長度。
本發明之另一實施例係提供一種半導體封裝。上述半導體封裝包括一基板,具有一晶片貼附面。一晶片,藉由一導電柱狀凸塊固接於上述晶片貼附面上,其中上述晶片包括一金屬焊墊,電性耦接至上述導電柱狀凸塊,其中上述金屬焊墊具有沿一第一方向的一第一長度和沿一第二方向的一第二長度,其中於一俯視圖中,上述第一長度不等於上述第二長度,其中上述第一方向和上述第二方向之間的夾角大於0度且小於等於90度。
本發明之又一實施例係提供一種半導體封裝。上述半導體封裝包括一基板,具有一晶片貼附面。一晶片,藉由一導電柱狀凸塊固接於上述晶片貼附面上,其中上述晶片包括一金屬焊墊,電性耦接至上述導電柱狀凸塊,其中上述金屬焊
墊僅於上述俯視圖中具有二重旋轉對稱。
本發明之更一實施例係提供一種半導體封裝。上述半導體封裝包括一基板,具有一晶片貼附面。一晶片,固接於上述晶片貼附面上,上述晶片的一主動表面係面對上述基板。複數個導電柱狀凸塊的至少一個具有一凸塊寬度,上述凸塊寬度範圍可從實質上等於或大於例如位於上述基板的上述晶片貼附面上的上述導線的一線寬至小於上述導線的線寬的2.5倍。
本發明之又另一實施例係提供一種半導體封裝。上述半導體封裝包括一基板。一導線,設置於上述基板上。一導電柱狀凸塊,設置於上述導線上,其中上述導電柱狀凸塊耦接至一晶片。
本發明之更又另一實施例係提供一種半導體封裝。上述半導體封裝包括一基板。一第一導線,設置於上述基板上。一阻焊層,設置於上述基板上,上述阻焊層具有覆蓋上述第一導線的一部分之一延伸部分,其中該阻焊層的該延伸部分具有一垂直側壁,該垂直側壁凸出於與其相鄰的該第一導線的該部分的一側壁。用於傳遞訊號的一第二導線,設置於上述基板上。一導電柱狀凸塊,設置於上述第二導線上,且連接至上述半導體晶片的一導電凸塊。一第一導電結構,設置於上述第二導線和上述導電柱狀凸塊之間或設置於上述第二導線和上述基板之間。一晶片,設置於上述第一導線的上方。
101‧‧‧第一部分
102‧‧‧第二部分
103‧‧‧第一寬度
104‧‧‧第二寬度
105‧‧‧第三部分
106‧‧‧第三寬度
200、600‧‧‧基板
200a‧‧‧晶片貼附面
204、620‧‧‧覆晶填充材質
210a、210b、220a、220b、804a、804b、804c、804d、804e、
804f、804g、804h、902a、902b、902c、902d、902e、902f、902g、902h‧‧‧導線
230a、230a1、230a2、230a3、230a4、230a5、230a6、230b、310、616、816、916‧‧‧導電柱狀凸塊
231‧‧‧凸塊下金屬層
232、614‧‧‧銅層
232a‧‧‧集成插塞
234、612‧‧‧焊錫蓋層
240‧‧‧基座
242‧‧‧第一保護層
243‧‧‧金屬焊墊
243a‧‧‧第一邊緣
243b‧‧‧第二邊緣
244‧‧‧第二保護層
246‧‧‧應力緩衝層
246a‧‧‧開口
260、606‧‧‧阻焊層
270‧‧‧第一方向
272‧‧‧第二方向
300、610‧‧‧半導體晶片
500a、500b、500c‧‧‧半導體封裝
602‧‧‧第一導線
602a、604a‧‧‧部分
604‧‧‧第二導線
605、607‧‧‧垂直側壁
608‧‧‧延伸部分
609‧‧‧底面
620a、620b、620c、620d、620a1、620a2、620b1、620b2、620c1、620c2、620d1、620d2、720a1、720a2、720a3、720a4、720a5、720a6‧‧‧導電結構
620c1-1、620c1-2、620c1-3、620c2-1、620c2-2、620c2-3、620d1-1、620d1-2、620d1-3、620d2-1、620d2-2、620d2-3‧‧‧導電結構部分
624‧‧‧主動表面
d1、d2‧‧‧距離
H‧‧‧底座高度
L1‧‧‧第一長度
L2‧‧‧第二長度
L3‧‧‧第三長度
L4‧‧‧第四長度
Lb‧‧‧凸塊長度
W‧‧‧線寬
Wb、B‧‧‧凸塊寬度
W1、W2‧‧‧寬度
第1圖顯示本發明一實施例之半導體封裝之剖面示意圖。
第2圖顯示本發明一實施例之半導體封裝之位於一晶片上的一導電柱狀凸塊的詳細結構剖面示意圖。
第3圖顯示本發明一實施例之半導體封裝之一金屬焊墊和一導電柱狀凸塊的俯視示意圖。
第4a圖顯示本發明另一實施例之半導體封裝的一部分之俯視示意圖。
第4b圖顯示沿第4a圖的I-I’切線的部分剖面圖。
第5a至5f圖顯示本發明不同實施例之一導電柱狀凸塊之俯視示意圖。
第6a圖顯示本發明又一實施例之半導體封裝的一部分之俯視示意圖。
第6b圖顯示沿第6a圖的A-A’切線的一種可能的剖面示意圖。
第6c圖顯示沿第6a圖的A-A’切線的另一種可能的剖面示意圖。
第6d、6e、6f圖為第6b、6c圖的放大示意圖,顯示本發明不同實施例之導電結構的詳細結構。
第7a至7f圖顯示本發明不同實施例之一額外金屬焊墊的俯視示意圖。
第8a至8h圖為本發明不同實施例之導電柱狀凸塊和其相應的導線的配置俯視示意圖,其中上述導線視為用於繞線的訊號/接地線段。
第9a至9h圖為本發明不同實施例之導電柱狀凸塊和其相
應的導線的配置俯視示意圖,其中每一條上述導線具有視為一焊墊區的一末端部分。
為了讓本發明之目的、特徵、及優點能更明顯易懂,下文特舉較佳實施例,並配合所附圖示,做詳細之說明。本發明說明書提供不同的實施例來說明本發明不同實施方式的技術特徵。其中,實施例中的各元件之配置係為說明之用,並非用以限制本發明。且實施例中圖式標號之部分重複,係為了簡化說明,並非意指不同實施例之間的關聯性。
第1圖顯示本發明一實施例之半導體封裝500a之部分剖面示意圖。第2圖顯示本發明一實施例之半導體封裝500a之位於一晶片上的一導電柱狀凸塊的詳細結構的剖面示意圖。在本實施例中,半導體封裝500a為一覆晶封裝體(flip chip package),其使用一銅柱狀凸塊(copper pillar bump)的一導電柱狀凸塊以作為一半導體晶片和一基板之間的連接。請參考第1和2圖,半導體封裝500a包括一基板200,其具有一晶片貼附面200a。在本發明一實施例中,基板200可由例如矽的半導體材質來形成,或由例如雙馬來醯亞胺-三氮雜苯樹脂(bismaleimide triacine,BT)、聚醯亞胺(polyimide)或ABF絕緣膜(ajinomoto build-up film,ABF)等有機材質來形成。複數個導線210a、210b、220a、220b,係設置於基板200的晶片貼附面200a上。在本發明一實施例中,導線210a、210b、220a、220b可包括訊號線或接地線,上述訊號線或接地線可用於直接固接
(mounted)至基板200之半導體晶片300的輸入/輸出(input/output,I/O)連接。
基板200的晶片貼附面200a可被一阻焊層(solder resistance layer)260覆蓋。在本實施例中,阻焊層260可由感光材料構成,且可藉由微影製程以曝光部分的導線210a、210b、220a、220b和一部分晶片貼附面200a。舉例來說,可移除阻焊層260內之位於半導體晶片300的正下方的一預定開口區,以形成一開口防焊物(open solder mask)或開口阻焊物(open solder resist),使導線210a、210b、220a、220b從其中的預定開口區暴露出來。
一半導體晶片300或晶片300固接於基板200的晶片貼附面200a上,上述晶片300具有面向基板200的主動表面(active surface)。晶片300的電路藉由一新穎的導線-凸塊-導線(trace bump trace,TBT)內連接結構內部連接至基板200的電路。上述TBT內連接結構可包括複數個板條形狀(lathy)的導電柱狀凸塊230a和230b,設置於晶片300的主動表面上。導電柱狀凸塊230a和230b的至少一個可由一金屬堆疊構成,上述金屬堆疊包括例如一濺鍍凸塊下金屬層的一凸塊下金屬層(under bump metallurgy(UBM)layer)(圖未顯示)、例如一電鍍銅層232之一銅層232和一焊錫蓋層(solder cap)234。以下會說明導電柱狀凸塊230a和230b的詳細結構。
請參考第1圖,導電柱狀凸塊230a和230b係分別對應至晶片貼附面200a上的導線210a、210b。在覆晶組裝製程期間,例如兩個導電柱狀凸塊230a和230b係分別接合至導線
210a、210b上。由於導電柱狀凸塊230a和230b具有小尺寸,所以可以降低接合應力、增加接合至導線的空間(bump-to-trace space),且有效地避免接合至導線的橋接問題(the problem of bump-to-trace bridging)。並且,可得到更大的繞線空間。經過回焊製程之後,可於具有增加之底座高度(stand-off height)H的一晶片300和基板200之間的一間隙中導入一覆晶填充材質204。上述增加之底座高度H有助於進行覆晶填充材質製程(underfill process)。在本發明一實施例中,覆晶填充材質204可包括毛細覆晶填充材質(capillary underfill,CUF)、成型覆晶填充材質(molded underfill,MUF)或上述組合。
第2圖顯示本發明一實施例之半導體封裝之位於一晶片300上的一導電柱狀凸塊310的詳細結構的剖面示意圖。上述導電柱狀凸塊的剖面示意圖為沿導電柱狀凸塊的長軸方向的剖面示意圖。如第2圖所示,晶片300可包括一基座240、位於基座240上方的一第一保護層242、位於第一保護層242之上的一金屬焊墊243、覆蓋金屬焊墊243和第一保護層242的一第二保護層244,以及位於第二保護層244之上的一應力緩衝層246。”之上(overlying)”一詞可意指但並非限制於”上(on)”或”上方(over)”。在本實施例中,基座240可包括但並非限制於一半導體基板、形成於上述半導體基板的主要表面上的電路元件、層間介電層(ILD)和內連接結構。在本發明一實施例中,上述內連接結構可包括複數個金屬層、與金屬層交錯堆疊的複數個介電層,以及穿過位於半導體基板上的介電層的複數個介層孔插塞。金屬焊墊243係屬於內連接結構的金屬層的一最上
層金屬層。並且,第一保護層242係屬於內連接結構的介電層的一最上層介電層。第一保護層242可包括但並非限制於氮化矽、氧化矽、氮氧化矽或上述組合。第二保護層244可包括但並非限制於氮化矽、氧化矽、氮氧化矽或上述組合。應力緩衝層246可包括但並非限制於聚醯亞胺(polyimide)、聚苯噁唑(polybenzoxazole,PBO)或上述組合。金屬焊墊243可包括但並非限制鋁、銅或上述合金。應力緩衝層246可包括第二保護層244。
可於應力緩衝層246中形成一開口246a以暴露出來至少一部分的金屬焊墊243。開口246a可具有任意形狀。在本發明一實施例中,開口246a可為沿導電柱狀凸塊的長軸方向延伸的板條形狀(lathy)或橢圓形狀。一凸塊下金屬層(UBM layer)231,可形成於開口246a中暴露出來的金屬焊墊243上。凸塊下金屬層231也可延伸於應力緩衝層246的一頂面上。在本實施例中,可利用濺鍍法形成凸塊下金屬層231,且凸塊下金屬層231可包括鈦、銅或上述組合。例如一電鍍銅層之一銅層232,可形成於凸塊下金屬層231上。可利用銅層232和凸塊下金屬層231填充開口246a,且位於開口246a內的銅層232和凸塊下金屬層231可形成一集成插塞(integral plug)232a,上述集成插塞232a係電性耦接導電柱狀凸塊(230a或230b)和其下的金屬焊墊243。一焊錫蓋層234,可形成於銅層232上。一鎳層233,可形成於銅層232和焊錫蓋層234之間。例如銅層232的銅層可為一重佈線層(redistribution layer,RDL)的一部分,或可與重佈線層(RDL)同時形成。
第3圖顯示本發明一實施例之半導體封裝之一金屬焊墊243和一導電柱狀凸塊310的俯視示意圖。在本實施例中,為了改善高密度半導體封裝的繞線能力,可縮小金屬焊墊的尺寸,使金屬焊墊於俯視圖中的形狀類似於相應的導電柱狀凸塊於俯視圖中的形狀。在本發明一實施例中,上述金屬焊墊可於俯視圖中僅具有二重旋轉對稱(2-fold rotational symmetry)。舉例來說,上述金屬焊墊可為一八角形(octangular shape)或一橢圓形(oval-shape)。在如第3圖所示之本發明一實施例中,形成於基板的晶片貼附面上的金屬焊墊243可為一八角形。金屬焊墊243可具有沿一第一方向270的一第一邊緣243a,以及沿一第二方向272的一第二邊緣243b,其中第二邊緣243b係實質上垂直於第一邊緣243a。並且,第一邊緣243a不相鄰於第二邊緣243b。在本實施例中,在俯視圖中,沿第一方向270的第一邊緣243a可設計不同於沿第二方向272的第二邊緣243b。並且,在如第3圖所示的俯視圖中,金屬焊墊243沿第一方向270的一第一長度L1可設計不同於沿第二方向272的一第二長度L2。在本實施例中,第一長度L1和第二長度L2的比率可設計約介於46:45和99:54之間。在本發明一實施例中,第一方向270和第二方向272之間的一夾角可設計大於0度且小於等於90度。
在本發明另一實施例中,半導體封裝的金屬焊墊243可為一橢圓形或另一種具180度旋轉對稱的形狀,在俯視圖中,金屬焊墊243沿第一方向270的第一長度L1可設計不同於沿第二方向272的第二長度L2。並且,第一長度L1和第二長度L2
的比率可設計約介於46:45和99:54之間。再者,第一方向270和第二方向272之間的一夾角可設計大於0度且小於等於90度。舉例來說,如果金屬焊墊243為一橢圓形,第一方向270也會沿著金屬焊墊243的一長軸(major axis),而第二方向272也會沿著金屬焊墊243的一短軸(minor axis)。
如第2和3圖所示,於應力緩衝層246中形成開口246a以暴露出來至少一部分的金屬焊墊243。在如第3圖所示之一實施例中,開口246a在俯視圖中為一八角形(octangular shape)。並且,開口246a具有沿第一方向270的第三長度L3和不同於第三長度L3之沿第二方向272的第四長度L4。在本發明另一實施例中,開口246a可為一橢圓形或另一種具180度旋轉對稱的形狀,類似於金屬焊墊243。另外,導電柱狀凸塊310在俯視圖中可為一八角形(octangular shape)或一橢圓形(oval-shape)。
在本發明其他實施例中,可設計導電柱狀凸塊對導線的一寬度或長度比率,以進一步改善高密度半導體封裝的繞線能力。第4a圖顯示本發明另一實施例之半導體封裝500b的一部分之俯視示意圖。第4b圖顯示沿第4a圖的I-I’切線的部分剖面圖。在本實施例中,半導體封裝500a為一覆晶封裝體,其使用一銅柱狀凸塊(copper pillar bump)的一導電柱狀凸塊以作為一半導體晶片和一基板之間的連接。上述圖式中的各元件如有與第1至3圖所示相同或相似的部分,則可參考前面的相關敍述,在此不做重複說明。
在如第4a和4b圖所示之實施例中,在俯視圖中,
導電柱狀凸塊230a和230b可具有沿導線210a、210b延伸的一圓滑且些微拉長的輪廓。在本實施例中,例如導電柱狀凸塊230b的至少一個導電柱狀凸塊的凸塊寬度Wb範圍可從實質上等於或大於例如位於基板200的晶片貼附面200a上的導線210b之導線的一線寬W至小於導線的線寬W的2.5倍。在本發明一實施例中,例如導電柱狀凸塊230b的至少一個導電柱狀凸塊的凸塊長度Lb範圍可從例如位於基板200的晶片貼附面200a上的導線210b之導線的線寬W的0.5倍至3倍。並且,晶片300可具有一凸塊間隙P,介於50 μm和200 μm之間。
另外,可設計複數個導電柱狀凸塊的至少一個的形狀為除了橢圓形之外的形狀,以擴大設計選擇。第5a至5f圖顯示本發明不同實施例之一導電柱狀凸塊之俯視示意圖。如第5a至5f圖所示,導電柱狀凸塊230a1至230a6為非圓滑形狀(non-round shape)或非對稱形狀(asymmetric shape)的導電柱狀凸塊,可了解本發明並非被上述揭露的實施例所限制。
第6a圖顯示本發明又一實施例之半導體封裝500c的一部分之俯視示意圖。第6b圖顯示沿第6a圖的A-A’切線的一種可能的剖面示意圖。第6c圖顯示沿第6a圖的A-A’切線的另一種可能的剖面示意圖。本發明一實施例之半導體封裝500c為一覆晶封裝體,其使用一銅柱狀凸塊(copper pillar bump)的一導電柱狀凸塊以作為一半導體晶片和一基板之間的連接。如第6a圖至第6c圖所示,本發明又一實施例之半導體封裝500c包括一基板600,基板600具有設置於其上的第一導線602和第二導線604。在本發明一實施例中,基板600可由例如矽的半導體材質
來形成,或由例如雙馬來醯亞胺-三氮雜苯樹脂(bismaleimide triacine,BT)、聚醯亞胺(polyimide)或ABF絕緣膜(ajinomoto build-up film,ABF)等有機材質來形成。在本發明一實施例中,第一導線602和第二導線604可包括訊號線或接地線,上述訊號線或接地線可用於直接固接(mounted)至基板600之半導體晶片610的輸入/輸出(input/output,I/O)連接。在本實施例中,每一條第一導線602具有可視為基板600的一墊區域(pad region)的一部分602a,而每一條第二導線604可視為用於繞線(routing)的訊號線段/接地線段。
請再參考第6a圖至第6c圖,形成一阻焊層(solder resistance layer)606,以覆蓋基板200。另外,除了阻焊層606的延伸部分608之外,阻焊層606暴露出基板600與後續固著於(mounted)基板600之上的半導體晶片610之間的重疊區域。請注意,阻焊層606的延伸部分608係沿著第二導線604延伸,且覆蓋部分第二導線604。並且,除了延伸部分608之外的阻焊層606係設置遠離於後續固著的半導體晶片610,且與半導體晶片610相距一距離d1。在本發明一實施例中,阻焊層606可包括防焊材質(solder mask material)、氧化物、氮化物或氮氧化物。如第6b圖所示,阻焊層606的延伸部分608覆蓋第二導線604的一部分604a。請注意,阻焊層606的延伸部分608的寬度W2係設計為大於第二導線604的一部分604a的寬度W1,使得延伸部分608的底面609的一部分暴露於第二導線604的一部分604a之外。且阻焊層606的延伸部分608具有一垂直側壁(vertical sidewall)607,第二導線604的一部分604a具有一垂直側壁
605,垂直側壁607凸出於與其相鄰的垂直側壁605。因此,延伸部分608與第二導線604的一部分604a共同具有一T形剖面。
請再參考第6a圖至第6c圖,然後,於第一導線602的一部分602a(亦即墊區域)上形成導電柱狀凸塊616。在本實施例中,每一個導電柱狀凸塊616可由一金屬堆疊構成,上述金屬堆疊包括例如一濺鍍凸塊下金屬層的一凸塊下金屬層(under bump metallurgy(UBM)layer)(圖未顯示)、一銅層614和一焊錫蓋層(solder cap)612。在本發明另一實施例中,可於導電柱狀凸塊616和第一導線602的一部分602a(亦即墊區域)之間形成例如鎳的導電緩衝層(圖未顯示)。上述導電緩衝層可作為導電柱狀凸塊616的一種晶層(seed layer)、一黏著層(adhesion layer)和/或一阻障層(barrier layer)。在本發明一實施例中,導電柱狀凸塊616可作為後續形成之導電凸塊的焊點(solder joint),而導電凸塊係用於傳輸半導體晶片610的輸入/輸出(I/O)訊號、接地(ground)訊號或電源(power)訊號。因此,導電柱狀凸塊616可幫助增加凸塊結構的機械強度。
請再參考第6a圖至第6c圖,將半導體晶片610固著於基板600的一晶片貼附面上,其中半導體晶片610具有設置於其主動表面624上的複數個導電凸塊或金屬焊墊(或接合焊墊(bond pad))(圖未顯示)。上述半導體晶片610的金屬焊墊藉由導電柱狀凸塊616分別連接至第一導線602的一部分602a(亦即墊區域),且導電柱狀凸塊616位於金屬焊墊和第二導線602的一部分602a之間。如第6a圖所示,阻焊層606係設置遠離於與導電柱狀凸塊616重疊之第二導線602的一部分602a(亦即墊區
域),且與第二導線602的一部分602a相距至少一距離d2。並且,阻焊層606的延伸部分608位於半導體晶片610的下方,且位於半導體晶片610的主動表面624的下方,且位於半導體晶片610的一投影區域(projection area)(圖未顯示)內。
請再參考第6a圖至第6c圖,可將一覆晶填充材質620填充基板600和半導體晶片610之間的一間隙,且覆蓋阻焊層606。覆晶填充材質620係用以補償基板、導線和半導體晶片之間熱膨脹係數(CTE)的差異。在本實施例中,阻焊層606的延伸部分608的底面609的一部分被覆晶填充材質620包裹。
上述覆晶填充材質包裹阻焊層的延伸部分的底面的一部分,且阻焊層的延伸部分的寬度係大於第二導線的部分的寬度,使上述覆晶填充材質會被由阻焊層的延伸部分和第二導線的部分共同構成的T形物錨定(anchored)。因此,可改善習知技術於覆晶填充材質和導線之間發生的覆晶填充材質分層(underfill delamination problem)問題。並且,阻焊層的延伸部分僅延伸進入半導體晶片的一投影區域,以覆蓋第二導線的一部分,阻焊層的剩餘部分會設置為遠離於半導體晶片,且與半導體晶片相距一距離,使半導體封裝仍然具有足夠的空間容許覆晶填充材質流動,以填充基板和半導體晶片之間的間隙。因此,阻焊層的延伸部分不會影響填充覆晶填充材質之點膠製程的成果。此外,本發明實施例之半導體封裝可應用於多種的封裝製程。舉例來說,可僅使用成型材質(molding compound)來填充基板和半導體晶片之間的間隙。在本發明另一實施例中,可使用成型材質和覆晶填充材質兩者填充基板和半導體晶片
之間的間隙。在本發明其他實施例中,可僅使用覆晶填充材質填充基板和半導體晶片之間的間隙。
另外,可於包括訊號線或接地線的第二導線602之下或之上增加一額外導電結構,以擴大設計選擇。上述額外導電結構的位置可設計與導電柱狀凸塊重疊或遠離於導電柱狀凸塊。如第6a圖至第6c圖所示,一導電結構620a、620b、620c或620d設置於第二導線602和導電柱狀凸塊616之間或設置於第二導線602和基板600之間。在如第6a圖至第6c圖所示的本發明一實施例中,一導電結構620a1或620c1係設置於第二導線602和基板600之間。另外,導電結構620a1或620c1係接觸第二導線602和基板600,且與導電柱狀凸塊616重疊。並且,一導電結構620b1或620d1設置與部分第二導線602和半導體晶片610重疊,其中部分第二導線602係遠離於導電柱狀凸塊616。在如第6a和6c圖所示的本發明另一實施例中,一導電結構620a2或620c2係設置於第二導線602和導電柱狀凸塊616之間。並且,導電結構620a2或620c2係接觸第二導線602和導電柱狀凸塊616,且與導電柱狀凸塊616重疊。再者,一導電結構620b2或620d2設置與部分第二導線602和基板600重疊,其中部分第二導線602係遠離於導電柱狀凸塊616。
在本發明一實施例中,導電結構620a、620b、620c或620d可用於傳遞訊號。在本發明一實施例中,導電結構620a、620b、620c或620d可包括一單一層結構。在本實施例中,導電結構620a和620b為單一層結構,而導電結構620c和620d為多層結構。在本發明一實施例中,上述單一層結構可包括一導
線或一金屬焊墊。在本發明一實施例中,上述多層結構可包括一導線、一金屬焊墊或上述組合的一堆疊結構。在如第6b和6c圖所示的本發明一實施例中,設置於第二導線602和基板600之間的導電結構620c1/620c2可包括從頂部至底部的導電結構部分620c1-1/620c2-1、620c1-2/620c2-2、620c1-3/620c2-3。每一個導電結構部分620c1-1/620c2-1、620c1-2/620c2-2、620c1-3/620c2-3可包括一導線或一金屬焊墊。舉例來說,導電結構部分620c1-1/620c2-1、620c1-2/620c2-2、620c1-3/620c2-3可分別為一導線、一金屬焊墊和另一導線。因此,導電結構部分620c1-1/620c2-1、620c1-2/620c2-2、620c1-3/620c2-3可共同構成包括一導線、一金屬焊墊或上述組合的一堆疊結構。然而,應注意的是導電結構部分的數量並無限制。
類似地,在如第6b和6c圖所示的本發明一實施例中,設置於第二導線602和半導體晶片610之間的導電結構620d1/620d2可包括從頂部至底部的導電結構部分620d1-1/620d2-1、620d1-2/620d2-2、620d1-3/620d2-3。每一個導電結構部分620d1-1/620d2-1、620d1-2/620d2-2、620d1-3/620d2-3可包括一導線或一金屬焊墊。舉例來說,導電結構部分620d1-1/620d2-1、620d1-2/620d2-2、620d1-3/620d2-3可分別為一導線、一金屬焊墊和另一導線。因此,導電結構部分620d1-1/620d2-1、620d1-2/620d2-2、620d1-3/620d2-3可共同構成包括一導線、一金屬焊墊或上述組合的一堆疊結構。然而,應注意的是導電結構部分的數量並無限制。
第6d、6e、6f圖為第6b、6c圖的放大示意圖,顯示
本發明不同實施例之導電結構620a1、620a2、620b2、620c1和620d2的詳細結構。第6d圖為第6b、6c圖所示的導電結構620a1或620b2的詳細配置。在本實施例中,可視為一金屬焊墊620a1/620b2的導電結構620a1/620b2係直接設置於基板600上,且第二導線602設置於金屬焊墊620a1/620b2的頂部上。
第6e圖為第6c圖所示的導電結構620a2的詳細配置。在本實施例中,第二導線602設置於基板600上。並且,可視為一金屬焊墊620a2的導電結構620a2係設置於第二導線602上。再者,導電柱狀凸塊616設置於金屬焊墊620a2的頂部上。
第6f圖為第6b、6c圖所示的導電結構620c1或620d2的詳細配置。在本實施例中,導電結構620c1/620d2係直接設置於基板600上,且,導線(例如第6b、6c圖所示的第二導線602)或一導電柱狀凸塊(例如第6b、6c圖所示的導電柱狀凸塊616)設置於金屬焊墊620c1/620d2的頂部上。在本實施例中,金屬焊墊620c1/620d2可包括可包括從頂部至底部的導電結構部分620c1-1/620d2-1、620c1-2/620d2-2、620c1-3/620d2-3。在本實施例中,導電結構部分620c1-1/620d2-1、620c1-2/620d2-2、620c1-3/620d2-3可分別為一導線620c1-1/620d2-1、一金屬焊墊620c1-2/620c2-2和另一導線620c1-3/620d2-3。第6f圖顯示金屬焊墊620c1-2/620d2-2係夾設於導線620c1-1/620d2-1和導線620c1-3/620d2-3之間。在本發明一實施例中,金屬焊墊620c1-2/620d2-2可被更多的金屬焊墊取代。
增加於第二導線602之下或之上的額外導電結構在俯視圖中可具有不同的形狀,以擴大設計選擇。第7a至7f圖
顯示本發明不同實施例之一額外導電結構的俯視示意圖。如第7a至7f圖所示,導電結構720a1至720a6為多邊形、圓滑形或水滴形的導電結構。舉例來說,如第7a圖所示的導電結構720a1為一長方形(rectangular shape),如第7b圖所示的導電結構720a2為一正方形(square shape),如第7c圖所示的導電結構720a3為一新月形(crescent shape),如第7d圖所示的導電結構720a4為一十邊形(decagonal shape),如第7e圖所示的導電結構720a5為一梯形(decagonal shape),如第7f圖所示的導電結構720a6為一水滴形(drop-shape)。可了解本發明並非被上述揭露的實施例限制。
並且,設置於半導體晶片上的導電柱狀凸塊與其相應的導線可具有不同的配置,以擴大設計選擇。第8a至8h圖為本發明不同實施例之導電柱狀凸塊816和其相應的導線804a-804h的配置俯視示意圖。在本實施例中,導線804a-804h可包括訊號線或接地線,上述訊號線或接地線可用於直接固接(mounted)至基板(例如第6a圖所示的基板600)之半導體晶片(例如第6a圖所示的半導體晶片610)的輸入/輸出(input/output,I/O)連接。在本實施例中,每一條導線804a-804h可視為用於繞線(routing)的訊號線段/接地線段。
如第8a圖所示,導線804a包括具有一第一寬度103的至少一第一部分101,和具有一第二寬度104的一第二部分102,且一導電柱狀凸塊816設置於導線804a的第二部分102上。在本實施例中,可設計使導線804a的第二部分102的第二寬度104大於第一部分101的第一寬度103。並且,用於使導電
柱狀凸塊816接合於其上之導線804a的第二部分102的第二寬度104可設計大於導電柱狀凸塊816的寬度。並且,可設計使導線804a的第二部分102在俯視圖中的輪廓類似於導電柱狀凸塊816在俯視圖中的輪廓。因此,在俯視圖中,導電柱狀凸塊816係設置於導線804a的第二部分102內。
如第8b圖所示,導線804b具有一均一的寬度(線寬),且複數個(例如三個)彼此接近導電柱狀凸塊816形成於導線804b上。在本實施例中,具有較小寬度的導電柱狀凸塊816可共同用來取代具有較大寬度的一單一導電柱狀凸塊舉例來說,如第8b圖所示的導電柱狀凸塊816的寬度係設計小於第8a圖所示的(單一)導電柱狀凸塊816的寬度。
如第8c圖所示,導線804c包括具有一第一寬度103的至少一第一部分101,和具有一第二寬度104的一第二部分102。一導電柱狀凸塊816設置於導線804c的第二部分102上。在本實施例中,可設計使導線804c的第二部分102的第二寬度104大於第一部分101的第一寬度103。並且,用於使導電柱狀凸塊816接合於其上之導線804c的第二部分102的第二寬度104可設計大於導電柱狀凸塊816的寬度。在本實施例中,導線804c的第二部分102的僅一側的相對邊緣的輪廓係設計類似於導電柱狀凸塊816在俯視圖中的輪廓。因此,在俯視圖中,導電柱狀凸塊816係設置於導線804c的第二部分102內。
如第8d圖所示,導線804d的一第二部分102具有一第二寬度104,上述第二寬度104遠大於導線804d的一第一部分101的一第一寬度103,以使複數個導電柱狀凸塊816設置於其
上。在本實施例中,可設計使俯視圖中的導線804d的第二部分102的邊緣環繞所有的導電柱狀凸塊816。因此,在俯視圖中,複數個導電柱狀凸塊816係設置於導線804d的第二部分102內。
如第8e圖所示,導線804e的一第二部分102具有一第二寬度104,上述第二寬度104遠大於導線804e的一第一部分101的一第一寬度103,以使複數個導電柱狀凸塊816設置於其上。在本實施例中,可設計使導線804e的第二部分102具有一均一的寬度(第二寬度104)。並且,在俯視圖中,導線804e的第二部分102的相對邊緣可彼此平行。
如第8f圖所示,導線804f包括具有一第一寬度103的至少一第一部分101,具有一第二寬度104的至少一第二部分102,和具有一第三寬度106的至少一第三部分105。在本實施例中,可設計使導線804f的每一個第二部分102位於兩個第一部分101之間。並且,可設計使導線804f的每一個第三部分105位於兩個第一部分101之間。在本實施例中,可設計使導線804f的第二部分102的第二寬度104和第三部分105的第三寬度106大於第一部分101的第一寬度103。並且,可設計使導線804f的第二部分102的第二寬度104和第三部分105的第三寬度106大於導電柱狀凸塊816的寬度。注意可設計使導電柱狀凸塊816接合於導線804f的第二部分102上。並且,可設計使沒有導電柱狀凸塊816接合於導線804f的第三部分105上。再者,可設計使導線804f的第二部分102在俯視圖中的輪廓類似於如第8a或8c圖所示的導線804a或804c的第二部分102在俯視圖中的輪廓。
第8g和8h圖為導電柱狀凸塊816的凸塊寬度B和導
線804g/804h的線寬W之間的關係。在本發明一實施例中,可設計使導線804g的線寬W小於導電柱狀凸塊816的凸塊寬度B。在本發明另一實施例中,可設計使導線804h的線寬W大於導電柱狀凸塊816的凸塊寬度B。在本發明一實施例中,導電柱狀凸塊816的凸塊寬度B和導線804g/804h的線寬W之間的關係可為10W<B<W/10。
第9a至9h圖為本發明不同實施例之導電柱狀凸塊916和其相應的導線902a-902h的配置俯視示意圖。在本實施例中,導線902a-902h可包括訊號線或接地線,上述訊號線或接地線可用於直接固接(mounted)至基板(例如第6a圖所示的基板600)之半導體晶片(例如第6a圖所示的半導體晶片610)的輸入/輸出(input/output,I/O)連接。在本實施例中,每一條導線902a-902h可具有視為一焊墊區的一末端部分。
如第9a圖所示,導線902a包括具有一第一寬度103的一第一部分101,和具有一第二寬度104的一第二部分102。在本實施例中,導線902a的第二部分102可視為一焊墊部分102。一導電柱狀凸塊916設置於導線902a的第二部分102上。在本實施例中,可設計使導線904a第二部分102的第二寬度104大於第一部分101的第一寬度103。並且,用於使導電柱狀凸塊916接合於其上之導線902a的第二部分102的第二寬度104可設計大於導電柱狀凸塊916的寬度。並且,可設計使導線902a的第二部分102在俯視圖中的輪廓類似於導電柱狀凸塊916在俯視圖中的輪廓。因此,在俯視圖中,導電柱狀凸塊916係設置於導線902a的第二部分102內。
如第9b圖所示,導線902b具有一均一的寬度(線寬),且複數個(例如三個)彼此接近導電柱狀凸塊916形成於導線902b上。在本實施例中,導線902b的第二部分102可視為一焊墊部分102。在本實施例中,具有較小寬度的導電柱狀凸塊916可共同用來取代具有較大寬度的一單一導電柱狀凸塊舉例來說,如第9b圖所示的導電柱狀凸塊916的寬度係設計小於第9a圖所示的(單一)導電柱狀凸塊916的寬度。
如第9c圖所示,導線902c包括具有一第一寬度103的至少一第一部分101,和具有一第二寬度104的一第二部分102。在本實施例中,導線902c的第二部分102可視為一焊墊部分102。一導電柱狀凸塊916設置於導線902c的第二部分102上。在本實施例中,可設計使導線902c的第二部分102的第二寬度104大於第一部分101的第一寬度103。並且,用於使導電柱狀凸塊916接合於其上之導線902c的第二部分102的第二寬度104可設計大於導電柱狀凸塊916的寬度。在本實施例中,導線902c的第二部分102的僅一側的相對邊緣的輪廓係設計類似於導電柱狀凸塊916在俯視圖中的輪廓。因此,在俯視圖中,導電柱狀凸塊916係設置於導線902c的第二部分102內。
如第9d圖所示,導線902d的一第二部分102具有一第二寬度104,上述第二寬度104遠大於導線902d的一第一部分101的一第一寬度103,以使複數個導電柱狀凸塊916設置於其上。在本實施例中,導線902d的第二部分102可視為一焊墊部分102。在本實施例中,可設計使俯視圖中的導線902d的第二部分102的邊緣環繞所有的導電柱狀凸塊916。因此,在俯視圖
中,複數個導電柱狀凸塊916係設置於導線902d的第二部分102內。
如第9e圖所示,導線902e的一第二部分102具有一第二寬度104,上述第二寬度104遠大於導線902e的一第一部分101的一第一寬度103,以使複數個導電柱狀凸塊916設置於其上。在本實施例中,導線902e的第二部分102可視為一焊墊部分102。在本實施例中,可設計使導線902e的第二部分102具有一均一的寬度(第二寬度104)。並且,在俯視圖中,導線902e的第二部分102的相對邊緣可彼此平行。
如第9f圖所示,導線902f包括具有一第一寬度103的至少一第一部分101,具有一第二寬度104的至少一第二部分102,和具有一第三寬度106的至少一第三部分105。在本實施例中,導線902f的最右邊的第二部分102可視為一焊墊部分102。在本實施例中,可設計使導線902f的每一個第二部分102位於兩個第一部分101之間。並且,可設計使導線902f的每一個第三部分105位於兩個第一部分101之間。在本實施例中,可設計使導線902f的第二部分102的第二寬度104和第三部分105的第三寬度106大於第一部分101的第一寬度103。並且,可設計使導線902f的第二部分102的第二寬度104和第三部分105的第三寬度106大於導電柱狀凸塊916的寬度。注意可設計使導電柱狀凸塊916接合於導線902f的第二部分102上。並且,可設計使沒有導電柱狀凸塊916接合於導線902f的第三部分105上。再者,可設計使導線902f的第二部分102在俯視圖中的輪廓類似於如第9a或9c圖所示的導線902a或902c的第二部分102在俯視
圖中的輪廓。
第9g和9h圖為導電柱狀凸塊916的凸塊寬度B和導線902g/902h的線寬W之間的關係。在本發明一實施例中,可設計使導線902g的線寬W小於導電柱狀凸塊916的凸塊寬度B。在本發明另一實施例中,可設計使導線902h的線寬W大於導電柱狀凸塊916的凸塊寬度B。在本發明一實施例中,導電柱狀凸塊916的凸塊寬度B和導線902g/902h的線寬W之間的關係可為10W<B<W/10。
雖然本發明已以較佳實施例揭露於上,然其並非用以限定本發明,任何熟習此項技藝者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
200‧‧‧基板
200a‧‧‧晶片貼附面
210a、210b、220a、220b‧‧‧導線
230a、230b‧‧‧導電柱狀凸塊
300‧‧‧半導體晶片
500b‧‧‧半導體封裝
Lb‧‧‧凸塊長度
W‧‧‧線寬
Wb‧‧‧凸塊寬度
Claims (56)
- 一種半導體封裝,包括:一基板,具有一晶片貼附面;以及一晶片,藉由一導電柱狀凸塊固接於該晶片貼附面上,其中該晶片包括:一金屬焊墊,電性耦接至該導電柱狀凸塊,其中該金屬焊墊具有一第一邊緣和實質上垂直於該第一邊緣的一第二邊緣,其中於一俯視圖中,該第一邊緣的長度不等於該第二邊緣的長度。
- 如申請專利範圍第1項所述之半導體封裝,其中該晶片更包括:一內連線結構,位於該基板和該金屬焊墊之間,其中該內連線結構包括複數個金屬層和複數個介電層,其中該內連線結構包括由該些介電層的一最上層介電層形成一第一保護層;一第二保護層,設置於該基板和該導電柱狀凸塊之間,且位於該金屬焊墊上;以及一覆晶填充材質,位於該基板和該晶片之間。
- 如申請專利範圍第1項所述之半導體封裝,其中於該俯視圖中,該金屬焊墊為八角形。
- 如申請專利範圍第2項所述之半導體封裝,其中該金屬焊墊由該內連線結構的該些金屬層的一最上層金屬層形成。
- 如申請專利範圍第1項所述之半導體封裝,其中該導電柱狀凸塊由一金屬堆疊構成,該金屬堆疊包括一凸塊下金屬層、 一銅層和一焊錫蓋層。
- 如申請專利範圍第1項所述之半導體封裝,其中於該俯視圖中,該金屬焊墊的形狀類似於相應的該導電柱狀凸塊的形狀。
- 如申請專利範圍第1項所述之半導體封裝,其中該金屬焊墊於該俯視圖中僅具有二重旋轉對稱。
- 如申請專利範圍第1項所述之半導體封裝,其中於該俯視圖中,該導電柱狀凸塊為八邊形或橢圓形。
- 如申請專利範圍第2項所述之半導體封裝,其中該第二保護層具有一開口,以暴露該金屬焊墊。
- 如申請專利範圍第9項所述之半導體封裝,其中於該俯視圖中,該開口為八邊形,且該開口具有實質上彼此垂直一第三邊緣和一第四邊緣,且其中於該俯視圖中,該第三邊緣的長度不等於該第四邊緣的長度。
- 一種半導體封裝,包括:一基板,具有一晶片貼附面;以及一晶片,藉由一導電柱狀凸塊固接於該晶片貼附面上,其中該晶片包括:一金屬焊墊,電性耦接至該導電柱狀凸塊,其中於一俯視圖中,該金屬焊墊具有沿一第一方向的一第一長度和沿一第二方向的一第二長度,且該第一長度不等於該第二長度,且其中該第一方向和該第二方向之間的夾角大於0度且小於或等於90度。
- 如申請專利範圍第11項所述之半導體封裝,其中該晶片更 包括:一內連線結構,位於該基板和該金屬焊墊之間,其中該內連線結構包括複數個金屬層和複數個介電層,其中該內連線結構包括由該些介電層的一最上層介電層形成一第一保護層;一第二保護層,設置於該基板和該導電柱狀凸塊之間,且位於該金屬焊墊上;以及一覆晶填充材質,位於該基板和該晶片之間。
- 如申請專利範圍第11項所述之半導體封裝,其中於該俯視圖中,該金屬焊墊為八角形或橢圓形。
- 如申請專利範圍第12項所述之半導體封裝,其中該金屬焊墊由該內連線結構的該些金屬層的一最上層金屬層形成。
- 如申請專利範圍第11項所述之半導體封裝,其中該導電柱狀凸塊由一金屬堆疊構成,該金屬堆疊包括一凸塊下金屬層、一銅層和一焊錫蓋層。
- 如申請專利範圍第11項所述之半導體封裝,其中於該俯視圖中,該金屬焊墊的形狀類似於相應的該導電柱狀凸塊的形狀。
- 如申請專利範圍第11項所述之半導體封裝,其中該金屬焊墊於該俯視圖中僅具有二重旋轉對稱。
- 如申請專利範圍第11項所述之半導體封裝,其中於該俯視圖中,該導電柱狀凸塊為八邊形或橢圓形。
- 如申請專利範圍第12項所述之半導體封裝,其中該第二保護層具有一開口,以暴露該金屬焊墊。
- 如申請專利範圍第19項所述之半導體封裝,其中該開口於該俯視圖中為八邊形,且該開口具有沿該第一方向的一第三長度和沿該第二方向的一第四長度,其中於一俯視圖中,該第三長度不等於該第四長度。
- 如申請專利範圍第11項所述之半導體封裝,其中該第一長度和該第二長度的比率介於46:45和99:54之間。
- 一種半導體封裝,包括:一基板,具有一晶片貼附面;以及一晶片,藉由一導電柱狀凸塊固接於該晶片貼附面上,其中該晶片包括:一金屬焊墊,電性耦接至該導電柱狀凸塊,其中該金屬焊墊於該俯視圖中僅具有二重旋轉對稱。
- 如申請專利範圍第22項所述之半導體封裝,其中該金屬焊墊具有一第一邊緣和實質上垂直於該第一邊緣的一第二邊緣,其中於一俯視圖中,該第一邊緣的長度不等於該第二邊緣的長度。
- 如申請專利範圍第22項所述之半導體封裝,其中於一俯視圖中,該金屬焊墊具有沿一第一方向的一第一長度和沿一第二方向的一第二長度,且該第一長度不等於該第二長度,且其中該第一方向和該第二方向之間的夾角大於0度且小於或等於90度。
- 如申請專利範圍第22項所述之半導體封裝,其中該晶片更包括:一內連線結構,位於該基板和該金屬焊墊之間,其中該內 連線結構包括複數個金屬層和複數個介電層,其中該內連線結構包括由該些介電層的一最上層介電層形成一第一保護層;一第二保護層,設置於該基板和該導電柱狀凸塊之間,且位於該金屬焊墊上;以及一覆晶填充材質,位於該基板和該晶片之間。
- 如申請專利範圍第22項所述之半導體封裝,其中於該俯視圖中,該金屬焊墊為八角形或橢圓形。
- 如申請專利範圍第22項所述之半導體封裝,其中該金屬焊墊由該內連線結構的該些金屬層的一最上層金屬層形成。
- 如申請專利範圍第25項所述之半導體封裝,其中該導電柱狀凸塊由一金屬堆疊構成,該金屬堆疊包括一凸塊下金屬層、一銅層和一焊錫蓋層。
- 如申請專利範圍第22項所述之半導體封裝,其中於該俯視圖中,該金屬焊墊的形狀類似於相應的該導電柱狀凸塊的形狀金屬焊墊。
- 如申請專利範圍第22項所述之半導體封裝,其中於該俯視圖中,該導電柱狀凸塊為八邊形或橢圓形。
- 如申請專利範圍第25項所述之半導體封裝,其中該第二保護層具有一開口,以暴露該金屬焊墊。
- 如申請專利範圍第31項所述之半導體封裝,其中於一俯視圖中,該開口為八邊形,且其中於一俯視圖中,該開口具有沿該第一方向的一第三長度和沿該第二方向的一第四長度,且該第三長度不等於該第四長度。
- 如申請專利範圍第24項所述之半導體封裝,其中該第一長度和該第二長度的比率介於46:45和99:54之間。
- 一種半導體封裝,包括:一基板;一導線,設置於該基板上;以及一導電柱狀凸塊,設置於該導線上,其中該導電柱狀凸塊耦接至一晶片。
- 如申請專利範圍第34項所述之半導體封裝,其中該導線包括具有一第一寬度的一第一部分,和具有一第二寬度的一第二部分,且該導電柱狀凸塊設置於該導線的該第二部分上。
- 如申請專利範圍第35項所述之半導體封裝,更包括複數個導電柱狀凸塊,設置於該導線的該第二部分上。
- 如申請專利範圍第34項所述之半導體封裝,更包括一金屬焊墊,位於該基板和該導線之間。
- 如申請專利範圍第37項所述之半導體封裝,更包括一金屬焊墊,位於該導電柱狀凸塊和該導線之間。
- 如申請專利範圍第34項所述之半導體封裝,其中該導線包括複數個導電層和一金屬焊墊,其中該金屬焊墊夾設於該些導電層之間。
- 一種半導體封裝,包括:一基板;一第一導線,設置於該基板上;一第二導線,設置於該基板上;一半導體晶片,設置於該第一導線和該第二導線的上方; 一導電柱狀凸塊,設置於該第二導線上,且連接至該半導體晶片的一導電凸塊;以及一第一導電結構,設置於該第二導線和該導電柱狀凸塊之間或設置於該第二導線和該基板之間。
- 如申請專利範圍第40項所述之半導體封裝,更包括:一阻焊層,設置於該基板上,且具有一延伸部分,該延伸部分覆蓋該第一導線的一部分,其中該阻焊層的該延伸部分的寬度大於該第一導線的該部分的寬度。
- 如申請專利範圍第40項所述之半導體封裝,其中該第一導電結構接觸該第二導線,且與該導電柱狀凸塊重疊。
- 如申請專利範圍第40項所述之半導體封裝,更包括:一第二導電結構,設置於與該第二導線的一部分和該半導體晶片重疊,或者與部分該第二導線和該基板重疊,其中該第二導線的該部分遠離於該導電柱狀凸塊。
- 如申請專利範圍第43項所述之半導體封裝,其中該第一導電結構或第二導電結構包括一單一層結構或一多層結構。
- 如申請專利範圍第44項所述之半導體封裝,其中該單一層結構包括一導線或一金屬焊墊。
- 如申請專利範圍第44項所述之半導體封裝,其中該多層結構為一導線、一金屬焊墊或上述組合的一堆疊結構。
- 如申請專利範圍第40項所述之半導體封裝,其中該第一導電結構為一多邊形、一圓滑形或一水滴形。
- 如申請專利範圍第40項所述之半導體封裝,其中該第二導線包括一訊號線或一接地線。
- 如申請專利範圍第41項所述之半導體封裝,其中該阻焊層設置以一距離遠離於該第二導線的一部分,該部分與該導電柱狀凸塊重疊。
- 如申請專利範圍第41項所述之半導體封裝,更包括一覆晶填充材質,填充該基板和該半導體晶片之間的一間隙,且覆蓋該阻焊層。
- 如申請專利範圍第41項所述之半導體封裝,其中該阻焊層的該延伸部分與該第一導線的該部分共同具有一T型剖面。
- 如申請專利範圍第41項所述之半導體封裝,其中該阻焊層的該延伸部分係低於該半導體晶片且位於該半導體晶片的投影面積內。
- 如申請專利範圍第50項所述之半導體封裝,其中該阻焊層的該延伸部分的一底面的一部分係從該第一導線的該部分暴露出來。
- 如申請專利範圍第53項所述之半導體封裝,其中該阻焊層的該延伸部分的該部分被該覆晶填充材質包裹。
- 如申請專利範圍第41項所述之半導體封裝,其中該阻焊層的該延伸部分具有一垂直側壁,突出於該第一導線的該部分的一相鄰垂直側壁,該相鄰垂直側壁相鄰於該垂直側壁。
- 如申請專利範圍第41項所述之半導體封裝,其中該阻焊層的該延伸部分沿著該第一導線延伸,且位於該半導體晶片的一晶片貼附面上方。
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TWI550728B (zh) * | 2014-03-10 | 2016-09-21 | 日月光半導體製造股份有限公司 | 封裝結構及其製造方法 |
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TWI623067B (zh) * | 2015-03-17 | 2018-05-01 | 聯發科技股份有限公司 | 半導體封裝、半導體封裝結構以及制造半導體封裝的方法 |
TWI713182B (zh) * | 2018-08-13 | 2020-12-11 | 聯發科技股份有限公司 | 半導體器件 |
TWI763198B (zh) * | 2019-12-26 | 2022-05-01 | 台灣積體電路製造股份有限公司 | 製造半導體封裝的方法以及半導體封裝 |
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US20160111358A1 (en) | 2016-04-21 |
US9553040B2 (en) | 2017-01-24 |
US20170186676A1 (en) | 2017-06-29 |
CN103367293A (zh) | 2013-10-23 |
US9520349B2 (en) | 2016-12-13 |
TWI579991B (zh) | 2017-04-21 |
US20150145127A1 (en) | 2015-05-28 |
CN106952883B (zh) | 2020-12-01 |
CN106952883A (zh) | 2017-07-14 |
US10553526B2 (en) | 2020-02-04 |
US9633936B2 (en) | 2017-04-25 |
US20130256878A1 (en) | 2013-10-03 |
CN103367293B (zh) | 2017-03-01 |
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