TW201322379A - 導電結構及其形成方法 - Google Patents

導電結構及其形成方法 Download PDF

Info

Publication number
TW201322379A
TW201322379A TW100142186A TW100142186A TW201322379A TW 201322379 A TW201322379 A TW 201322379A TW 100142186 A TW100142186 A TW 100142186A TW 100142186 A TW100142186 A TW 100142186A TW 201322379 A TW201322379 A TW 201322379A
Authority
TW
Taiwan
Prior art keywords
layer
opening
conductive
bump
pad
Prior art date
Application number
TW100142186A
Other languages
English (en)
Other versions
TWI502691B (zh
Inventor
Geng-Shin Shen
Chung-Pang Chi
Original Assignee
Chipmos Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipmos Technologies Inc filed Critical Chipmos Technologies Inc
Priority to TW100142186A priority Critical patent/TWI502691B/zh
Priority to CN201210052495.3A priority patent/CN103123917B/zh
Priority to US13/654,710 priority patent/US8872336B2/en
Publication of TW201322379A publication Critical patent/TW201322379A/zh
Priority to US14/494,026 priority patent/US9159685B2/en
Application granted granted Critical
Publication of TWI502691B publication Critical patent/TWI502691B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/03602—Mechanical treatment, e.g. polishing, grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05172—Vanadium [V] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/1148—Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1183—Reworking, e.g. shaping
    • H01L2224/11831—Reworking, e.g. shaping involving a chemical process, e.g. etching the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1183—Reworking, e.g. shaping
    • H01L2224/1184—Reworking, e.g. shaping involving a mechanical process, e.g. planarising the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1183—Reworking, e.g. shaping
    • H01L2224/11845—Chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199—Material of the matrix
    • H01L2224/1329—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本發明關於一種用於一半導體晶片之導電結構及其形成方法，半導體晶片包含一半導體基材、一襯墊、一保護層及一圖案化絕緣層，圖案化絕緣層設置於保護層上並局部且直接覆蓋於襯墊之一第一開口上以使襯墊暴露出一第二開口，其中第一開口大於第二開口。導電結構包含一凸塊下金屬層及一導電凸塊，凸塊下金屬層設置於圖案化絕緣層所形成之第二開口內並與襯墊電性連接，導電凸塊設置於凸塊下金屬層上並與凸塊下金屬層電性連接。其中，導電凸塊之一上表面係高於圖案化絕緣層之一上表面，並且導電凸塊位於第二開口內之區域係被凸塊下金屬層所包覆。

Description

導電結構及其形成方法
 本發明係關於一種導電結構及其形成方法，特別是關於一種用於一半導體晶片之導電結構及其形成方法。
覆晶(Flip Chip)封裝已逐漸成為半導體封裝之主流製程，而覆晶接合技術，即是將晶片(Chip)之正面倒置(Filp)後，再利用晶片上所形成之凸塊(Bump)作為晶片與對向基板(Substrate)上之電路電性連結的橋樑，因此作為導電結構之凸塊，其品質良窳便為半導體封裝產品整體效能之重要關鍵。
第1A至1F圖所示為習知凸塊結構及其形成步驟。首先如第1A圖所示，晶片11由基材111、襯墊112及保護層113所組成，而保護層113 會形成一第一開口113a，以局部曝露出襯墊112。
為使凸塊能順利附著於襯墊112上，如第1B圖所示，需要先行形成凸塊下金屬層(Under Bump Metal,UBM)121於保護層113上，並且凸塊下金屬層121透過保護層113所形成之第一開口113a與襯墊112電性相接，藉此凸塊下金屬層121不但具有接合凸塊與襯墊112之功用外，亦作為凸塊與襯墊112間的導電媒介。
隨後，請參閱第1C圖，形成絕緣層122於凸塊下金屬層121上，再視設計需求，使用光阻劑，以於襯墊112上方位置圖案化形成適當之第二開口122a，以便後續進行凸塊植入步驟。
因此，如第1D圖所示，可視設計需求，使用電鍍或蒸鍍或其他製程，形成凸塊123於絕緣層122之第二開口122a內，並且凸塊123透過凸塊下金屬層121與襯墊112構成電性相接。
由於凸塊123植入步驟完成後，絕緣層122階段性任務已完成，如第1E圖所示，即可去除不需要的絕緣層122。
最後，為了阻斷基材111內之晶圓元件透過凸塊下金屬層121與外部元件產生電性傳導的機會，如第1F圖所示，將以一蝕刻(UBM Etching)製程去除凸塊123底部以外的凸塊下金屬層121，便完成習知晶片11之凸塊結構。
然而上述製程中，絕緣層122及其所定義之第二開口122a僅是作為後續植入凸塊123的前置步驟，是故於形成凸塊123後，絕緣層122便無存在的必要，造成絕緣層122無法妥善運用外，還必須花費多道程序及成本，以光阻劑去除(PR Stripper)絕緣層122，然後再清洗晶片11表面殘留的光阻劑或異物後，才能繼續進行去除凸塊下金屬層121的步驟。
此外，凸塊下金屬層121通常由二層金屬所組成，習知係藉由此等金屬之導電性及各金屬層之不同元素特性，作為接合襯墊112與凸塊123之間的黏著層。然而，習知凸塊下金屬層121僅經由二金屬層之表面與襯墊112及凸塊123進行接合，倘若遇到二金屬層之製程控制品質不佳時，便容易造成凸塊下金屬層121與凸塊123之間或是凸塊下金屬層121與襯墊112之間產生裂縫，造成凸塊123的導電效果不穩定，進而影響整體晶片11之工作效能。
有鑑於此，如何提高凸塊品質及降低整體製程之成本，乃為此一業界日益重視的問題。
本發明之一目的在於提供一種使用於半導體晶片之導電結構，半導體晶片包含一半導體基材、一襯墊、一保護層及一圖案化絕緣層，襯墊設置於半導體基材上，保護層設置於半導體基材及襯墊上以使襯墊暴露出一第一開口，圖案化絕緣層設置於保護層上並局部且直接覆蓋於襯墊之第一開口上以使襯墊暴露出一第二開口，其中第一開口大於第二開口。而導電結構包含一凸塊下金屬層及一導電凸塊，凸塊下金屬層設置於圖案化絕緣層所形成之第二開口內並與襯墊電性連接，導電凸塊設置於凸塊下金屬層上並與凸塊下金屬層電性連接；其中，導電凸塊之一上表面係高於圖案化絕緣層之一上表面，由於本發明之導電凸塊位於圖案化絕緣層所形成之第二開口內之區域係被凸塊下金屬層所包覆，因此導電凸塊、凸塊下金屬層及襯墊三者間不但可穩定的結合，亦具有良好的導電傳導效果。
本發明之另一目的在於提供一種導電結構之製造方法，特別是一種可降低整體製程成本之導電結構。為達此前述目的，本發明之導電結構之製造方法包含：形成一圖案化絕緣層於一半導體晶片之一保護層上並局部且直接覆蓋於一襯墊之一第一開口上，以使襯墊暴露出一第二開口，第一開口大於第二開口，其中半導體晶片包含一半導體基材、一襯墊及一保護層，襯墊設置於半導體基材上，保護層設置於半導體基材及襯墊上以使襯墊暴露出第一開口；形成一凸塊下金屬層，覆蓋圖案化絕緣層及其所形成之第二開口內，以與襯墊電性連接；形成一導電凸塊於第二開口中以與凸塊下金屬層電性連接，其中凸塊下金屬層包覆導電凸塊之一周圍；去除凸塊下金屬層之一外部區域層，使導電凸塊之一上表面高於凸塊下金屬層之一上表面，並且導電凸塊位於該第二開口內之區域係被凸塊下金屬層所包覆；換言之，導電凸塊在不高於圖案化絕緣層之區域係被凸塊下金屬層所包覆。其中外部區域層係指位於第二開口之外的區域。
本發明藉由改變習知導電結構之製程順序，並保留習知技術中會被去除之絕緣層，藉以作為導電結構之固定輔助元件以及半導體晶片之絕緣阻隔層，藉此不但可增加導電結構的導電穩定性，並可減少不必要的製程步驟，以達節省成本之功效。
為讓本發明之上述目的、技術特徵和優點能更明顯易懂，下文係以較佳實施例配合所附圖式進行詳細說明。
以下將透過實施例來解釋本發明內容，然而，關於實施例中之說明僅為闡釋本發明之技術內容及其目的功效，而非用以直接限制本發明。須說明者，以下實施例以及圖示中，與本發明非直接相關之元件已省略而未繪示；且圖示中各元件之尺寸及相對位置關係僅用以示意俾便瞭解，非用以限制實施比例及尺寸大小。
第2A至2D圖係本發明較佳實施例之導電結構22之製造流程示意圖，其中第2D圖為製造完成後之導電結構22示意圖。如第2D圖所示，本實施例之導電結構22包含凸塊下金屬層23及導電凸塊24，凸塊下金屬層23設置於圖案化絕緣層214所形成之第二開口214a內並與襯墊212電性連接，導電凸塊24設置於凸塊下金屬層23上並與凸塊下金屬層23電性連接。其中，導電凸塊24之上表面24s係高於圖案化絕緣層214之上表面214s，且導電凸塊24位於第二開口214a內之區域係被凸塊下金屬層23所包覆，亦即凸塊下金屬層23 包覆了導電凸塊24之上表面214s以外之區域。
於本實施例中，導電凸塊24之上表面24s高於圖案化絕緣層214之上表面214s約2至5微米(micrometer)。而凸塊下金屬層23包含第一導體層231及第二導體層232，第一導體層231設置於第二開口214a內並與襯墊212電性連接；第二導體層232設置於第一導體層231上並與第一導體層231電性連接。
第2A圖至2D圖所示為前述實施例之導電結構的製造方法流程示意圖，以下將依照製程順序配合圖式依序說明。
首先，請參閱第2A圖，半導體晶片21包含一半導體基材211、一襯墊212、一保護層213及一圖案化絕緣層214，襯墊212係設置於半導體基材211上，保護層213係設置於半導體基材211及襯墊212上，並暴露出襯墊212之一部分以定義出一第一開口213a。如同所屬技術領域具有通常知識者所瞭解，襯墊212之材質較佳可由金、銅或其他金屬所製成，以作為半導體晶片21與外界電性傳導的接點。
在此特別說明的是，有別於習知導電結構製程係依序先形成凸塊下金屬層、圖案化絕緣層後，再形成導電凸塊；本發明製程之一特點即在於，先將圖案化絕緣層214形成於保護層213上並局部且直接覆蓋於襯墊212之第一開口213a上，並暴露出襯墊212而於該襯墊212上形成另一開口，即前述之第二開口214a，其中第一開口213a大於第二開口214a。於本實施態樣中，圖案化絕緣層214之材料較佳選自聚醯亞胺(Polyimide, PI)、阻焊層(SolderResist, SR)、苯環丁烯(Benzocyclobutene, BCB)或矽氧烷聚合物(siloxanepolymers, SINR)，然後視實際需求，可利用一光罩微影製程或一蝕刻製程，以圖案化形成第二開口214a，再進一步固化(cured)前述圖案化絕緣層214。在此補充說明，於本實施例中所使用的矽氧烷聚合物(siloxanepolymer)為Shin-Etsu化學有限公司所製造之SINR系列材料。
請進一步參考第2B圖，完成圖案化絕緣層214之步驟後，便可形成凸塊下金屬層23以覆蓋於圖案化絕緣層214上以及圖案化絕緣層214所形成之第二開口214a內；藉此凸塊下金屬層23可透過圖案化絕緣層214所形成之第二開口214a，以與襯墊212電性連接。
更明確而言，凸塊下金屬層23分別由第一導體層231及第二導體層232所組成。先形成第一導體層231以覆蓋於圖案化絕緣層214上及第二開口214a內，並與襯墊212電性連接；再形成第二導體層232以覆蓋於第一導體層231上，並與第一導體層231電性相接。如同所屬技術領域具有通常知識者所瞭解，第一導體層231較佳選自一鈦、鎢、釩或其合金所製成，除了可防止第二導體層232與襯墊212的金屬擴散，同時更強化彼此間之附著力；而第二導體層232較佳選自金、銅、銀或其合金所製成，以增加襯墊212與導電凸塊間之電性傳導；然而本發明之第一導體層及第二導體層所選用之材料並不以上述為限，凡具有導電特性之材料均可作為本發明之應用。
請進一步參考第2C圖，形成導電凸塊24於第二開口214a中以與凸塊下金屬層23電性連接，而導電凸塊24被凸塊下金屬層23所包覆。更明確而言，形成導電凸塊24之方式，較佳係以電鍍方式所製成，其中導電凸塊24係可為金、銅、銀、鎳或其合金所製成；於其他實施態樣中，導電凸塊可為具導電性之高分子凸塊，其中具導電性之高分子凸塊係為印刷(Printing)或點膠方式所形成。
為了方便說明，如第2C圖所示，在此將第二開口214a以外的區域界定為一外部區域層233；詳言之，外部區域層233係指圖案化絕緣層214上方之凸塊下金屬層23。由於現階段導電凸塊24整體被凸塊下金屬層23所包覆，尚無法與外界之基板進行接合，因此必須去除外部區域層233。更明確而言，由於導電凸塊24的硬度高於凸塊下金屬層23，故凸塊下金屬層23之外部區域層233內更容易被去除；因此，接下來將藉由一研磨法(Lapping)、一電漿蝕刻法(Plasma Etching)或一化學機械研磨法(Chemical Mechanical Polishing, CMP)來去除凸塊下金屬層23之外部區域層233。去除外部區域層233後，如第2D圖所示，導電凸塊24之上表面24s便高於凸塊下金屬層23之上表面23s，並且導電凸塊24 位於該第二開口214a內 之區域係被凸塊下金屬層23所包覆。更明確而言，圖案化絕緣層214上方之凸塊下金屬層23已經移除，只剩下第二開口214a內之凸塊下金屬層23包覆著導電凸塊24，而凸塊下金屬層23之上表面23s則與圖案化絕緣層214之上表面214s齊平。因此，完成後之導電結構22，圖案化絕緣層214之厚度約2至20微米，而導電凸塊24之上表面24s高於圖案化絕緣層214之上表面214s約2至5微米。最後，如第3圖所示，導電結構22之導電凸塊24便可與對向基板31之電路(圖未示出)進行接合。
相較於習知之導電結構製程，移除不必要的圖案化絕緣層，本發明之導電結構特別保留 圖案化絕緣層 並進一步固化後，以作為半導體晶片與外部基板之間的阻隔層，具有減少製程並妥善運用圖案化絕緣層的使用功能。
此外，由於凸塊下金屬層包覆著導電凸塊的下半部，再由固化後之圖案化絕緣層支撐著凸塊下金屬層及導電凸塊，除了增加導電凸塊與凸塊下金屬層之間的導電面積外，也加強凸塊下金屬層的接合結構，避免導電凸塊與凸塊下金屬層間或者襯墊與凸塊下金屬層間產生裂縫，因此本發明之半導體晶片及導電結構具有較高之良率及良好導電效果。
上述之實施例僅用來例舉本發明之實施態樣，以及闡釋本發明之技術特徵，並非用來限制本發明之範疇。任何熟悉此技術者可輕易完成之改變或均等性之安排均屬於本發明所主張之範圍，本發明之權利範圍應以申請專利範圍為準。
111．．．基材
112．．．襯墊
113．．．保護層
113a．．．第一開口
121．．．凸塊下金屬層
122．．．絕緣層
122a．．．第二開口
123．．．凸塊
21．．．半導體晶片
211．．．半導體基材
212．．．襯墊
213．．．保護層
213a．．．第一開口
214．．．圖案化絕緣層
214a．．．第二開口
214s．．．上表面
22．．．導電結構
23．．．凸塊下金屬層
23s．．．上表面
231．．．第一導體層
232．．．第二導體層
233．．．外部區域層
24．．．導電凸塊
24s．．．上表面
31．．．對向基板
第1A至1F圖係習知導電結構及其製造方法之示意圖；
第2A至2D圖係本發明之導電結構及其製造方法之示意圖；以及
第3圖係為應用本發明之導電結構之半導體晶片與基板之連接示意圖。
21．．．半導體晶片
211．．．半導體基材
212．．．襯墊
213．．．保護層
213a．．．第一開口
214．．．圖案化絕緣層
214a．．．第二開口
214s．．．上表面
22．．．導電結構
23．．．凸塊下金屬層
23s．．．上表面
231．．．第一導體層
232．．．第二導體層
24．．．導電凸塊
24s．．．上表面

Claims (16)

  1. 一種用於一半導體晶片之導電結構，該半導體晶片包含一半導體基材、一襯墊、一保護層及一圖案化絕緣層，該襯墊設置於該半導體基材上，該保護層設置於該半導體基材及該襯墊上以使該襯墊暴露出一第一開口，該圖案化絕緣層設置於該保護層上並局部且直接覆蓋於該襯墊之該第一開口上以使該襯墊暴露出一第二開口，該第一開口大於該第二開口，該導電結構包含：
    　　一凸塊下金屬層(Under Bump Metal, UBM)，設置於該圖案化絕緣層所形成之該第二開口內並與該襯墊電性連接；以及
    　　一導電凸塊，設置於該凸塊下金屬層上並與該凸塊下金屬層電性連接，
    　　其中，該導電凸塊之一上表面係高於該圖案化絕緣層之一上表面，其中該導電凸塊位於該第二開口內之區域係被該凸塊下金屬層所包覆。
  2. 如請求項1所述之導電結構，其中該導電凸塊之該上表面高於該圖案化絕緣層之該上表面約2至5微米(micrometer)。
  3. 如請求項1所述之導電結構，其中該圖案化絕緣層係為聚醯亞胺(Polyimide, PI)、阻焊層(SolderResist, SR)、苯環丁烯(Benzocyclobutene, BCB)或矽氧烷聚合物(siloxane polymer)。
  4. 如請求項1所述之導電結構，其中該圖案化絕緣層之厚度約2至20微米。
  5. 如請求項1所述之導電結構，其中該導電凸塊係為金、銅、銀、鎳或其合金所製成。
  6. 如請求項1所述之導電結構，其中該導電凸塊係為一導電高分子凸塊。
  7. 如請求項6所述之導電結構，其中該導電高分子凸塊係為印刷(Printing)或點膠方式所形成。
  8. 如請求項1所述之導電結構，其中該凸塊下金屬層包含：
    　　一第一導體層，設置於該第二開口內並與該襯墊電性連接；以及
    　　一第二導體層，設置於該第一導體層上並與該第一導體層電性連接。
  9. 如請求項8所述之導電結構，其中該第一導體層係為一鈦、鎢、釩或其合金所製成。
  10. 如請求項8所述之導電結構，其中該第二導體層係為金、銅、銀或其合金所製成。
  11. 一種導電結構之形成方法，包含：
    　　形成一圖案化絕緣層於一半導體晶片之一保護層上並局部且直接覆蓋於一襯墊之一第一開口上，以使該襯墊暴露出一第二開口，該第一開口大於該第二開口，其中該半導體晶片包含一半導體基材、一襯墊及一保護層，該襯墊設置於該半導體基材上，該保護層設置於該半導體基材及該襯墊上，以使該襯墊暴露出該第一開口；
    　　形成一凸塊下金屬層(Under Bump Metal, UBM)，覆蓋該圖案化絕緣層及該第二開口以與該襯墊電性連接；
    　　形成一導電凸塊於該第二開口中以與該凸塊下金屬層電性連接，其中該凸塊下金屬層包覆該導電凸塊之一周圍；以及
    　　去除該凸塊下金屬層位於該第二開口外之一外部區域層，使該導電凸塊之一上表面高於該凸塊下金屬層之一上表面，且該導電凸塊位於該第二開口內之區域係被該凸塊下金屬層所包覆。
  12. 如請求項11所述之形成方法，其中形成一圖案化絕緣層之步驟更包含固化(cured)該圖案化絕緣層之步驟。
  13. 如請求項11所述之形成方法，其中該導電凸塊之該上表面高於該圖案化絕緣層之該上表面約2至5微米。
  14. 如請求項11所述之形成方法，其中該導電凸塊係為電鍍方式所製成。
  15. 如請求項11所述之形成方法，其中形成一凸塊下金屬層之步驟包含：
    　　形成一第一導體層以覆蓋該圖案化絕緣層及該第二開口並與該襯墊電性連接；以及
    　　形成一第二導體層以覆蓋該第一導體層並與該第一導體層電性連接。
  16. 如請求項11所述之形成方法，其中去除該凸塊下金屬層之一外部區域層之步驟係藉由一研磨法(Lapping)一電漿蝕刻法(Plasma Etching)以及一化學機械研磨法(Chemical Mechanical Polishing, CMP)其中之一。
TW100142186A 2011-11-18 2011-11-18 導電結構及其形成方法 TWI502691B (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
TW100142186A TWI502691B (zh) 2011-11-18 2011-11-18 導電結構及其形成方法
CN201210052495.3A CN103123917B (zh) 2011-11-18 2012-02-13 导电结构及其形成方法
US13/654,710 US8872336B2 (en) 2011-11-18 2012-10-18 Conductive structure and method for forming the same
US14/494,026 US9159685B2 (en) 2011-11-18 2014-09-23 Conductive structure and method for forming the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW100142186A TWI502691B (zh) 2011-11-18 2011-11-18 導電結構及其形成方法

Publications (2)

Publication Number Publication Date
TW201322379A true TW201322379A (zh) 2013-06-01
TWI502691B TWI502691B (zh) 2015-10-01

Family

ID=48426015

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100142186A TWI502691B (zh) 2011-11-18 2011-11-18 導電結構及其形成方法

Country Status (3)

Country Link
US (2) US8872336B2 (zh)
CN (1) CN103123917B (zh)
TW (1) TWI502691B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11024593B2 (en) 2018-09-28 2021-06-01 Taiwan Semiconductor Manufacturing Co., Ltd. Metal bumps and method forming same

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10008461B2 (en) 2015-06-05 2018-06-26 Micron Technology, Inc. Semiconductor structure having a patterned surface structure and semiconductor chips including such structures
CN111508919A (zh) * 2019-01-31 2020-08-07 联华电子股份有限公司 半导体装置及半导体装置的制作方法
JP7319808B2 (ja) 2019-03-29 2023-08-02 ローム株式会社 半導体装置および半導体パッケージ
CN111682006A (zh) * 2020-07-09 2020-09-18 江苏纳沛斯半导体有限公司 一种半导体封装结构及其制造方法
CN116487358A (zh) * 2022-01-13 2023-07-25 长鑫存储技术有限公司 半导体结构及其制备方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6103552A (en) * 1998-08-10 2000-08-15 Lin; Mou-Shiung Wafer scale packaging scheme
JP2003203940A (ja) 2001-10-25 2003-07-18 Seiko Epson Corp 半導体チップ及び配線基板並びにこれらの製造方法、半導体ウエハ、半導体装置、回路基板並びに電子機器
TW525284B (en) * 2002-03-01 2003-03-21 Advanced Semiconductor Eng Bump process
KR100659527B1 (ko) * 2003-10-22 2006-12-20 삼성전자주식회사 3차원 범프 하부 금속층을 갖는 플립 칩 본딩용 반도체칩과 그 실장 구조
KR100630736B1 (ko) * 2005-01-28 2006-10-02 삼성전자주식회사 반도체 소자의 범프 및 제조 방법
JP2007227874A (ja) * 2006-01-30 2007-09-06 Fujitsu Ltd 薄膜キャパシタ及びその製造方法
KR100835277B1 (ko) * 2006-11-23 2008-06-05 삼성전자주식회사 희생 양극을 갖는 전자 장치의 제조방법 및 그에 의해제조된 전자 장치
TWI337386B (en) * 2007-02-16 2011-02-11 Chipmos Technologies Inc Semiconductor device and method for forming packaging conductive structure of the semiconductor device
US8669658B2 (en) 2007-07-24 2014-03-11 Taiwan Semiconductor Manufacturing Company, Ltd. Crosstalk-free WLCSP structure for high frequency application
CN101969053B (zh) * 2008-05-16 2012-12-26 精材科技股份有限公司 半导体装置及其制造方法
TWI393197B (zh) * 2008-07-16 2013-04-11 Chipmos Technoligies Inc 晶片封裝

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11024593B2 (en) 2018-09-28 2021-06-01 Taiwan Semiconductor Manufacturing Co., Ltd. Metal bumps and method forming same
TWI739163B (zh) * 2018-09-28 2021-09-11 台灣積體電路製造股份有限公司 積體電路結構及其形成方法

Also Published As

Publication number Publication date
US9159685B2 (en) 2015-10-13
US20150011082A1 (en) 2015-01-08
TWI502691B (zh) 2015-10-01
US20130127047A1 (en) 2013-05-23
CN103123917A (zh) 2013-05-29
US8872336B2 (en) 2014-10-28
CN103123917B (zh) 2015-08-05

Similar Documents

Publication Publication Date Title
TWI451545B (zh) 凸塊墊結構及其製造方法
US9515038B2 (en) Electrical connection for chip scale packaging
TWI502691B (zh) 導電結構及其形成方法
CN101728347B (zh) 封装结构及其制造方法
US10068861B2 (en) Semiconductor device
US8729700B2 (en) Multi-direction design for bump pad structures
KR20010029196A (ko) 범프 패드에 오목 패턴이 형성된 재배치 웨이퍼 레벨 칩 사이즈 패키지 및 그 제조방법
JP2012069704A (ja) 半導体装置及びその製造方法
TWI576974B (zh) Semiconductor device and method for manufacturing semiconductor device
TWI463621B (zh) 封裝基板結構及其製法
US9524944B2 (en) Method for fabricating package structure
TW200917392A (en) Semiconductor device and method of bump formation
TWI419284B (zh) 晶片之凸塊結構及凸塊結構之製造方法
US7381636B2 (en) Planar bond pad design and method of making the same
JP2007157963A (ja) 半導体装置の製造方法及び半導体装置
CN105229781B (zh) 使用电介质桥接器的电镀方法和电镀结构
US8426303B2 (en) Manufacturing method of semiconductor device, and mounting structure thereof
TWI470708B (zh) 電子元件封裝體及其製作方法
TWM629323U (zh) 覆晶封裝結構
WO2016139794A1 (ja) 半導体装置および半導体装置の製造方法
US8476760B2 (en) Electroplated posts with reduced topography and stress
JP2010182952A (ja) 半導体装置及びその製造方法
TWI599006B (zh) 凸塊底層金屬化層結構及其形成方法和重佈金屬化層結構
TWI399839B (zh) 內置於半導體封裝構造之中介連接器
TWI339416B (en) Method of forming conductive bumps with different diameters