TWI739163B - 積體電路結構及其形成方法 - Google Patents

積體電路結構及其形成方法 Download PDF

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TWI739163B
TWI739163B TW108135089A TW108135089A TWI739163B TW I739163 B TWI739163 B TW I739163B TW 108135089 A TW108135089 A TW 108135089A TW 108135089 A TW108135089 A TW 108135089A TW I739163 B TWI739163 B TW I739163B
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Taiwan
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polymer layer
layer
integrated circuit
metal pad
opening
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TW108135089A
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TW202025320A (zh
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鄭明達
趙永清
曾俊凱
林政仁
康金瑋
陳玉芬
李明機
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台灣積體電路製造股份有限公司
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Abstract

一種形成積體電路結構的方法，包括：在金屬墊上形成圖案化保護層，金屬墊的頂面透過圖案化保護層中的第一開口露出，以及在圖案化保護層上方塗覆聚合物層。聚合物層基本上不含N-甲基-2-吡咯啶酮(NMP)，而是包括脂肪族醯胺作為溶劑。此方法更包括：在聚合物層上進行曝光製程，在聚合物層上進行顯影製程以形成聚合物層中的第二開口，其中金屬墊頂面透過第二開口露出，烘烤聚合物，以及形成具有導孔部分(via portion)延伸進入第二開口的導電區。

Description

積體電路結構及其形成方法
本發明實施例是關於半導體元件的形成方法，特別是關於凸塊金屬的輪廓結構。
在積體電路的形成中，如電晶體的元件在晶圓中的半導體基底表面形成。互連結構接著形成在積體電路元件上。金屬墊形成於互連結構上方，並電性耦合至互連結構。保護層和第一聚合物層形成在金屬墊上方，其金屬墊透過保護層和第一聚合層的開口露出。
重分佈線隨後形成以連接金屬墊，接著是於重分佈線上方的第二聚合物層的形成。形成凸塊下金屬層，並延伸進入第二聚合物層中的開口。凸塊下金屬層電性連接至重分佈線。金屬柱可以形成在凸塊下金屬層上。然後，焊球置於凸塊下金屬層上方，並被回焊。
本發明實施例提供一種積體電路結構的形成方法，方法包括：在金屬墊上形成圖案化保護層，金屬墊之頂面透過圖案化保護層的第一開口而露 出；在圖案化保護層上塗覆聚合物層，其中聚合物層基本上不含N-甲基-2-吡咯啶酮(NMP)，其中聚合物層包括脂肪族醯胺(aliphatic amide)作為溶劑；在聚合物層上進行曝光製程；在聚合物層上進行顯影製程以形成聚合物層的第二開口，其中金屬墊之頂面透過第二開口而露出；烘烤聚合物；以及形成導電區，導電區包括導孔部分(via portion)延伸進入第二開口。
本發明實施例提供一種積體電路結構的形成方法，其中導孔部分包括：筆直側壁；筆直底面；以及圓角，包括連接至筆直側壁的頂端和連接至筆直底面的底端，其中圓角具有小於4μm的R角。
本發明實施例提供一種積體電路結構的形成方法，方法包括：在金屬墊上塗覆聚合物層；圖案化聚合物層以形成聚合物層的開口，其中金屬墊之頂面露出於開口，聚合物層包括：筆直側壁面向開口，以及圓角，包括連接至筆直側壁的頂端和連結(join)至金屬墊之頂面的底端，其中圓角面具有小於約4μm的R角；以及形成導電區，包括：導孔部分，延伸進入該開口，以及凸塊部分，於聚合物層上方。
本發明實施例提供一種積體電路結構，包括：金屬墊；聚合物層，於金屬墊上並接觸金屬墊；以及金屬凸塊，包括：導孔部分，於聚合物層中，其中導孔部分包括：筆直側壁，筆直底面，以及圓底角，包括連接至筆直側壁的頂端和連接至筆直底面的底端，其中圓角具有小於約4μm的R角，以及凸塊部分，於聚合物層上方並連結至導孔部分。
20:封裝體，元件晶圓，中介結構晶圓，封裝基底條
22:封裝體
24:半導體基底
26:積體電路元件
28:層間介電層
30:接觸插塞
32:互連結構
34:金屬線
36:導孔
37:導孔，金屬部件
38:金屬間介電層，低k介電層
39:頂介電層
42:金屬墊
42A:頂面
44:圖案化保護層
46:(第一)開口
48:介電層，聚合物層
48A:筆直側壁
48B:圓滑側壁
48C:頂面
50:微影遮罩
50A:不透明部分
50B:透明部分
52:(第二)開口
54:晶種層
56:電鍍遮罩
58:金屬凸塊，開口
58A:導孔部分
58B:凸塊部分
60:含銅層
62:金屬蓋層
64:焊料區
65:焊料區
66:切割線
68:封裝體
70:導電部件
71:底部填充劑
72:封裝物
200:製程流程
202,204,206,208,210,212,214,216,218,220,222,224:製程步驟
H1:厚度，高度
H2:突起高度
W1:寬度
R角:圓圈直徑
θ:傾斜角度
以下將配合所附圖式詳述本揭露之各面向。應注意的是，依據在 業界的標準做法，各種特徵並未按照比例繪製。事實上，可任意地放大或縮小元件的尺寸，以清楚地表現出本揭露的特徵。
第1圖-第10圖是根據一些實施例繪示出封裝形成的中間階段的剖面示意圖。
第11圖是根據一些實施例繪示出部分金屬凸塊的放大剖面示意圖。
第12圖是根據一些實施例繪示出部分金屬凸塊的俯視圖。
第13圖至第16圖是根據一些實施例的模擬結果。
第17圖是根據一些實施例繪示出金屬凸塊側壁的傾斜角度和金屬凸塊稜角的R角之間的關聯性。
第18圖是根據一些實施例繪示出金屬凸塊側壁的傾斜角度和曝光焦點之間的關聯性。
第19圖是根據一些實施例繪示出形成封裝的製程流程圖。
以下揭露提供了許多的實施例或範例，用於實施本發明的不同部件。組件和配置的具體範例描述如下，以簡化本發明實施例。當然，這些僅僅是範例，並非用以限定本發明實施例。舉例來說，敘述中提及第一部件形成於第二部件之上，可包括形成第一和第二部件直接接觸的實施例，也可包括額外的部件形成於第一和第二部件之間，使得第一和第二部件不直接接觸的實施例。另外，本發明可在各種範例中重複元件符號及/或字母。這樣重複是為了簡化和清楚的目的，其本身並非主導所討論各種實施例及/或配置之間的關係。
再者，此處可使用空間上相關的用語，如「在...之下」、「下方的」、「低於」、「在...上方」、「上方的」、「高於」和類似用語可用於此， 以便描述如圖所示一元件或部件和其他元件或部件之間的關係。這些空間用語除了包括圖式繪示的方位外，也企圖包括使用或操作中的裝置的不同方位。當裝置被轉至其他方位(旋轉90°或其他方位)，則在此所使用的空間相對描述可同樣依旋轉後的方位來解讀。
根據一些實施例提供積體電路和其形成方法。積體電路結構形成的中間階段是根據一些實施例所繪示。一些實施例中的變化會被討論。在所有視圖和例示性實施例中，類似元件符號會用來標示類似元件。根據本發明實施例，金屬凸塊的形成包括導孔部分(via portion)和在其上方的凸塊部分(bump portion)。導孔部分延伸進入聚合物層以連接在聚合物層下方的導電部件，如金屬墊。導孔部分的輪廓包括寬度、高度、傾斜角度、以及R角，會做調整以減少對在聚合物層下方的低k(低介電常數)介電層所造成的應力。聚合物層的材料也會做調整以達到導孔部分所欲之輪廓。
第1圖至第10圖是根據本發明的一些實施例繪示出包括金屬凸塊的積體電路結構形成方法的中間階段的剖面示意圖。對應製程也在第19圖所示的製程流程200以示意圖反映出來。
第1圖繪示出封裝體20的剖面示意圖。根據本發明的一些實施例，封裝體20是包括主動元件和可包括被動元件的元件晶圓，其以積體電路元件26表示。元件晶圓20中可包括多個封裝體22，其中一個封裝體22以示意圖繪示出。根據本發明的替代實施例，封裝體20是中介結構晶圓，不包括主動元件，可包括也可不包括被動元件，如電感、電阻、電容等。根據本發明的其他替代實施例，封裝體20是封裝基底條(package substrate strip)，包括無芯封裝基底或內含芯封裝基底。在後續的討論，是以元件晶圓作為封裝體20的範例進行討 論。本發明的實施例也可以套用在中介結構晶圓、封裝基底、封裝物等。
根據本發明的一些實施例，晶圓20包括半導體基底24和在半導體基底24頂面形成的部件。半導體基底24可是以結晶矽、結晶鍺、鍺化矽、或三五族半導體化合物，如磷砷化鎵、砷化鋁銦、砷化鋁鎵、砷化鎵銦、磷化鎵銦、砷磷化鎵銦、或其他類似化合物所形成。半導體基底24也可是塊狀半導體基底或是絕緣層上半導體基底。淺溝槽隔離區(未繪出)可在半導體基底24中形成以隔離半導體基底24中的主動區。雖然未被繪出，貫穿導孔可形成以延伸進入半導體基底24，其中貫穿導孔被用來電性互耦晶圓20正反兩面的部件。
根據本發明的一些實施例，晶圓20包括積體電路元件26，其形成於半導體基底24頂面上。根據一些實施例，積體電路元件26可包括互補式金屬氧化物半導體電晶體、電阻、電容、二極體、和其他類似元件。積體電路元件26的細節沒有在此繪示。根據本發明的替代實施例，晶圓20是用來形成中介結構，而基底24可以是半導體基底或是介電基底。
層間介電層28形成在半導體基底24上方，並將積體電路元件26中的電晶體閘極堆疊(未繪出)之間的空間填滿。根據本發明的一些實施例，層間介電層28是以磷酸矽酸鹽玻璃、硼酸矽酸鹽玻璃、硼摻雜磷酸矽酸鹽玻璃、氟摻雜矽酸鹽玻璃、四乙氧基矽烷、或其他類似材料所形成。層間介電層28可用旋轉塗布、流動性化學氣相沉積、或其他類似方法所形成。根據本發明的一些實施例，層間介電層28是用電漿輔助化學氣相沉積、低壓化學氣相沉積、或其他類似沉積方法所形成。
接觸插塞30形成在層間介電層28中，並用來將積體電路元件26電性連接到在層間介電層28上方的金屬線和導孔。根據本發明的一些實施例，接 觸插塞30是以導電材料形成，其導電材料選自鎢、鋁、銅、鈦、鉭、氮化鈦、氮化鉭、其合金、及/或其多層膜。接觸插塞30的形成可包括在層間介電層28中形成接觸開口，以一或多個導電材料將接觸開口填滿，和進行平坦化製程(如化學機械拋光製程或機械研磨製程)使接觸插塞30頂面和層間介電層28頂面齊平。
於層間介電層28和接觸插塞30之上可有互連結構32。互連結構32包括金屬線34和導孔36，其形成在介電層38(也被稱為金屬間介電層)中。同一水平上的金屬線以下被統稱為金屬層。根據本發明的一些實施例，互連結構32包括多個金屬層，其包括金屬線34，並透過導孔36相互連接。金屬線34和導孔36可以鋁或鋁合金所形成，也可以其他金屬所形成。根據本發明的一些實施例，介電層38是以低k介電材料所形成。舉例來說，低k介電材料的介電常數(k值)可低於約3.0。介電層38可以含碳低k介電材料、氫矽酸鹽(Hydrogen SilsesQuioxane)、甲基矽酸鹽(MethylSilsesQuioxane)、或其他類似材料所形成。根據本發明的一些實施例，介電層38的形成包括沉積含造孔劑介電材料，然後進行固化製程將造孔劑驅出，而後剩餘的介電層38是多孔性。
金屬線34、導孔36、和介電層38的形成製程可包括單鑲嵌製程及/或雙鑲嵌製程。在單鑲嵌製程中，先在其中一個介電層38形成溝槽，接著以導電材料將溝槽填滿。再進行平坦化製程，如化學機械拋光製程或機械研磨製程，以移除高於各層間介電層的導電材料多餘部分，留下在溝槽中的金屬線。在雙鑲嵌製程中，溝槽和導孔開口均形成在金屬間介電層中，其導孔開口在溝槽下方並連接至溝槽。然後，以導電材料將溝槽和導孔開口填滿，以分別形成金屬線和導孔。導電材料可包括擴散阻隔層和於擴散阻隔層上方的含銅金屬材料。 擴散阻隔層可包括鈦、氮化鈦、鉭、氮化鉭、或其他類似材料。
晶圓20更包括頂導電(金屬)部件，如金屬線、金屬墊、或導孔(以37表示)於頂介電層39中。根據本發明的一些實施例，介電層39是以低k介電材料所形成，其材料與底下的介電層38所使用的材料類似。根據本發明的其他實施例，介電層39是以非低k介電材料所形成，其材料包括氮化矽、未摻雜矽玻璃、氧化矽、或其他類似材料。介電層39也可有多層結構包括，例如，兩層未摻雜矽玻璃和位在其之間的一層氮化矽。介電層39有時被稱為保護層。頂金屬部件也可以鋁或鋁合金形成，並可有雙鑲嵌結構或單鑲嵌結構。
金屬墊42形成於金屬部件37上方並與其接觸。個別製程繪示於第19圖的製程流程200中的製程202。繪示出的金屬墊42代表在同一水平上的多個金屬墊。金屬墊42可透過導電部件，如金屬線34和導孔36，電性耦合至積體電路元件26。根據本發明的一些實施例，金屬墊42是鋁墊或是鋁銅墊，其他金屬材料也可被使用。根據本發明的一些實施例，金屬墊42具有大於約95%的鋁百分比。
圖案化保護層44形成在金屬墊42上。個別製程繪示於第19圖的製程流程200中的製程204。保護層44的某些部份可覆蓋金屬墊42的邊緣部分，而金屬墊42頂面的中間部分則透過開口46所露出。根據本發明的一些實施例，開口46是在蝕刻製程中蝕刻保護層44所形成。保護層44可是單膜層或是複合層，並可以無孔材料所形成。根據本發明的一些實施例，保護層44是複合層，包括氧化矽層和位於氧化矽層上方的氮化矽層。
第2圖繪示了介電層48的應用。個別製程繪示於第19圖的製程流程200中的製程206。根據本發明的一些實施例，介電層48是以稀釋於溶劑中的 聚合物所形成。介電層48的形成可包括旋轉塗佈聚合物層48和前烘烤聚合物層48，使其在後續曝光製程和顯影製程可以維持其形狀。根據本發明的一些實施例，前烘烤是在介於約100℃和180℃的溫度範圍中進行。前烘烤的持續時間可介於約2分鐘和10分鐘之間。
根據本發明的一些實施例，作為慣用溶劑的N-甲基-2-吡咯啶酮(NMP)被脂肪族醯胺(aliphatic amide)取代，當介電層48中形成開口時，所欲之輪廓(第3圖和第11圖)得以產生。根據本發明的一些實施例，塗布完的介電層48(當塗布完後而於烘烤前)不含NMP。根據本發明的替代實施例，塗布完的介電層48(當塗布完後而於烘烤前)基本上不含NMP，例如，包括具有小於約0.3%，或小於約0.1%的NMP的重量百分比。可以理解的是，有些用來偵測聚合物成份的分析儀器可偵測到高於特定值(如0.3%)的化學品(如NMP)濃度，但是卻沒有具有偵測小於約0.3% NMP濃度的準確度。
另外，為了適應脂肪族醯胺作為溶劑的使用，塗布完的聚合物48也可包括其他如烷氧基癸烷(alkoxy decane)的添加劑。烷氧基癸烷也是聚合物。如此一來，所得的聚合物可包括矽氧烷(其化學式為Si(OR)n)，可以用傅立葉轉換紅外線(Fourier transform Infrared)和氣相層析質譜儀(Gas Chromatography Mass Spectrometry)所偵測。根據本發明的一些實施例，塗布完的介電層48中的烷氧基癸烷具有大於約0.1%的重量百分比(排除溶劑)。矽氧烷的重量百分比可以被偵測到，並可介於約0.1%和10%的範圍之間。
第2圖也繪示了介電層48的曝光製程，其製程使用微影遮罩50所進行。個別製程繪示於第19圖的製程流程200中的製程208。微影遮罩50包括不透明部分50A以阻擋曝光所使用的光線，以及透明部分50B允許光線通過，以曝 光選定部分的介電層48。
曝光完成後，接著進行顯影製程，使開口52形成在介電層48中，如第3圖所示。個別製程繪示於第19圖的製程流程200中的製程208。金屬墊42頂面於開口52露出。
顯影製程完成後，接著進行主烘烤製程，也是固化製程，以固化介電層48。個別製程繪示於第19圖的製程流程200中的製程210。根據本發明的一些實施例，主烘烤製程在溫度介於約200℃和400℃的範圍之間進行。主烘烤的持續時間可介於約1小時和12小時的範圍之間。可以觀察到的是，傾斜角度θ(第11圖)與烘烤溫度有關聯，而溫度越高導致傾斜角度θ越大，反之亦然。於是，烘烤溫度是為了調整傾斜角度θ而進行調整。舉例來說，傾斜角度θ可在大於約45°和小於90°的範圍之間，可以透過前烘烤溫度介於約120℃和210℃的範圍之間來達成。傾斜角度θ也可在約70°和80°的範圍之間，可以透過前烘烤溫度介於約140℃和160℃的範圍之間來達成。另外，根據一些實施例，藉由增加在用來做介電層48的曝光製程的機台的曝光焦點可增加傾斜角度θ。所欲之傾斜角度θ可以藉由調整曝光焦點至適當值來達成，其適當值可以透過實驗發現。
在烘烤製程中，介電層48收縮，其厚度減少。第11圖繪示了開口52的放大示意圖，其開口52被後續製程中金屬凸塊58的導孔部分58A所填滿。如第11圖所示，主烘烤製程完成後，介電層48具有H1的厚度，是介電層48位在金屬墊42和保護層44正上方部份的厚度。根據本發明的一些實施例，厚度H1等於或大於約5μm，並可在介於約5μm和15μm的範圍之間。如後續段落所討論，將厚度H1調整至等於或大於約5μm對於減少低k介電層38(第3圖)中的應力至沒有裂縫在低k介電層38中產生的程度極為關鍵。金屬凸塊58的導孔部分58A接觸 金屬墊42以形成介面，其介面具有寬度W1。寬度W1也是開口52的底寬度，如第3圖所示。根據本發明的一些實施例，寬度W1等於或小於約20μm，並可在介於約8μm和20μm的範圍之間。如後續段落所討論，將寬度W1設在等於或小於約20μm對於減少低k介電層38中的應力至沒有裂縫在低k介電層38中產生的程度極為關鍵。
在剖面示意圖中，如第11圖所示，介電層48有筆直側壁48A，以及連接至筆直側壁48A的圓滑側壁48B。圓滑側壁48B也連接至金屬墊42的頂面42A，其頂面也形成第3圖中開口52的底面。圓滑側壁48B形成具有R角的部分圓圈，R角是圓滑側壁48B所嵌合的圓圈的直徑。根據本發明的一些實施例，R角小於約4μm。再者，R角大於0μm，並可大於約1μm。根據本發明的一些實施例，R角是在介於約1μm和3μm的範圍之間。如後續段落將被討論，將R角設在等於或小於約4μm對於減少低k介電層38中的應力至沒有裂縫在低k介電層38中產生的程度極為關鍵。
筆直側壁48A可具有傾斜角度θ，是筆直側壁48A和水平面(與晶片22頂面和底面平行)之間形成的銳角。根據本發明的一些實施例，傾斜角度θ在介於約45°和90°的範圍之間。如後續段落將被討論，將傾斜角度θ設在介於約45°和90°的範圍之間對於減少低k介電層38中的應力至沒有裂縫在低k介電層38中產生的程度極為關鍵。
根據一些實施例，如第4圖所示，由於採用脂肪族醯胺和烷氧基癸烷溶劑，介電層48的頂面48C可在介電層48和筆直側壁48A連結的區域突起。在距離開口52較遠的區域，介電層48的頂面48C較為平坦。根據本發明的一些實施例，突起高度H2(也被稱為頂高度)小於1.5μm，並可在介於約0.5μm和1.5μm 的範圍之間。突起的頂面48C用虛線所繪示。介電層48的頂面也有在介電層48和筆直側壁48A連結的區域維持平坦的可能，如第4圖的實線所示(也在第3圖中所示)。第5圖至第10圖沒有繪示頂面的突起，雖然這些圖的頂面也可突起。
第5圖至第9圖繪示了金屬凸塊的形成。根據本發明的一些實施例，形成金屬凸塊以與金屬墊42接觸。根據本發明的替代實施例，額外導線和可能的介電層於金屬墊42上方，並在金屬凸塊下方形成。舉例來說，可有重分佈線(有時被稱為後保護層互連結構)和聚合物層的形成，聚合物層中的後保護層互連結構將金屬墊42與在聚合物層上方的金屬凸塊做互連。
參考第5圖，晶種層54沉積在介電層48上方。晶種層54是導電晶種層，根據一些實施例，可是金屬晶種層。個別製程繪示於第19圖的製程流程200中的製程212。根據本發明的一些實施例，晶種層54是包括2或3層的複合層。舉例來說，晶種層54可包括下層和上層，其中下層可包括鈦層、氮化鈦層、鉭層、氮化鉭層、或其他類似材料。上層的材料可包括銅或銅合金。根據替代實施例，晶種層54是單膜層，舉例來說，可是銅層。晶種層54可用物理氣相沉積、電漿輔助化學氣相沉積、原子層沉積等所形成，其他適用的方法也可使用。晶種層54是延伸進入開口52的順應層。
第6圖繪示了圖案化電鍍遮罩56的形成。個別製程繪示於第19圖的製程流程200中的製程214。根據本發明的一些實施例，電鍍遮罩56是以光阻所形成。電鍍遮罩56被圖案化以形成開口58，而〝露出〞一部份的晶種層54。電鍍遮罩56的圖案化可包括曝光製程和顯影製程。
接著，參考第7圖，進行電鍍製程以形成金屬凸塊58。個別製程繪示於第19圖的製程流程200中的製程216。金屬凸塊58可包括一或多個非焊金 屬層。舉例來說，金屬凸塊58可包括含銅層60，其包括銅或銅合金。金屬凸塊58也可包括金屬蓋層62於含銅層60上方。金屬蓋層62可是含鎳層、含鈀層、金層、及/或其他類似材料，或包括上述層的複合層。
在金屬凸塊58頂端上，以例如電鍍形成焊料區64。個別製程繪示於第19圖的製程流程200中的製程216。焊料區64可以錫銀合金、錫銀銅合金、或其他類似材料所形成，也可以是無鉛或是含鉛。在後續製程，電鍍遮罩56在剝除製程中被移除，露出晶種層54在遮罩下方的部分。個別製程繪示於第19圖的製程流程200中的製程218。舉例來說，當電鍍遮罩56以光阻所形成，電鍍遮罩56可以用氧灰化。接著，先前被電鍍遮罩56覆蓋，因其灰化而露出的部分晶種層54，透過蝕刻被移除，舉例來說，用低於大氣壓力的純氫輝光電漿(pure hydrogen glow plasma)以蝕刻銅。氮氫混合物或氯氬混合物可以被用作製程氣體。鈦，如果包括在晶種層，可以被含氟氣體，如六氟化硫、或四氟化碳、或三氟化氮，進行蝕刻。晶種層54在被金屬凸塊58所覆蓋的部分保持不被移除。個別製程繪示於第19圖的製程流程200中的製程218。所得的結構於第8圖所示。在全文中，晶種層54的剩餘部分被視為金屬凸塊58的一部份。金屬凸塊58包括延伸進入介電層48的導孔部分58A，和高於介電層48頂面的凸塊部分58B。金屬凸塊58的凸塊部分58B側壁基本上可是垂直及筆直。導孔部分58A的輪廓細節可以參考第11圖所示的輪廓。
參考第9圖，焊料區64在回焊製程中被回焊，例如，對流回焊製程、雷射回焊製程、或其他類似方法。個別製程繪示於第19圖的製程流程200中的製程220。焊料區64因而具有圓化表面。
第12圖繪示了金屬凸塊58的俯視圖。根據本發明的一些實施例， 導孔部分58A和凸塊部分58B均具有長條狀。在此情況下，寬度W1(也參考第4圖和第11圖)是導孔部分58A的較小寬度(在寬度方向)。根據本發明的替代實施例，金屬凸塊58可具有非長條俯視形狀，其長軸和短軸之間不具有明顯的差異。舉例來說，俯視形狀可是圓狀，寬度W1則是圓狀的直徑。導孔部分58A和凸塊部分58B的俯視形狀也可是六角形，寬度W1則是對應六角形兩平行邊之間的距離。開口46(第1圖)的形狀也繪示在第12圖。
參考回第9圖，晶圓20於晶粒切割製程中被單粒化。單粒化是沿著切割線66進行。個別製程繪示於第19圖的製程流程200中的製程222。封裝體22(可是元件晶粒、封裝基底、中介結構、封裝物、或其他類似結構)因而與彼此分開以形成分離的封裝體。
接著，參考第10圖，其中一個封裝體22被接合至封裝體68，封裝體68可是中介結構、封裝基底、封裝物、元件晶粒、印刷電路板、或其他類似結構。個別製程繪示於第19圖的製程流程200中的製程224。可以透過焊料區65進行接合，焊料區65包括焊料區64(第9圖)的材料。焊料區65可包括或可不包括從焊料區進行額外焊接於封裝體68中的導電部件70上。底部填充劑71可置於封裝體22和封裝體68之間的空隙中。底部填充劑71可接觸介電層48的頂面，並可接觸凸塊部分58B的側壁。再者，底部填充劑71可圍繞金屬凸塊58，並與金屬凸塊58接觸。封裝物72因而形成。
當低k介電層38的應力增加到約150MPa，低k介電層38被發現到可能破裂。當低k介電層38的應力低於150MPa，低k介電層38則不會破裂。於是，進行多個模擬，以決定某些變因對低k介電層38的應力所造成的影響。模擬結果在第13、14、15、16、17圖所繪示。
在第13圖所繪示的模擬結果中，低k介電層38(第10圖)的應力被繪示為金屬凸塊58的導孔部分58A的寬度W1(第11圖)的函數。X軸代表寬度W1，Y軸代表低k介電層38的應力。第13圖顯示出，隨著寬度W1的增加，低k介電層38的應力增加。當寬度W1達到約20μm或更大，應力則增加到臨界值或更高。這表示當寬度W1小於20μm時，低k介電層38不會破裂，當寬度W1大於約20μm時，則有破裂的可能性。於是，減少寬度W1導致所欲之低k介電層38的應力減少，寬度W1的設計要小於約20μm。
第14圖繪示了模擬結果，其中低k介電層38(第10圖)的正規化應力被繪示為導孔部分58A的寬度W1(第11圖)的函數。X軸代表寬度W1，Y軸代表低k介電層38的正規化應力，其正規化應力為低k介電層38的應力和臨界值(150MPa)的比例。與第13圖類似，第14圖顯示出，隨著寬度W1的增加，低k介電層38的應力增加。當寬度W1達到約20μm，正規化應力增加到1.0。第14圖也顯示出，減少寬度W1導致所欲之低k介電層38的應力減少，寬度W1的設計要小於約20μm。
第15圖繪示了模擬結果，其中低k介電層38(第10圖)的應力被繪示為金屬凸塊58的導孔部分58A的高度H1(第11圖)的函數。X軸代表以微米為單位的高度H1，Y軸代表低k介電層38的正規化應力。第15圖顯示出，隨著高度H1的增加，低k介電層38的應力減少。當高度H1增加到約5μm或更高，正規化應力減少到臨界值1.0或更低，表示低k介電層38不太會破裂。於是，增加高度H1導致所欲之低k介電層38的應力減少，高度H1的設計要大於約5μm。
第16圖繪示了模擬結果，其中低k介電層38(第10圖)的應力被繪示為導孔部分58A的筆直側壁48A(第11圖)的傾斜角度θ的函數。X軸代表傾 斜角度θ，Y軸代表低k介電層38的正規化應力，其正規化至臨界值(150MPa)。第16圖顯示出，隨著傾斜角度θ的增加，低k介電層38的應力減少。當傾斜角度θ大於約45°，正規化應力減少到臨界值1.0，表示低k介電層38不會破裂。於是，增加傾斜角度θ導致所欲之低k介電層38的應力減少，傾斜角度θ的設計要大於約45°。另一方面，傾斜角度θ不能大於90°，因為如此會對順應性晶種層54的形成(第5圖)造成困難，並在後續金屬凸塊58的電鍍造成問題(如孔洞)。根據本發明的一些實施例，傾斜角度θ是在約70°和80°的範圍之間。
第17圖繪示了R角和傾斜角度θ的關聯性。X軸代表傾斜角度θ，Y軸代表R角。隨著傾斜角度θ的增加，R角被發現到會減少。如前所述，增加傾斜角度θ及/或減少R角可以減少低k介電層38的應力，反之亦然。於是，第17圖顯示出，減少傾斜角度θ和增加R角有著類似的影響，反之亦然。第17圖所示的關聯性也可以被反映為：R角=0.0152θ2-0.5863θ+4.3865 [式一]
如第13、14、15、16、17圖所示，低k介電層38應力的減少可以透過減少R角、減少金屬凸塊58的導孔部分的寬度W1、增加介電層48的厚度H1、以及增加傾斜角度θ所達成。模擬結果顯示出，當寬度W1(第11圖)小於約20μm、高度H1大於約5μm、以及傾斜角度大於約45°(和小於90°)，金屬凸塊58和介電層48所施加在低k介電層的應力不會造成裂縫。
第18圖繪示了傾斜角度θ和在第2圖所示的製程中於介電層48(當介電層48為光敏感層)上進行曝光的曝光焦點之間的關係。可以理解的是，第18圖繪示了一個範例，而當使用不同的曝光機台時，此關係可會不同。如第18圖所示，根據一些實施例，藉由增加曝光焦點，輪廓的角度可增加。
本發明的實施例有一些有利的特徵。藉由調整塗覆聚合物的成份，金屬凸塊的導孔部分輪廓，其輪廓包括金屬凸塊的導孔部分底寬度W1、聚合物的厚度、金屬凸塊的導孔部分側壁的傾斜角度θ，被調整至所欲之輪廓，使在聚合物層底下的低k介電層的應力減少，低k介電層的破裂得以被避免。
根據本發明的一些實施例，形成積體電路結構的方法包括：形成圖案化保護層於金屬墊之上，金屬墊頂層透過圖案化保護層中的第一開口而露出；塗覆聚合物層於圖案化保護層之上，其中聚合物層基本上不含NMP，其中聚合物層包括脂肪族醯胺作為溶劑；在聚合物層上進行曝光製程；在聚合物層上進行顯影製程以形成聚合物層中的第二開口，其中金屬墊頂層透過第二開口而露出；烘烤聚合物；以及形成導電區，包括導孔部分延伸進入第二開口。在一實施例，聚合物層包括烷氧基癸烷。在一實施例，導孔部分包括：筆直側壁；筆直底面；以及圓角，包括連接至筆直側壁的頂端和連接至筆直底面的底端，其中圓角具有小於約4μm的R角。在一實施例，筆直側壁具有介於約45°和90°之間的傾斜角度。在一實施例，筆直側壁具有介於約70°和80°之間的一傾斜角度。在一實施例，於烘烤製程後，聚合物層具有大於約5μm的厚度。在一實施例，當聚合物層被塗覆上，聚合物層中的NMP具有小於約0.3%的重量百分比。在一實施例，當聚合物層被塗覆上，聚合物層不含NMP。
根據本發明的一些實施例，形成積體電路結構的方法包括：塗覆聚合物層於金屬墊之上；圖案化聚合物層以形成聚合物層中的開口，其中金屬墊的頂面透過開口而露出，聚合物層包括：筆直側壁面對開口，圓角面包括連接至筆直側壁的頂端和連結(join)至金屬墊之頂面的底端，其中圓角面具有小於約4μm的R角；以及形成導電區，包括：導孔部分延伸進入開口，凸塊部分於 聚合物層之上。在一實施例，當聚合物層塗覆上時，聚合物層包括脂肪族醯胺作為溶劑。在一實施例，當聚合物層塗覆上時，聚合物層不含NMP。在一實施例，聚合物層包括矽氧烷。在一實施例，此方法更包括在聚合物層圖案化後，烘烤聚合物層。
根據本發明的一些實施例，積體電路結構包括：金屬墊；聚合物層於金屬墊上方並與金屬墊接觸；金屬凸塊，包括聚合物層中的導孔部分，其中導孔部分包括筆直側壁，筆直底面，以及圓底角包括連接至筆直側壁的頂端和連接至筆直底面的底端，其中圓底角具有小於約4μm的R角；以及凸塊部分於聚合物層之上，並連結至導孔部分。在一實施例，筆直側壁具有介於約45°和90°之間的傾斜角度。在一實施例，傾斜角度是介於約70°和80°之間。在一實施例，聚合物層包括矽氧烷。在一實施例，聚合物層於金屬墊正上方的部分具有大於約5μm的厚度。在一實施例，導孔部分接觸金屬墊頂面以形成介面，其介面具有小於約20μm的寬度。
以上概述數個實施例之部件，以便在本發明所屬技術領域中具有通常知識者可以更加理解本發明的觀點。在本發明所屬技術領域中具有通常知識者應理解，他們能輕易地以本發明實施例為基礎，設計或修改其他製程和結構，以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應理解，此類等效的結構並無悖離本發明的精神與範圍，且他們能在不違背本發明之精神和範圍下，做各式各樣的改變、取代和替換。
20:封裝體，元件晶圓，中介結構晶圓，封裝基底條
22:封裝體
24:半導體基底
26:積體電路元件
28:層間介電層
30:接觸插塞
32:互連結構
34:金屬線
36:導孔
38:金屬間介電層，低k介電層
42:金屬墊
44:圖案化保護層
48:介電層，聚合物層
48A:筆直側壁
48C:頂面，突起面
52:(第二)開口
H1:厚度，高度
H2:突起高度
W1:寬度

Claims (11)

  1. 一種積體電路結構的形成方法，該方法包括：在一金屬墊上形成一圖案化保護層，該金屬墊之一頂面透過該圖案化保護層的一第一開口而露出；在該圖案化保護層上塗覆一聚合物層，其中該聚合物層基本上不含N-甲基-2-吡咯啶酮(NMP)，其中該聚合物層包括脂肪族醯胺(aliphatic amide)作為溶劑；在該聚合物層上進行曝光製程；在該聚合物層上進行顯影製程以形成該聚合物層的一第二開口，其中該金屬墊之該頂面透過該第二開口而露出；烘烤該聚合物；以及形成一導電區，該導電區包括一導孔部分(via portion)延伸進入該第二開口，其中該導孔部分包括：一筆直側壁，其中該筆直側壁具有介於約70°和80°之間的一傾斜角度；一筆直底面；以及一圓角，包括連接至該筆直側壁的一頂端和連接至該筆直底面的一底端，其中該圓角具有小於約4μm且大於1μm的一R角。
  2. 如請求項1之積體電路結構的形成方法，其中該聚合物層包括烷氧基癸烷(alkoxy decane)。
  3. 如請求項1之積體電路結構的形成方法，其中該烘烤製程的溫度範圍介於約120℃和210℃之間。
  4. 如請求項1之積體電路結構的形成方法，其中在該烘烤製程後，該 聚合物層具有大於約5μm的一厚度。
  5. 如請求項1-4中任一項之積體電路結構的形成方法，其中當塗覆該聚合物層時，該聚合物層中的NMP的重量百分比小於約0.3%。
  6. 一種積體電路結構的形成方法，該方法包括：在一金屬墊上塗覆一聚合物層；圖案化該聚合物層以形成該聚合物層的一開口，其中該金屬墊之一頂面露出於該開口，該聚合物層包括：一筆直側壁面向該開口，其中該筆直側壁具有介於約70度和80度之間的一傾斜角度；以及一圓角，包括連接至該筆直側壁的一頂端和連結(join)至該金屬墊之該頂面的一底端，其中該圓角具有小於約4μm且大於1μm的一R角；以及形成一導電區，包括：一導孔部分，延伸進入該開口；以及一凸塊部分，於該聚合物層上方。
  7. 如請求項1-4、6中任一項之積體電路結構的形成方法，其中當塗覆該聚合物層時，該聚合物層中不含NMP。
  8. 如請求項1-4、6中任一項之積體電路結構的形成方法，其中該聚合物層包括矽氧烷。
  9. 一種積體電路結構，包括：一金屬墊；一聚合物層，於該金屬墊上並接觸該金屬墊；以及一金屬凸塊，包括： 一導孔部分，於該聚合物層中，其中該導孔部分包括：一筆直側壁，其中該筆直側壁具有介於約70度和80度之間的一傾斜角度；一筆直底面；以及一圓底角，包括連接至該筆直側壁的一頂端和連接至該筆直底面的一底端，其中該圓底角具有小於約4μm且大於1μm的一R角；以及一凸塊部分，於該聚合物層上方並連結至該導孔部分。
  10. 如請求項9之積體電路結構，其中該聚合物層於該金屬墊正上方部分的厚度大於約5μm。
  11. 如請求項9之積體電路結構，其中該導孔部分接觸該金屬墊之一頂面以形成一介面，該介面具有小於約20μm的一寬度。
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