TWI735991B - 封裝體及其製造方法 - Google Patents

封裝體及其製造方法 Download PDF

Info

Publication number
TWI735991B
TWI735991B TW108138949A TW108138949A TWI735991B TW I735991 B TWI735991 B TW I735991B TW 108138949 A TW108138949 A TW 108138949A TW 108138949 A TW108138949 A TW 108138949A TW I735991 B TWI735991 B TW I735991B
Authority
TW
Taiwan
Prior art keywords
layer
package
protective layer
metal bump
package component
Prior art date
Application number
TW108138949A
Other languages
English (en)
Other versions
TW202036690A (zh
Inventor
張容華
何健暘
高金福
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW202036690A publication Critical patent/TW202036690A/zh
Application granted granted Critical
Publication of TWI735991B publication Critical patent/TWI735991B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/98—Methods for disconnecting semiconductor or solid-state bodies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02311—Additive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02313—Subtractive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0239—Material of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03901—Methods of manufacturing bonding areas involving a specific sequence of method steps with repetition of the same manufacturing step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05181—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10145—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/11013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the bump connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/1191—Forming a passivation layer after forming the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1405—Shape
    • H01L2224/14051—Bump connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/29386—Base material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the bump connector during or after the bonding process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83104—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus by applying pressure, e.g. by injection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/384—Bump effects
    • H01L2924/3841—Solder bridging

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一種方法包括：形成一金屬凸塊於一第一封裝部件的上表面上；形成一焊料區於金屬凸塊的上表面上；形成一保護層延伸於金屬凸塊的側壁上；回流焊料區以將第一封裝部件接合至一第二封裝部件；以及噴塗一底膠於第一封裝部件與第二封裝部件之間。 底膠與保護層接觸。

Description

封裝體及其製造方法
本發明實施例係關於一種半導體封裝技術，且特別是關於一種封裝體及其製造方法。
隨著半導體技術的發展，半導體晶片/晶粒變得越來越小。同時，需要將更多功能整合至半導體晶粒內。因此，半導體晶粒需要越來越多的I/O接墊封裝至較小的區域內，且I/O接墊的密度會隨著時間的推移而快速上升。如此一來，半導體晶粒的封裝變得更加困難，此不利地影響了封裝的良率。
傳統封裝方法中，可形成層疊封裝(Package-on-Package,PoP)結構。PoP結構包括底部封裝與接合至底部封裝的頂部封裝。為了形成底部封裝，首先模製一裝置晶粒於模塑材料(molding compound)內，並使裝置晶粒的金屬凸點經由模塑材料露出。然後，用於將電子信號重新分佈至比裝置晶粒更大的面積的重佈線(Redistribution Line,RDL)形成於模塑材料及裝置晶粒上。可形成金屬凸塊及/或焊料區，其用於將底部封裝與頂部封裝接合。
另一種封裝方法被稱為基底上晶圓上晶片(Chip-on-Wafer-on-Substrate,CoWoS)。在相應的封裝中，首先將多個第一裝置晶粒接合至一晶圓，晶圓內包括多個第二裝置晶粒。可透過微凸塊或焊料區 進行接合。然後，將底膠噴塗至第一裝置晶粒與第二裝置晶粒之間的間隙中，接著將晶圓分割成多個封裝體。每個封裝體可通過焊料區接合至一封裝基板。然後，將另一底膠噴塗於接合在一起的封裝體與封裝基板之間。
一種封裝體的製造方法包括：形成一金屬凸塊於一第一封裝部件的一上表面上；形成一焊料區於金屬凸塊的上表面上；形成一保護層延伸於金屬凸塊的一側壁上；回流焊料區以將第一封裝部件接合至一第二封裝部件；以及噴塗一底膠於第一封裝部件與第二封裝部件之間，其中底膠與保護層接觸。
一種封裝體的製造方法包括：形成一電鍍罩幕於一第一封裝部件的一上表面處；電鍍一第一金屬凸塊於電鍍罩幕的一開口內；電鍍一第一焊料區於開口內及第一金屬凸塊上方；去除電鍍罩幕，其中第一金屬凸塊突出於第一封裝部件的一上層介電層；回流第一焊料區；以及形成一第一介電保護層於第一封裝部件上，其中第一介電保護層接觸第一金屬凸塊的一垂直側壁。
一種封裝體包括：一封裝部件，包括：一介電層；一金屬凸塊，突出於介電層；一焊料區，位於金屬凸塊上方並接觸金屬凸塊；以及一保護層，接觸金屬凸塊的一側壁及介電層的一表面，其中保護層由一介電材料形成。
20,70,71,118:封裝部件
22:晶片/晶粒/封裝部件
24:半導體基底
26:積體電路裝置
28:內層介電層
32:內連線結構
34:金屬線
36:導通孔
37:頂部金屬特徵部件
38,38A,78,88,92,98:介電層
42:金屬接墊
44:鈍化層
46,94:開口
48:介電層/高分子層
50:種子層
50A,102A:下層
50B,102B:上層
52,104:電鍍罩幕
54,106:金屬凸塊
54A:銅層
54B:金屬蓋層
56:焊料區
60,110:保護層
62:印刷頭
63,103:區域
64:微影罩幕
66,117:切割道
72:基底
74:通孔電極
80:電路
82,90,96:重佈線
84:凸塊下金屬層
86,108,112:焊料區
102:金屬種子層
106A:膜層
106B:蓋層
114:底膠
116:封裝體
200:製程流程
202,204,206,208,210,212,214,216,218,220,222,224,226,228,230,232:製程
H1,H2:高度
第1至10圖繪示出根據一些實施例之製造具有保護層位於微凸塊的側壁上的封裝部件的中間階段的剖面示意圖。
第11至19圖繪示出根據一些實施例之製造具有保護層位於金屬凸塊的側壁上的晶圓的中間階段的剖面示意圖。
第20至23圖繪示出根據一些實施例之將封裝部件接合至晶圓上的中間階段的剖面示意圖。
第24圖繪示出根據一些實施例之用於製造封裝體的製程流程圖。
以下的揭露內容提供許多不同的實施例或範例，以實施本發明的不同特徵部件。而以下的揭露內容是敘述各個構件及其排列方式的特定範例，以求簡化本揭露內容。當然，這些僅為範例說明並非用以限定本發明。舉例來說，若是以下的揭露內容敘述了將一第一特徵部件形成於一第二特徵部件之上或上方，即表示其包含了所形成的上述第一特徵部件與上述第二特徵部件是直接接觸的實施例，亦包含了尚可將附加的特徵部件形成於上述第一特徵部件與上述第二特徵部件之間，而使上述第一特徵部件與上述第二特徵部件可能未直接接觸的實施例。另外，本揭露內容在各個不同範例中會重複標號及/或文字。重複是為了達到簡化及明確目的，而非自行指定所探討的各個不同實施例及/或配置之間的關係。
再者，在空間上的相關用語，例如”下方”、”之下”、”下”、”上方”、”上”等等在此處係用以容易表達出本說明書中所繪示的圖式中元件或特徵部件與另外的元件或特徵部件的關係。這些空間上的相關用語除了涵蓋圖式所繪示的方位外，還涵蓋裝置於使用或操作中的不同方位。此裝置可具有不同方位(旋轉90度或其他方位)且此處所使用的空間上的相關符號同樣有相應的解釋。
根據一些實施例，提供了一種封裝體及其製造方法。根據一些實施例說明封裝體製造的中間階段及某些實施例的一些變型討論。全文各種視圖及實施例說明，相似的標號用於表示相似的元件。
根據一些實施例，介電保護層形成於金屬凸塊的側壁上，使得金屬凸塊的側壁未能潤濕以進行焊接。如此一來，將金屬凸塊接合至其他封裝部件的焊料區將無法在金屬凸塊的側壁上遷移/潤濕。因此避免因焊料遷移而於焊料區內引起的空隙。
第1至10圖繪示出根據一些實施例之製造封裝部件的中間階段的剖面示意圖。如第24圖所示，對應的製程也示意性地反映於製程流程200中。
第1圖繪示出封裝部件20的剖面示意圖。封裝部件20內可包括多個封裝部件22，其中繪示出兩個封裝部件22作為示例。根據一些實施例，封裝部件20為裝置晶圓，包括主動裝置及可能的被動裝置，其表示為積體電路裝置26。根據另一實施例，封裝部件20為中介層(interposer)晶圓，其可包括或不包括主動裝置及/或被動裝置。根據又另一實施例，封裝部件20為封裝基板條(package substrate strip)，其包括多個封裝基板。封裝部件20也可為包括多個封裝體位於其內的重建(reconstructed)晶圓。在後續的討論中，將討論裝置晶圓作為封裝部件20的示例，然而本文的實施例也可應用於中介層晶圓、封裝基板、封裝體或重建晶圓等。
根據一些實施例，封裝部件20包括半導體基底24及形成於半導體基底24的上表面上的特徵部件。半導體基底24可由晶體矽、晶體鍺、矽鍺或III-V族化合物半導體(諸如，GaN、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP或GaInAsP等)。半導體基底24也可為塊材半導體基底或絕緣體上覆半導體(Semiconductor-On-Insulator,SOI)基底。可形成淺溝槽隔離(Shallow Trench Isolation,STI)區(未繪示)於半導體基底24內，以隔離半導體基底24內的主動 區。儘管未繪示於第1圖中，然而可形成通孔電極(through-via)(有時稱為矽通孔電極或半導體通孔電極)延伸至半導體基底24內，其中通孔電極用於將特徵部件電性內耦接於封裝部件20的相對側上。
根據一些實施例，封裝部件20包括多個積體電路裝置26，積體電路裝置26可包括形成於半導體基底24的上表面上的一些部分。根據一些實施例，積體電路裝置26可包括互補式金屬氧化物半導體(Complementary Metal-Oxide Semiconductor,CMOS)的電晶體、電阻器、電容器或二極體等)。此處並未繪示積體電路裝置26的細部結構。根據其他實施例，封裝部件20用於形成多個中介層，並且基板24可為半導體基板或介電基板。
形成內層介電層(Inter-Layer Dielectric,ILD)28於半導體基底24上方，並填充積體電路裝置26內的電晶體(未繪示)的閘極堆疊之間的空間。根據一些實施例，內層介電層(ILD)28由磷矽酸鹽玻璃(Phospho Silicate Glass,PSG)、硼矽酸鹽玻璃(Boro Silicate Glass,BSG)、硼摻雜磷矽酸鹽玻璃(Boron-doped Phospho Silicate Glass,BPSG)、氟摻雜矽酸鹽玻璃(Fluorine-doped Silicate Glass,FSG)、四乙氧基矽烷(Tetra Ethyl Ortho Silicate,TEOS)氧化物等。根據一些實施例，使用諸如電漿輔助化學氣相沉積(Plasma-Enhanced Chemical Vapor Deposition,PECVD)、低壓化學氣相沉積(Low Pressure Chemical Vapor Deposition,LPCVD)、旋塗或流動式化學氣相沉積(Flowable Chemical Vapor Deposition,FCVD)等的沉積方法形成內層介電層(ILD)28。
形成接觸插塞(未繪示)於內層介電層(ILD)28內，並且用於將積體電路裝置26電性連接至上方的金屬線及導通孔(via)。根據一些實施例，接觸插塞由選自鎢、鋁、銅、鈦、鉭、氮化鈦、氮化鉭、其合金及/或其多層材料形成。接觸插塞的形成可包括形成多個接觸開口於內層介電層(ILD)28內，將一或多種導電材料填入接觸開口內，並進行平坦化(例如化學機械研磨 (Chemical Mechanical Polish,CMP)製程或機械研磨製程)以整平接觸插塞的上表面與內層介電層(ILD)28的上表面。
位於內層介電層(ILD)28及接觸插塞上方的是內連線結構32。內連線結構32包括金屬線34及導通孔36，其形成於多個介電層38內(也稱為金屬層間介電層(Inter-metal Dielectric,IMD))。以下將相同層位的金屬線統稱為一金屬層。根據一些實施例，內連線結構32包括多個金屬層，其包括透過導通孔36內連接的金屬線34。金屬線34及導通孔36可由銅或銅合金形成，且其也可由其他金屬形成。根據一些實施例，介電層38由低k介電材料形成。舉例來說，低k介電材料的介電常數(k值)可小於約3.0。介電層38可包括含碳的低k介電材料、含氫矽氧烷(Hydrogen SilsesQuioxane,HSQ)或甲基矽氧烷(MethylSilsesQuioxane,MSQ)等。根據一些實施例，介電層38的製作包括沉積含成孔劑(porogen)的介電材料，然後進行固化製程以驅除成孔劑，因此餘留的介電層38為多孔的。
金屬線34及導通孔36的製造可包括單鑲嵌及/或雙鑲嵌製程。在單鑲嵌製程中，首先於介電層38的其中一者內形成一溝槽，然後於溝槽內填入導電材料。接著進行平坦化(例如，化學機械研磨(CMP)製程)，以去除導電材料高於對應介電層38的上表面的多餘部分，而在溝槽中留下金屬線。在雙鑲嵌製程中，在介電層38的其中一者內形成一溝槽及一介層開口，介層開口位於溝槽下方並連接至溝槽。然後將導電材料填入溝槽介層開口內，以分別形成金屬線及導通孔。導電材料可包括一擴散阻障層及位於擴散阻障層上方的含銅金屬材料。擴散阻障層可包括鈦、氮化鈦、鉭或氮化鉭等。
內連線結構32包括位於頂部介電層內的頂部導電(金屬)特徵部件(標示為37)，例如金屬線、金屬接墊或導通孔，頂部介電層多個介電層38的其中一者(標記為介電層38A)。根據一些實施例，介電層38A由低k介電材 料(與較下方的介電層38的材料相似)形成。根據其他實施例，介電層38A由非低k介電形成材料，其可包括氮化矽、未摻雜的矽酸鹽玻璃(Undoped Silicate Glass，USG)或氧化矽等。介電層38A也可具有多層結構，包括例如兩個USG層與位於其間的氮化矽層。頂部金屬特徵部件37也可由銅或銅合金形成，且可具有雙鑲嵌結構或單鑲嵌結構。介電層38A有時稱為鈍化層。
形成多個金屬接墊42於頂部金屬特徵部件37上方並與頂部金屬特徵部件37接觸。根據一些實施例，金屬接墊42可透過內連線結構32電性耦接至積體電路裝置26。金屬接墊42可為鋁接墊或鋁銅接墊，且可使用其他金屬材料。根據一些實施例，金屬接墊42具有大於約95%的鋁百分比。
形成一圖案化的鈍化層44於內連線結構32上。鈍化層44的一些部分可覆蓋金屬接墊42的邊緣部分，且金屬接墊42上表面的中央部分露出於鈍化層44的開口46。鈍化層44可為單層或複合層，且可由無孔材料形成。根據一些實施例，鈍化層44為一複合層，其包括氧化矽層及位於氧化矽層上方的氮化矽層。
第1圖進一步繪示出介電層48的製作。根據一些實施例，介電層48由高分子形成，諸如聚醯亞胺(polyimide)、聚苯並噁唑(polybenzoxazole,PBO)或苯並環丁烯(benzocyclobutene,BCB)等。根據其他實施例，介電層48由無機介電材料形成，諸如氧化矽、氮化矽或氮氧化矽等。在後續的討論中，介電層48稱為高分子層48，同時可由其他材料形成。對高分子層48進行圖案化，而露出金屬接墊42的中央部分。高分子層48可由感光材料(例如，光阻)形成，其可為負型光阻或正型光阻。高分子層48的製作及圖案化可包括曝光製程及顯影製程。根據一些實施例，在顯影之後，除了下層金屬接墊(例如，42)要露出的部分，高分子層48覆蓋封裝部件20的整個下層部分。
第2至5圖繪示出多個金屬凸塊及多個焊料區的製作。根據一些實 施例，在形成金屬凸塊之前形成多個重佈線(RDL，未繪示)，以將金屬接墊42電性連接至金屬凸塊，如第2至5圖所示。重佈線(RDL)的製作包括：沉積一毯覆式金屬種子層(其可為一銅層)；形成一圖案化的電鍍罩幕(未繪示)於金屬種子層上；電鍍形成重佈線(RDL)；去除圖案化的電鍍罩幕以及蝕刻先前被圖案化的電鍍罩幕覆蓋的金屬種子層的部分。餘留的金屬種子層結合電鍍材料形成重佈線(RDL)，重佈線(RDL)包括延伸至高分子層48內的導通孔部及位於高分子層48上的走線部。根據另一實施例，略過重佈線(RDL)的製作。
接下來，如第2圖所示，沉積一種子層50於高分子層48上。對應的製程如第24圖所示的製程流程中的製程202。種子層50為導電種子層，且可為金屬種子層。根據一些實施例，種子層50為包括多個膜層的複合層。舉例來說，種子層50可包括一下層50A及一上層50B，其中下層50A可包括一鈦層、一氮化鈦層、一鉭層或一氮化鉭層等。上層50B的材料可包括銅或銅合金。根據其他實施例，種子層50為單層，例如為一銅層。種子層50可使用物理氣相沉積(Physical Vapor Deposition,PVD)形成，然而也可使用其他合適的方法。種子層50延伸至高分子層48中的開口內。
第3圖繪示出電鍍罩幕52的製作。對應的製程如第24圖所示的製程流程中的製程204。根據一些實施例，電鍍罩幕52由光阻形成。圖案化電鍍罩幕52以形成多個開口，透過這些開口露出種子層50的一些部分。
接下來，進行電鍍製程以形成多個金屬凸塊54。對應的製程如第24圖所示的製程流程中的製程206。金屬凸塊54可包括一或多個非焊料金屬層。舉例來說，金屬凸塊54可包括含銅層54A，其含銅或銅合金。金屬凸塊54也可包括位於含銅層54A上的金屬蓋層54B。金屬蓋層54B可為含鎳層或含鈀層等，或其多層結構。
透過電鍍形成焊料區56於金屬凸塊54的頂部。焊料區56可由Sn-Ag合金或Sn-Ag-Cu合金等形成，且可為無鉛或含鉛。在後續的製程中，電鍍罩幕52於剝除製程中去除。舉例來說，當電鍍罩幕52由光阻形成時，可使用氧氣來灰化電鍍罩幕52。然後去除種子層50被電鍍罩幕52覆蓋的部分。接下來，如第4圖所示，透過蝕刻去除先前被電鍍罩幕52覆蓋的種子層50的露出部分，而種子層50被金屬凸塊54覆蓋的部分保留下來未被去除。對應的製程如第24圖所示的製程流程中的製程208及製程210。在第4圖中繪示出所得的結構。在全文的說明中，種子層50的餘留部分視為金屬凸塊54的一部分。所得的金屬凸塊54的側壁可為實質上垂直的。在封裝部件22的平面示意圖中，金屬凸塊54可排置成一陣列或以其他重複的圖案配置。
請參照第5圖，多個焊料區56於回流製程(例如，對流回流製程或雷射回流製程等)中進行回流。焊料區56因此具有圓化表面。
第6圖繪示出保護層60的製作，其用於至少減少並可能消除流向金屬凸塊54的側壁的焊料流動/遷移的量。對應的製程如第24圖所示的製程流程中的製程212。保護層60覆蓋並接觸高分子層48的上表面及包括金屬凸塊54之間的部分。根據一些實施例，保護層60的材料選擇為不可潤濕焊料的介電材料。舉例來說，保護層60可由高分子形成，諸如聚醯亞胺或聚苯並噁唑(PBO)等。已經發現聚醯亞胺對銅具有高潤濕性，因此可容易地散佈在金屬凸塊54的整個側壁表面上而增加保護層的益處。保護層60與高分子層48可由相同材料形成，諸如聚醯亞胺或聚苯並噁唑(PBO)，或者可由不同的材料形成，舉例來說，其中一個由聚苯並噁唑(PBO)形成，而另一個由聚醯亞胺形成。由於高分子層48與保護層60以不同的製程形成，因此不管由相同的材料還是由不的材料形成，都可區分高分子層48與保護層60之間的界面。保護層60也可由其他材料形成，例如環氧樹脂。形成保護層60時，可為流動的(水性)形式，然後固化為 一固體層。保護層60內不包括填料顆粒，且整個保護層60可由均質材料形成。保護層60不含填料顆粒可使保護層60具有改良的流動性，因而其可於金屬凸塊54的所有側壁上爬升而無需形成過多的量，因此減少或消除了保護層60覆蓋焊料區56的風險。
根據一些實施例，使用選擇性形成方法來形成保護層60，例如噴墨印刷(inkjet printing)，其中將保護層60選擇性地噴塗到金屬凸塊54之間的空間，而不塗佈於金屬凸塊54上。可透過印刷頭62進行噴墨打印。根據一些實施例，將噴塗的材料噴塗至相鄰的金屬凸塊54之間的中間區域並隔開相鄰的金屬凸塊54。保護層60的黏度夠低，使噴塗材料流動而接觸金屬凸塊54的側壁。再者，由於毛細作用，保護層60爬至金屬凸塊54的側壁的上部上，如此一來，相鄰金屬凸塊54之間的保護層60的部分具有一上表面低於保護層60位於金屬凸塊54的側壁上的側壁頂部尖端，且低於焊料區56與金屬凸塊54之間的界面。在進行印刷之後，固化保護層60。在固化製程中，保護層60的上表面為一自由表面，其不受其他特徵部件的限制(例如，壓制和/或接觸)。
當使用選擇性形成方法形成保護層60時，其中保護層60可選擇性地覆蓋或不覆蓋封裝部件20上的區域，相鄰的封裝部件22之間的切割道可形成保護層60或不形成保護層60。舉例來說，區域63可設置有保護層60也可不設置有保護層60。
金屬凸塊54的側壁的高度表示為H1。保護層60與金屬凸塊54接觸的部分的高度表示為H2。根據一些實施例，保護層60保護金屬凸塊54的大部分側壁，因此比值H2/H1大於0.5。比值H2/H1可等於1.0，或者約在0.5與1.0之間的範圍內。當比值H2/H1小於1.0時，保護層60不與對應的上方焊料區56接觸。由於焊料可潤濕金屬凸塊54的側壁且不可潤濕保護層60，因此當保護層60覆蓋金屬凸塊54的整個側壁時，非焊料可潤濕表面覆蓋金屬凸塊54的整個可潤濕表 面。此提供了防止焊料遷移(或流動)至金屬凸塊54的側壁的改進益處。由於製程變異，保護層60可攀爬至不同的高度。舉例來說，保護層60的一些部分可能會攀爬至焊料區56與金屬凸點54之間的界面，而保護層60的其他一些部分可能會攀爬至對應含銅層54A的上表面與下表面之間的中間高度，或對應金屬蓋層54B的上表面與下表面之間的中間高度。
由於分散、流動及毛細作用，在兩相鄰的金屬凸塊54之間的間隙中，保護層60的對應部分的上表面在靠近間隙中間點處為最低，且上述保護層60的部分在靠近金屬凸塊54的上表面高於上述保護層60的部分在遠離金屬凸塊54的上表面。如所示的示例，保護層60的對應部分可連續彎曲。具有保護層60的最終結構繪示於第9圖。
第7及8圖繪示出根據另一實施例之保護層60的製作。請參照第7圖，可透過旋轉塗佈法進行保護層60塗覆。保護層60包括位於相鄰金屬凸塊54之間間隙內的一些部分以及位於焊料區56的表面上的一些其他部分。根據一些實施例，保護層60由光敏材料形成，例如聚醯亞胺或聚苯並噁唑(PBO)等。
接下來，如第8圖所示，一微影罩幕64用於對保護層60進行曝光，其包括用於阻擋光的非透明部及用於容許光通過的透明部。保護層60可為正型光阻也可為負型光阻，因此使位於焊料層56上的保護層60部分曝光，或者使未位於金屬凸塊54上的保護層60部分曝光。在曝光之後，進行顯影製程，因而去除位於焊料層56上的保護層60部分。所得的結構如第9圖所示。
第9圖也繪示出封裝部件20的單體化(晶粒切割)製程，上述製程沿切割道66進行單體化。對應的製程如第24圖所示的製程流程中的製程214。因而晶片22(其稱為晶粒22或封裝部件22)彼此分離。由於保護層60可能存在或不存在於切割道66上(如區域63所示，可能不存在保護層60)，在單體化製程中，用於單體化的刀具可能穿過相鄰封裝部件22中的保護層60部分之間的空 間，但未穿過保護層60。若保護層60延伸至切割道66中，則刀具也可穿過保護層60。
第10圖繪示出根據一些實施例之封裝部件22其中之一者。區域63可包括或不包括保護層60。根據一些實施例，在封裝部件22的平面示意圖中，不具有保護層60的區域63可形成連續的完整環體圍繞保護層60。換句話說，保護層60可(或可不)自封裝部件22的所有邊緣橫向凹入。
第11至19圖繪示出根據一些實施例之晶圓級封裝部件70的形成。根據一些實施例，封裝部件70為中介層晶圓，其沒有主動裝置，且可包括或不包括被動裝置。根據其他實施例，封裝部件70為裝置晶圓，其中包括電路80。電路80可包括主動裝置(例如，電晶體和二極體)或被動裝置(例如，電容器、電阻器或電感器等)。以虛線表示電路80，以表示其可形成或不形成。封裝部件70可包括基底72以及延伸到基底72中的通孔電極74(有時稱為矽通孔電極或基底通孔電極)。根據一些實施例，基底72為半導體基底，其可為矽基底、矽鍺基底、碳化矽基底或III-V族化合物基底等。當基底72由半導體材料形成時，通孔電極74被介電環圍繞，介電環使通孔電極74與基底72電性絕緣。根據一些實施例，基底72為由以下材料形成的介電基底：例如，氧化矽或氮化矽等。通孔電極74延伸至基板72的上表面與下表面之間的中間層位。通孔電極74為導電的。根據一些實施例，通孔電極74延伸至基底72上方的介電層78內。可理解的是，在介電層78與基底72之間可存在(或者不存在)多個介電層。在介電層中形成的金屬線和導通孔以連接至通孔電極74及和積體電路裝置80。再者，通孔電極74的上表面可與介電層78的上表面切齊，或者可與基底72上的任何介電層的上表面切齊平。
封裝部件70包括多個封裝部件71，封裝部件71為未切割的晶圓級封裝部件70的一部分。封裝部件71可為裝置晶粒或中介層晶粒等。根據一些實 施例，封裝部件71是中央處理單元(Central Processing Unit,CPU)晶粒、應用處理器(AP)晶粒或另一類型的邏輯晶粒。積體電路裝置80(若有形成)包括電晶體、二極體、電容器、電阻器及/或類似物，且形成於基板72的一表面上。
重佈線(RDL)82(有時稱為金屬線及導通孔)形成於介電層78上，且電性連接至通孔電極74。凸塊下金屬層(UBM)84形成於重佈線(RDL)82上，並電性耦接至重佈線(RDL)82。焊料區86形成於凸塊下金屬層(UBM)84上。根據一些實施例，如第11圖所示，焊料區86形成於封裝部件70的前側上。根據另一實施例，形成焊料區86於封裝部件70的背側上，且金屬凸塊(第19圖)形成於封裝部件70的前側上。在整個說明書中，前側為形成有電路80的一側及/或通孔電極74從該側延伸至基底72中。
請參照第12圖，進行背側研磨製程以去除一部分的基底72直至露出通孔電極74。對應的製程如第24圖所示的製程流程中的製程216。接下來，可略微凹陷基底72(例如，透過蝕刻)，使得通孔電極74從基底72的表面突出。對應的製程如第24圖所示的製程流程中的製程218。接下來，沉積一介電層88，隨後進行化學機械研磨(CMP)製程或機械研磨製程以再次暴露通孔電極74。藉此形成具有通孔電極74穿過的介電層88，如第13圖所示。對應的製程如第24圖所示的製程流程中的製程220。根據一些實施例，介電層88由氧化矽或氮化矽等形成。第14圖繪示出重佈線(RDL)90的製作，其包括接墊部，位於通孔電極74正上方並接觸通孔電極74。重佈線(RDL)90可由鋁、銅、鎳或鈦等形成。對應的製程如第24圖所示的製程流程中的製程222。
第15及16圖分別繪示出介電層92及重佈線(RDL)96的製作。請參照第15圖，形成一介電層92。根據一些實施例，介電層92由光敏性高分子形成，諸如聚苯並噁唑(PBO)或聚醯亞胺等。根據另一實施例，介電層92由無機材料形成，諸如氮化矽或氧化矽等。舉例來說，使用微影製程對介電層92進 行圖案化，因而形成開口94以露出重佈線(RDL)90。
請參照第16圖，形成重佈線(RDL)96以電性連接至重佈線(RDL)90。根據一些實施例，重佈線(RDL)96的製作包括沉積一毯覆式金屬種子層；形成一圖案化的電鍍罩幕(未繪示)於毯覆式金屬種子層上；電鍍重佈線(RDL)96於毯覆式金屬種子層的開口內；去除電鍍罩幕；以及蝕刻先前電鍍罩幕覆蓋的金屬種子層的部分。根據另一實施例，使用鑲嵌製程形成重佈線(RDL)96，且形成重佈線(RDL)96於介電層98內。重佈線(RDL)96的上表面可與介電層98的上表面切齊，或者重佈線(RDL)96可包括一些部分位於介電層98上。
第17圖繪示出金屬種子層102的製作。根據一些實施例，金屬種子層102為一多層結構，其包括下層102A與上層102B。下層102A與上層102B的材料可分別相似於種子層50下層50A及上層50B的材料(第2圖)。舉例來說，下層102A可由鈦形成，上層102B可由銅形成。形成方法包括物理氣相沉積(PVD)等。接下來，形成一電鍍罩幕104並圖案化，以露出金屬種子層102的一些部分。
請進一步參照第17圖，透過電鍍形成金屬凸塊106及焊料區108。對應的製程如第24圖所示的製程流程中的製程224。根據一些實施例，金屬凸塊106由非回流(非焊料)的金屬材料形成。舉例來說，金屬凸塊106內的膜層106A可由銅形成，且金屬凸塊106內的蓋層106B可由鎳形成。在電鍍焊料區108之後，去除電鍍罩幕104(例如，透過灰化製程)，以露出其下方的金屬種子層102部分。然後，蝕刻金屬種子層102的露出部分。在整個說明書中，金屬種子層102的餘留部分也視作金屬凸塊106的一部分。第18圖繪示出所得的封裝部件70。根據一些實施例，不對封裝部件70行回流。
第19圖繪示出保護層110的製作。對應的製程如第24圖所示的製程流程中的製程226。保護層110的材料、形成方法及結構可參照第6至8圖討論 的保護層60的候選材料、候選形成方法及候選結構中進行選擇。保護層110覆蓋金屬凸塊106的側壁。保護層110的高度相對於金屬凸塊106的高度可相似於保護層60(第6圖)的高度相對於金屬凸塊54的高度的關係。保護層110可形成或不形成於相鄰封裝部件71之間的切割道上。舉例來說，保護層110可形成或不形成於區域103內。
請參照第20圖，將封裝部件22放置於封裝部件70上，並使每一封裝部件22對準一個封裝部件71。焊料區108與相應的焊料區56接觸。接下來，進行回流製程，使得焊料區108與對應的焊料區56接合以形成焊料區112。第21圖繪示出所得的結構。對應的製程如第24圖所示的製程流程中的製程228。在回流製程中，由於金屬凸塊54及106的可潤濕側壁分別由保護層60及110保護，焊料將不會流至金屬凸塊54及106的表面而導致焊料自金屬凸塊54及106之間的區域流失。而是，焊料主要位於金屬凸塊54與對應的金屬凸塊106之間。
請參照第22圖，底膠114設置於封裝部件22與70之間的間隙中。對應的製程如第24圖所示的製程流程中的製程230。底膠114可包括一基材及位於其內的填料顆粒。基材可包括環氧樹脂或高分子等。填料顆粒可包括二氧化矽或氧化鋁等。填料顆粒可具有球形，且可具有不同的直徑。由於底膠114與保護層54/106由不同的材料形成並且以不同的製程形成，因此底膠114與保護層60和110之間具有可區別的界面。由於區域103內可包括或不包括保護層110，因此底膠114可延伸(或不延伸)至保護層110的相鄰部分之間的空間，以接觸下方的介電層(例如，介電層98)。
接下來，如第23圖所示，進行單體化製程，以將封裝部件70及上方的特徵部件(包括封裝部件22、保護層60及底膠114)分離為彼此相同的多個封裝體116。第23圖繪示出所得到的多個封裝體116其中一者。對應的製程如第24圖所示的製程流程中的製程232。在單體化製程中使用的刀具穿過切割道 117。由於切割道117可包括或不具有保護層110，如由區域103所表示，此區域可包括或不包括保護層110，刀具可切穿保護層110，或者可穿過保護層110的相鄰部分之間的空間。
第23圖進一步繪示出封裝體116接合至封裝部件118(其可為印刷電路板、中介層或封裝基板等)。根據一些實施例，封裝部件22可包括具有通孔電極23位於其內的基板24，且可形成金屬凸塊(未繪示)於封裝部件22的上表面上。基板24內的通孔電極23使用虛線繪示出。虛線表示其可能會或不會形成。金屬凸塊可用於將封裝部件22接合至上方的封裝部件，例如裝置晶粒。舉例來說，當封裝部件22與上方的記憶體晶粒接合時，可形成高頻寬記憶體(High Bandwidth Memory,HBM)立方體。另外，可於基板72的與形成電路80的表面相反的表面上形成積體電路81來取替形成積體電路80。
在上述的實施例中，根據一些實施例討論了一些製程與特徵部件。也可包括其他特徵部件及製程。舉例來說，可包括測試結構以輔助3D封裝或3DIC裝置的驗證測試。測試結構可包括形成於重佈線層內或基底上的測試接墊，其容許對3D封裝或3DIC進行測試或探針及/或探針卡的使用等。驗證測試可在中間結構以及最終結構上進行。另外，此處所述的結構與方法可與測試方法(其結合已知合格晶粒的中間驗證)結合使用，以增加良率並降低成本。
本文所述的實施例具有一些有利特徵。可靠度測試表明了當具有突出的金屬凸塊及焊料區的封裝體在升溫(例如，超過100℃)下儲存時，因焊料向金屬凸塊側壁的遷移，而使金屬凸塊之間的焊料區遭受焊料損失，導致於焊料區產生空隙。再者，在進行回流製程接合封裝部件時，焊料也可能流到金屬凸塊的側壁，再次導致焊料損失。透過形成不可潤濕的保護層來保護金屬凸塊的側壁，至少減少或消除了焊料損失。
根據一些實施例，一種封裝體的製造方法包括：形成一金屬凸塊 於一第一封裝部件的一上表面上；形成一焊料區於金屬凸塊的上表面上；形成一保護層延伸於金屬凸塊的一側壁上；回流焊料區以將第一封裝部件接合至一第二封裝部件；以及噴塗一底膠於第一封裝部件與第二封裝部件之間，其中底膠與保護層接觸。在一實施例中，透過噴墨印刷形成保護層。在一實施例中，在噴墨印刷中，將保護層印刷至與金屬凸塊隔開的位置，且保護層透過毛細作用延伸至金屬凸塊的側壁上。在一實施例中，形成保護層包括：旋塗保護層於第一封裝部件上，其中保護層包括一部分位於焊料區的上表面上；以及進行一微影製程以去除保護層位於焊料區的上表面上的部分。在一實施例中，形成保護層包括噴塗一光敏性高分子，且保護層內沒有填料顆粒。在一實施例中，保護層與焊料區隔開。在一實施例中，上述方法更包括在形成保護層之後，自一對應的晶圓上切割第一封裝部件，其中在噴塗底膠之後進行切割。在一實施例中，上述方法更包括自第一封裝部件與一額外部件之間的切割道去除一部分的保護層，其中第一封裝部件與額外部件為一未切割晶圓的多個部分。在一實施例中，形成金屬凸塊與形成焊料區包括：形成一圖案化電鍍罩幕，具有一開口位於其內；以及電鍍金屬凸塊及焊料區於開口內。
根據一些實施例，一種封裝體的製造方法包括：形成一電鍍罩幕於一第一封裝部件的一上表面處；電鍍一第一金屬凸塊於電鍍罩幕的一開口內；電鍍一第一焊料區於開口內及第一金屬凸塊上方；去除電鍍罩幕，其中第一金屬凸塊突出於第一封裝部件的一上層介電層；回流第一焊料區；以及形成一第一介電保護層於第一封裝部件上，其中第一介電保護層接觸第一金屬凸塊的一垂直側壁。在一實施例中，形成第一介電保護層包括塗覆一光敏性高分子。在一實施例中，形成的第一介電保護層與第一焊料區隔開。在一實施例中，形成第一介電保護層包括一噴墨印刷製程，且第一介電保護層流動以實質上覆蓋第一金屬凸塊的整個垂直側壁。在一實施例中，第一介電保護層接觸上層介電 層，且第一介電保護層與上層介電層由相同的介電材料形成，且在各自的製程步驟中形成。在一實施例中，上述方法更包括形成一第二封裝部件，包括：形成一第二金屬凸塊；形成一第二焊料區於第二金屬凸塊上；以及形成一第二介電保護層，接觸第二金屬凸塊的一側壁；將第一焊料區與第二焊料區回流成一第三焊料區，以接合第一封裝部件至第二封裝部件；噴塗一底膠於第一封裝部件與第二封裝部件之間，其中底膠接觸第一介電保護層及第二介電保護層。
根據一些實施例，一種封裝體包括：一第一封裝部件，包括一介電層；一金屬凸塊，突出於介電層；一焊料區，位於金屬凸塊上方並接觸金屬凸塊；以及一保護層，接觸金屬凸塊的一側壁及介電層的一表面，其中保護層由一介電材料形成。在一實施例中，保護層內沒有填料顆粒。在一實施例中，封裝體更包括一第二封裝部件，接合至第一封裝部件；以及一底膠，接觸保護層。在一實施例中，保護層與焊料區隔開。在一實施例中，保護層與介電層由相同的介電材料形成，且其間具有可區別的界面。
以上概略說明了本發明數個實施例的特徵，使所屬技術領域中具有通常知識者對於本揭露的型態可更為容易理解。任何所屬技術領域中具有通常知識者應瞭解到可輕易利用本揭露作為其它製程或結構的變更或設計基礎，以進行相同於此處所述實施例的目的及/或獲得相同的優點。任何所屬技術領域中具有通常知識者也可理解與上述等同的結構並未脫離本揭露之精神和保護範圍內，且可在不脫離本揭露之精神和範圍內，當可作更動、替代與潤飾。
200:製程流程
202,204,206,208,210,212,214,216,218,220,222,224,226,228,230,232:製程

Claims (15)

  1. 一種封裝體的製造方法，包括：形成一金屬凸塊於一第一封裝部件的一上表面上；形成一焊料區於該金屬凸塊的該上表面上；形成一保護層延伸於該金屬凸塊的一側壁上，其中透過噴墨印刷形成該保護層；回流該焊料區，以將該第一封裝部件接合至一第二封裝部件；以及噴塗一底膠於該第一封裝部件與該第二封裝部件之間，其中該底膠與該保護層接觸。
  2. 如請求項1之封裝體的製造方法，其中在該噴墨印刷中，將該保護層印刷至與該金屬凸塊隔開的一位置，且該保護層透過毛細作用延伸至該金屬凸塊的該側壁上。
  3. 如請求項1之封裝體的製造方法，其中形成該保護層包括：旋塗該保護層於該第一封裝部件上，其中該保護層包括一部分位於該焊料區的該上表面上；以及進行一微影製程，以去除該保護層位於該焊料區的該上表面上的該部分。
  4. 如請求項1之封裝體的製造方法，其中形成該保護層包括噴塗一光敏性高分子，且該保護層內沒有填料顆粒。
  5. 如請求項1至請求項4任一項之封裝體的製造方法，其中該保護層與該焊料區隔開。
  6. 如請求項1至請求項4任一項之封裝體的製造方法，更包括在形成該保護層之後，自一對應的晶圓上切割該第一封裝部件，其中在噴塗該底膠 之後進行該切割。
  7. 如請求項1至請求項4任一項之封裝體的製造方法，更包括自該第一封裝部件與一額外部件之間的一切割道去除一部分的該保護層，其中該第一封裝部件與該額外部件為一未切割晶圓的多個部分。
  8. 一種封裝體的製造方法，包括：形成一電鍍罩幕於一第一封裝部件的一上表面處；電鍍一第一金屬凸塊於該電鍍罩幕的一開口內；電鍍一第一焊料區於該開口內及該第一金屬凸塊上方；去除該電鍍罩幕，其中該第一金屬凸塊突出於該第一封裝部件的一上層介電層；回流該第一焊料區；以及形成一第一介電保護層於該第一封裝部件上，其中該第一介電保護層接觸該第一金屬凸塊的一垂直側壁。
  9. 如請求項8之封裝體的製造方法，其中形成的該第一介電保護層與該第一焊料區隔開。
  10. 如請求項8至請求項9任一項之封裝體的製造方法，其中該第一介電保護層接觸該上層介電層，且該第一介電保護層與該上層介電層由相同的介電材料形成，且在各自的製程步驟中形成。
  11. 如請求項8至請求項9任一項之封裝體的製造方法，更包括：形成一第二封裝部件，包括：形成一第二金屬凸塊；形成一第二焊料區於該第二金屬凸塊上；以及 形成一第二介電保護層，接觸該第二金屬凸塊的一側壁；將該第一焊料區與該第二焊料區回流成一第三焊料區，以接合該第一封裝部件至該第二封裝部件；噴塗一底膠於該第一封裝部件與該第二封裝部件之間，其中該底膠接觸該第一介電保護層及該第二介電保護層。
  12. 一種封裝體，包括：一第一封裝部件，包括：一介電層；一金屬凸塊，突出於該介電層；一焊料區，位於該金屬凸塊上方並接觸該金屬凸塊；以及一保護層，接觸該金屬凸塊的一側壁及該介電層的一表面，其中該保護層由一介電材料形成。
  13. 如請求項12之封裝體，其中該保護層內沒有填料顆粒。
  14. 如請求項12之封裝體，更包括：一第二封裝部件，接合至該第一封裝部件；以及一底膠，接觸該保護層。
  15. 如請求項12至請求項14任一項之封裝體，其中該保護層與該焊料區隔開。
TW108138949A 2018-10-31 2019-10-29 封裝體及其製造方法 TWI735991B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/176,017 2018-10-31
US16/176,017 US10784222B2 (en) 2018-10-31 2018-10-31 Metal-bump sidewall protection

Publications (2)

Publication Number Publication Date
TW202036690A TW202036690A (zh) 2020-10-01
TWI735991B true TWI735991B (zh) 2021-08-11

Family

ID=70325452

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108138949A TWI735991B (zh) 2018-10-31 2019-10-29 封裝體及其製造方法

Country Status (5)

Country Link
US (3) US10784222B2 (zh)
KR (2) KR20200050349A (zh)
CN (1) CN111128762B (zh)
DE (1) DE102019117763B4 (zh)
TW (1) TWI735991B (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3671812B1 (en) * 2018-12-19 2022-02-09 IMEC vzw A method for bonding and interconnecting semiconductor chips
KR102624169B1 (ko) * 2019-06-24 2024-01-12 삼성전자주식회사 반도체 소자 및 이를 포함하는 반도체 패키지
US11587870B2 (en) * 2019-08-13 2023-02-21 Micron Technology, Inc. Apparatus comprising aluminum interconnections, memory devices comprising interconnections, and related methods
US11101228B1 (en) * 2020-02-13 2021-08-24 Qualcomm Incorporated Integrated circuit package with a magnetic core
US20220020693A1 (en) * 2020-07-17 2022-01-20 Taiwan Semiconductor Manufacturing Co., Ltd. Eccentric Via Structures for Stress Reduction
US11670601B2 (en) * 2020-07-17 2023-06-06 Taiwan Semiconductor Manufacturing Co., Ltd. Stacking via structures for stress reduction
KR20220016365A (ko) * 2020-07-30 2022-02-09 삼성전자주식회사 반도체 패키지
US11923357B2 (en) * 2021-01-18 2024-03-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device structure and methods of forming the same
US20220367366A1 (en) * 2021-05-13 2022-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and method of manufacturing the same
US11830865B2 (en) 2021-10-26 2023-11-28 Nanya Technology Corporation Semiconductor device with redistribution structure and method for fabricating the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180138115A1 (en) * 2016-11-11 2018-05-17 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6878633B2 (en) * 2002-12-23 2005-04-12 Freescale Semiconductor, Inc. Flip-chip structure and method for high quality inductors and transformers
US6888255B2 (en) * 2003-05-30 2005-05-03 Texas Instruments Incorporated Built-up bump pad structure and method for same
KR100609334B1 (ko) 2005-06-13 2006-08-08 삼성전자주식회사 감광성 폴리머가 갭필된 적층 회로부재 및 그의 제조 방법
JP4483896B2 (ja) 2007-05-16 2010-06-16 ソニー株式会社 半導体装置及びその製造方法
CN101542726B (zh) * 2008-11-19 2011-11-30 香港应用科技研究院有限公司 具有硅通孔和侧面焊盘的半导体芯片
JP5120342B2 (ja) 2009-06-18 2013-01-16 ソニー株式会社 半導体パッケージの製造方法
US8841766B2 (en) * 2009-07-30 2014-09-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
US8441124B2 (en) * 2010-04-29 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
US8901736B2 (en) * 2010-05-28 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Strength of micro-bump joints
US9018758B2 (en) * 2010-06-02 2015-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall spacer and metal top cap
US8492892B2 (en) * 2010-12-08 2013-07-23 International Business Machines Corporation Solder bump connections
US9245834B2 (en) 2012-03-16 2016-01-26 Stats Chippac, Ltd. Semiconductor device and method of forming compliant conductive interconnect structure in flipchip package
US8981559B2 (en) 2012-06-25 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
US9723716B2 (en) * 2013-09-27 2017-08-01 Infineon Technologies Ag Contact pad structure, an electronic component, and a method for manufacturing a contact pad structure
US9406588B2 (en) * 2013-11-11 2016-08-02 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method thereof
US9406642B1 (en) 2014-03-11 2016-08-02 Stats Chippac Ltd. Integrated circuit packaging system with insulated trace and method of manufacture thereof
US9875980B2 (en) 2014-05-23 2018-01-23 Amkor Technology, Inc. Copper pillar sidewall protection
US9484308B2 (en) * 2014-06-25 2016-11-01 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device
US9379076B2 (en) * 2014-10-01 2016-06-28 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
JP6456232B2 (ja) 2015-04-30 2019-01-23 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US10886250B2 (en) * 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
KR102367404B1 (ko) 2015-08-03 2022-02-25 삼성전자주식회사 반도체 패키지의 제조 방법
US9881884B2 (en) * 2015-08-14 2018-01-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same
JP6543559B2 (ja) 2015-11-18 2019-07-10 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
US9859245B1 (en) * 2016-09-19 2018-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with bump and method for forming the same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180138115A1 (en) * 2016-11-11 2018-05-17 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same

Also Published As

Publication number Publication date
US20210005564A1 (en) 2021-01-07
CN111128762A (zh) 2020-05-08
US11476219B2 (en) 2022-10-18
US20200135677A1 (en) 2020-04-30
DE102019117763A1 (de) 2020-04-30
KR20210149014A (ko) 2021-12-08
US10784222B2 (en) 2020-09-22
KR102374254B1 (ko) 2022-03-16
DE102019117763B4 (de) 2022-12-29
US20220367397A1 (en) 2022-11-17
CN111128762B (zh) 2021-12-31
KR20200050349A (ko) 2020-05-11
TW202036690A (zh) 2020-10-01

Similar Documents

Publication Publication Date Title
TWI735991B (zh) 封裝體及其製造方法
CN109786262B (zh) 互连芯片
US11094671B2 (en) Package with thinned substrate
TWI734234B (zh) 半導體裝置的形成方法及半導體結構
KR102010667B1 (ko) 상이한 평면들 상에서의 단자 연결들을 위한 융기된 비아
CN111128933B (zh) 半导体封装件及其形成方法
US11646220B2 (en) Raised via for terminal connections on different planes
CN110970311B (zh) 集成电路结构和形成集成电路结构的方法
TWI793597B (zh) 半導體裝置及其製造方法