TW201308534A - 半導體裝置與相關方法 - Google Patents

半導體裝置與相關方法 Download PDF

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TW201308534A
TW201308534A TW100127470A TW100127470A TW201308534A TW 201308534 A TW201308534 A TW 201308534A TW 100127470 A TW100127470 A TW 100127470A TW 100127470 A TW100127470 A TW 100127470A TW 201308534 A TW201308534 A TW 201308534A
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wafer
sub
semiconductor device
disposed
package
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TW100127470A
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TWI475651B (zh
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Yu-Yu Lin
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Global Unichip Corp
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Priority to TW100127470A priority Critical patent/TWI475651B/zh
Priority to CN201110359460XA priority patent/CN102915992A/zh
Priority to US13/548,311 priority patent/US9053949B2/en
Publication of TW201308534A publication Critical patent/TW201308534A/zh
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Abstract

一種半導體裝置與相關方法，包括一基板、一第一晶片，環繞晶片設置的複數個子封裝系統與一散熱體。第一晶片與子封裝系統設於基板的同一表面上，兩者於該表面上的投影有部份重疊，有部份不重疊。各子封裝系統包括一介面板與複數個以覆晶形式安裝於介面板上的第二晶片。散熱體具有一突出部份與一散熱板；散熱板覆蓋第一晶片與子封裝系統，突出部份設於第一晶片與散熱板間。

Description

半導體裝置與相關方法
本發明是有關於一種半導體裝置與相關方法，且特別是有關於一種整合多晶片且可兼顧集積度與散熱的半導體裝置與相關方法。
各式各樣的半導體裝置是現代資訊社會最重要的硬體基礎之一。晶片(晶粒、裸晶)是半導體裝置的基礎元件；不同的晶片間可交換訊號、資料以整體性地發揮一電子系統的功能。為了以更小的體積、更高的集積度實現電子系統，現代的半導體裝置會將複數個晶片整合為同一封裝，例如說是系統級封裝(System in Package，SiP)。舉例而言，封裝上封裝(Package on Package，PoP)技術即是將一晶片封裝垂直堆疊於另一晶片封裝上，以整合多個晶片的功能。
不過，以目前封裝上封裝技術形成的半導體裝置仍存在散熱不佳等缺點。
為克服習知技術的缺點，本發明的目的之一是提供一種可兼顧集積度與散熱的半導體裝置，其包括一基板、一或多個第一晶片、一或多個子封裝系統與一散熱體。基板具有一第一表面與複數個外部互聯導體；第一晶片即安裝於第一表面上，外部互聯導體則設於基板的相反兩面。
各子封裝系統安裝於第一表面上，每一子封裝系統於第一表面的投影與第一晶片於第一表面的投影有部份重疊，並有部份不重疊。各子封裝系統中包括一或多個第二晶片、複數個互聯導體(interconnector)與一介面板(interposer)。其中，第二晶片可以是裸晶，也可以是已封裝的矽晶(packaged silicon)。在各子封裝系統的一實施例中，第二晶片可以是裸晶，並以覆晶(flip-chip)方式藉由裸晶底下的凸塊(bump)而安裝於介面板上。以及/或者，第二晶片可以是已封裝的矽晶，藉由針腳及/或圓球狀焊球(例如球格式封裝(Ball Grid Array，BGA)的焊球)安裝於介面板。介面板設於第二晶片與基板的第一表面之間，互聯導體則與第二晶片設於介面板的相反兩面。對應各子封裝系統的互聯導體，基板的第一表面上更設有複數個接點(contact)；各子封裝系統的互聯導體即耦接於接點與介面板之間。
一實施例中，第一晶片以覆晶形式安裝於基板的第一表面上；在第一表面上，第一晶片沿一第一方向的突起高度低於子封裝系統中各互聯導體沿第一方向的高度。
散熱體具有一突出部份、一散熱板與一或多個側壁；散熱板覆蓋於第一晶片與各子封裝系統之上，突出部份設於第一晶片與散熱板之間，各側壁則設於散熱板與第一表面之間。
本發明的又一目的是提出一種提供(例如生產、製造、實現)前述半導體裝置的方法，包括：將第一晶片安裝於基板的第一表面上；當第二晶片為裸晶時，可以覆晶的方式安裝於介面板上，而當第二晶片為封裝體時，則以連接導體(如針腳及/或焊球)安裝於介面板上，以組裝子封裝系統；將子封裝系統中的互聯導體耦接至基板上的對應接點以將各子封裝系統安裝於第一表面上；安裝散熱體，並於基板上附接複數個外部互聯導體。
為了對本發明之上述及其他方面有更佳的瞭解，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下：
請參考第1圖至第7圖。第1圖的立體外視圖示意的是依據本發明一實施例的半導體裝置10，第2圖示意的是半導體裝置10的各主要構件，包括一基板12、一晶片20、一或多個子封裝系統(以兩個子封裝系統22a與22b為例)與一散熱體14。第3圖以子封裝系統22a為例說明本發明子封裝系統的架構實施例；第4圖則是晶片20與子封裝系統22a、22b於基板12上的配置示意圖。第5圖以各角度的視圖示意散熱體14的一種實施例；第6圖則顯示散熱體14於基板12上的配置示意圖。第7圖以不同視圖示意本發明半導體裝置10的架構。
如第1圖所示，基板12在一z方向上具有兩相反的表面16a與16b(可分別視為上表面與下表面)，在表面16b上並設有複數個互聯導體18以作為外部互聯導體。晶片20(第一晶片)與子封裝系統22a、22b則安裝於表面16a上(第一表面)，如第2圖所示；也就是說，互聯導體18與晶片20分別設於基板12的相反兩面。互聯導體18可以是焊球(ball)、針腳(pin)或接點。
如第2圖所示，各子封裝系統22a、22b於表面16a的投影P_a、P_b與晶片20於表面16a的投影P_c有部份重疊(如斜線區域所示)，並有部份不重疊。如第3圖與第4圖所示，子封裝系統22a中包括一介面板24a、複數個互聯導體34(第4圖)與一或多個晶片(第二晶片，其可以是裸晶，以及/或者，亦可以是已封裝的矽晶)，例如說是晶片D1至D4。各晶片D1至D4在z方向上有兩相反的表面，如晶片D1有表面t1與b1(可分別視為上表面與下表面)，晶片D2具有表面t2與b2，晶片D3有表面t3與b3，晶片D4有表面t4與b4。在表面b1至b4上，各晶片D1至D4均設有複數個互聯導體28。在晶片D1至D4的各晶片中，若某一晶片為裸晶，則其表面設置的互聯導體28為裸晶底下的凸塊；若某一晶片為已封裝的矽晶，則其互聯導體28則可以是球格式封裝(Ball Grid Array，BGA)的焊球。
如第3圖與第4圖所示，介面板24a在z方向上有兩相反的表面t24a與t24b(第4圖)；表面t24a上設有複數個接點30，各接點30對應於一互聯導體28，可相互搭配嵌合。在子封裝系統22a中，各晶片D1與D4即是經由各互聯導體28與對應接點30的耦接(連接、焊合)而被安裝於介面板24a上(可一併參考第7圖的側視示意圖)。換言之，晶片D1至D4係以覆晶(flip-chip)形式安裝於介面板24a上；晶片D1至D4的表面b1與b4上設有半導體活性區(active region，未圖示)，以設置互聯導體28；互聯導體28可以是格狀陣列(grid array)排列的凸塊、焊球、針腳或接點。
相對於設置在表面t24a上的各晶片D1至D4，互聯導體34則設置於介面板24a的相反表面t24b上，如第4圖所示。互聯導體34可以是焊球、針腳或接點。
類似於子封裝系統22a，子封裝系統22b中亦包括一介面板24b、複數個互聯導體34與一或多個晶片，例如說是晶片D5至D8，如第4圖所示。在z方向上，介面板24b具有兩相反表面t24b與b24b；晶片D5至D8設置於表面t24b上，互聯導體34則設於表面b24b上。
如第4圖所示，基板12在其表面16a上更設有複數個接點，各接點38對應於一互聯導體34，可相互搭配、嵌合。子封裝系統22a與22b即是經由互聯導體34與接點38間的連接(焊合)而被安裝於基板12上(可一併參考第7圖的側視示意圖)。也就是說，在半導體裝置10中，介面板24a設於晶片D1至D4與基板12的表面16a之間，子封裝系統22a的互聯導體34即耦接於接點38與介面板24a之間。類似地，介面板24b設於晶片D5至D8與表面16a之間，子封裝系統22b的互聯導體34則介於接點38與介面板24b之間。
一實施例中，晶片20亦可以利用覆晶形式而安裝於基板12的表面16a上。晶片20在方向z上有相反兩表面t20(第2圖)與b20(第4圖)。如第4圖所示，晶片20在表面b20上設有複數個互聯導體32(可以是焊球、針腳或接點)；對應地，基板12在其表面16a上亦設有複數個接點36，各接點36可和一互聯導體32相互嵌合搭配。晶片20即是經由互聯導體32與接點36的連接而安裝於基板12的表面16a上。如第7圖的側視示意圖所示，在表面16a上，晶片20沿方向z的突起高度低於子封裝系統22a、22b中各互聯導體34沿方向z的高度，使晶片20可以設置在介面板24a、24b之下(請一併參考第7圖的頂視示意圖)。
如第5圖所示，散熱體14具有一突出部份46、一散熱板40與一或多個側壁，例如側壁42a與42b。散熱板40在方向z上有兩相反表面t40與b40；突出部份46由表面b40沿著方向z的反方向延伸。如第6圖與第7圖所示，散熱板40覆蓋於晶片20與各子封裝系統22a、22b之上，突出部份46設於晶片20與散熱板40之間，各側壁42a、42b則設於散熱板40與基板12的表面16a之間。
散熱體14可以是由高導熱係數的材質(例如金屬)製成，以替晶片20、D1至D8散熱。舉例而言，散熱板40的表面b40可直接或間接地(隔著一層導熱膠合層)貼合於晶片D1至D8的表面t1至t8，突出部份46則可(直接或間接地)貼合於晶片20的表面t20；如此，晶片20運作時產生的熱就可經由突出部份46傳導至散熱板40，並由散熱板40逸散出去。若有需要，散熱板40的表面t40及/或側壁42a、42b上亦可設置增強散熱的鰭片等結構。
在第1圖至第7圖的實施例中，介面板24a與24b承載了晶片D1至D8。在另一種實施例中，介面板24a、24b不僅可承載晶片，亦可承載其他電子元件(未圖示)，例如被動元件(電阻、電容及/或電感等等)。
由第1圖至第7圖的討論可知，子封裝系統22a、22b的介面板24a、24b可部份延伸覆疊於晶片20之上，以擴大介面板24a、24b上能承載晶片/電子元件的面積，使介面板24a、24b可以承載更多晶片/電子元件，提高半導體裝置10的封裝集積度。再者，介面板24a、24b不會完全覆蓋晶片20，使散熱體14的突出部份46仍能延伸至晶片20，兼顧晶片20的散熱。
延續第1圖至第7圖的實施例，請參考第8圖，其係以側視示意半導體10中的導電路徑。基板12與介面板24a、24b中可分別設置一或多層的導體層(如金屬層，未圖示)，用以形成繞線，以和互聯導體28、32與34搭配形成各種導電路徑，使晶片20、D1至D8可互相電性耦接，並經由互聯導體18電性耦接外界電路(例如電路板或另一半導體裝置)。舉例而言，子封裝系統中的晶片，例如子封裝系統22a的晶片D3或D4，即可經由互聯導體28、介面板24a、互聯導體34、基板12與互聯導體32而電性耦接至晶片20，使子封裝系統中的晶片可以和晶片20交換(傳輸及/或接收)資料、訊號。
晶片20本身可經由互聯導體32、基板12而電性耦接至外部互聯導體18，以和外界電路交換資料訊號，以及/或者汲取運作所需的電力。類似地，子封裝系統中的晶片，例如子封裝系統22a的晶片D4，則可經由互聯導體28、介面板24a、互聯導體34、基板12而電性耦接至外部互聯導體18，以和外界電路交換資料訊號，以及/或者汲取運作所需的電力。
同一子封裝系統中的不同晶片，例如子封裝系統22a中的晶片D3與D4，可經由晶片D3的互聯導體28、介面板24a與晶片D4的互聯導體28相互電性耦接以交換資料、訊號。類似地，不同子封裝系統中的不同晶片，例如子封裝系統22a中的晶片D3與子封裝系統22b中的晶片D7，則可經由晶片D3的互聯導體28、介面板24a、介面板24a的互聯導體34、基板12、介面板24b的互聯導體34、介面板24b與晶片D7的互聯導體28而相互電性耦接，並交換資料、訊號。
在本發明半導體裝置10的一實施例中，晶片20可以是一處理器(控制器)，而晶片D1至D8可以是記憶體晶粒，為晶片20提供運作所需的記憶體資源。
請參考第9圖，其所示意的是依據本發明一實施例而提供(例如組裝、生產、製造、加工及/或實現)本發明半導體裝置的流程100。以下即以半導體裝置10的實現為例來說明流程100的各主要步驟。
步驟102：將晶片20貼附至基板12的表面16a。如第4圖所示，可將晶片20的互聯導體32嵌合於對應的接點36；當互聯導體32嵌合至對應接點36後，可在互聯導體32之間注入底膠(underfill)，以覆晶形式將晶片20安裝於基板12的表面16a上。
步驟104：組裝各子封裝系統22a、22b；舉例而言，可將晶片D1至D4安裝於介面板24a上。晶片D1至D4可以是裸晶，亦可以是已封裝的矽晶。若晶片為裸晶時，可以用覆晶的方式安裝於介面板24a上；若晶片為已封裝的矽晶時，則可以焊球或針腳等形式安裝於介面板24a上。同理，晶片D5至D8亦被安裝於介面板24b上。如第3圖所示，晶片D1至D4的互聯導體28可被嵌合至介面板24a的接點30；若晶片D1至D4為裸晶，可在表面t24a與表面b1至b4間注入底膠(未圖示)。若晶片D1至D4非裸晶，底膠則非必要。若有需要，亦可在介面板24a、24b上安裝其他電子元件。
步驟106：將子封裝系統22a、22b貼附於基板12的表面16a；如第4圖所示，子封裝系統22a、22b的互聯導體34可連接嵌合於基板12上的對應接點38，以將子封裝系統22a、22b安裝於表面16a上。由於介面板24a與24b部份延伸於晶片20之上，子封裝系統22a、22b於表面16a的投影與晶片20的投影有部份重疊，並有部份不重疊。
步驟108：貼附散熱體14，將散熱體14安裝於基板12上，使散熱板40覆蓋於晶片20與子封裝系統22a、22b之上，並使突出部份46被設置於晶片20與散熱板40之間，如第4圖與第7圖所示。在一種實施例中，散熱體14的側壁42a、42b、突出部份46與散熱板40可先組裝為一體，再被貼附至基板12上。在另一種實施例中，散熱體14的側壁42a、42b、突出部份46與散熱板40即一體成形。在又一種實施例中，係先將側壁42a、42b形成於基板12上，再將散熱板14(與突出部份46)組合至側壁42a與42b上。
步驟110：將外部互聯導體18貼附於基板12的表面16b。基板12的表面16b上可設置複數個接點(未圖示)，各接點對應一互聯導體18而可相互嵌合；此步驟即是將互聯導體18連接至對應的接點，以將各互聯導體18附接於基板12。至此，就可完成半導體裝置10。
請參考第10圖，其所示意的是依據本發明另一實施例的散熱體14b。類似於第6圖的散熱體14，散熱體14b亦設有突出部份46、散熱板40與側壁42a、42b；散熱體14b更具有另兩側壁42c與42d，使散熱體14b的側壁42a至42d可環繞於晶片20與子封裝系統22a、22b四周。
在第1圖至第10圖的粒子中，半導體裝置10中設有單一晶片20。在其他實施例中(未圖示)，半導體裝置10可以設置複數個晶片20；這些晶片20可以是設置於子封裝系統22a與22b之間，並與突出部份46接觸。其中，至少有一晶片20係覆蓋於子封裝系統22a及/或22b之下。
在第1圖至第10圖實施例中，晶片D1至D4係以凸塊、焊球或針腳或其他接合形式安裝於子封裝系統22a的介面板24a上。
總結來說，相較於習知技術，本發明不僅可增進半導體裝置的封裝集積度，還可兼顧封裝中各晶片的散熱，確保封裝中的電子系統能順利地運作。
綜上所述，雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10．．．半導體裝置
12．．．基板
14、14b．．．散熱體
16a-16b、t20-b20、t24a-b24a、t24b-b24b、t40-b40．．．表面
18、28、32、34．．．互聯導體
20、D1-D8．．．晶片
22a-22b．．．子封裝系統
24a-24b．．．介面板
30、36、38．．．接點
40．．．散熱板
42a-42d．．．側壁
46．．．突出部份
100．．．流程
102-110．．．步驟
z．．．方向
P_a、P_b、P_c．．．投影
第1圖以立體外視圖示意本發明半導體裝置的一實施例。
第2圖示意第1圖半導體裝置的各主要構件。
第3圖示意第2圖子封裝系統的架構實施例。
第4圖示意第2圖晶片與子封裝系統於基板上的配置實施例。
第5圖以不同角度示意第2圖散熱體的實施例。
第6圖示意第5圖散熱體於第2圖基板的配置實施例。
第7圖以不同角度示意第1圖半導體裝置。
第8圖示意第1圖半導體裝置中的各種電性耦接導電路徑。
第9圖係以第1圖半導體裝置為例示意本發明方法的流程實施例。
第10圖示意第6圖散熱體的另一實施例。
10．．．半導體裝置
12．．．基板
14．．．散熱體
16a．．．表面
18、28、32、34．．．互聯導體
20、D1-D8．．．晶片
22a-22b．．．子封裝系統
24a-24b．．．介面板
40．．．散熱板
42a-42b．．．側壁
46．．．突出部份
z．．．方向

Claims (14)

  1. 一種半導體裝置，包含：一基板，具有一第一表面；一第一晶片，安裝於該第一表面上；至少一子封裝系統，安裝於該第一表面上，各該子封裝系統於該第一表面的投影與該第一晶片於該第一表面的投影係有部份重疊，並有部份不重疊；以及一散熱體(heat spreader)，具有一突出部份與一散熱板；該散熱板係覆蓋於該第一晶片與各該子封裝系統之上，而該突出部份係設於該第一晶片與該散熱板之間；其中，各該子封裝系統包含：至少一第二晶片；以及一介面板(interposer)，設於各該第二晶片與該第一表面之間；各該第二晶片安裝於該介面板上。
  2. 如申請專利範圍第1項所述的半導體裝置，其中，該第一表面上更設有複數個接點(contact)，而各該子封裝系統更包含複數個互聯導體(interconnector)，各該互聯導體與各該第二晶片係設於該介面板的相反兩面，且該些互聯導體係分別耦接於該些接點與該介面板之間。
  3. 如申請專利範圍第2項所述的半導體裝置，其中，該第一晶片係以覆晶形式安裝於該第一表面上；於該第一表面上，該第一晶片沿一第一方向的突起高度係低於該些互聯導體沿該第一方向的高度。
  4. 如申請專利範圍第1項所述的半導體裝置，其中該散熱體更具有至少一側壁，各該側壁設於該散熱板與該第一表面之間。
  5. 如申請專利範圍第1項所述的半導體裝置，更包含複數個外部互聯導體；該些外部互聯導體係與該第一晶片設於該基板的相反兩面。
  6. 如申請專利範圍第1項所述的半導體裝置，其中該第二晶片為一裸晶，該第二晶片以覆晶(flip-chip)的方式安裝於該介面板上。
  7. 如申請專利範圍第1項所述的半導體裝置，其中該第二晶片為一已封裝之矽晶，該第二晶片藉由一焊球或一針腳安裝於該介面板上。
  8. 一種半導體裝置，包含：一基板，具有一第一表面；一第一晶片，安裝於該第一表面上；至少一子封裝系統，安裝於該第一表面上，各該子封裝系統於該第一表面的投影與該第一晶片於該第一表面的投影係有部份重疊，並有部份不重疊；以及一散熱體，具有一突出部份與一散熱板；該散熱板係覆蓋於該第一晶片與各該子封裝系統之上，而該突出部份係設於該第一晶片與該散熱板之間；其中，各該子封裝系統包含：至少一第二晶片；以及一介面板，設於各該第二晶片與該第一表面之間。
  9. 如申請專利範圍第8項所述的半導體裝置，其中，該第一表面上更設有複數個接點(contact)，而各該子封裝系統更包含複數個互聯導體(interconnector)，各該互聯導體與各該第二晶片係設於該介面板的相反兩面，且該些互聯導體係分別耦接於該些接點與該介面板之間。
  10. 一種提供一半導體裝置的方法，包含：將一第一晶片安裝於一基板的一第一表面上；組裝至少一子封裝系統，包含：於各該子封裝系統中將至少一第二晶片安裝於一介面板上；將各該子封裝系統安裝於該第一表面上，使各該子封裝系統於該第一表面的投影與該第一晶片於該第一表面的投影係有部份重疊，並有部份不重疊；以及安裝一散熱體(heat spreader)；該散熱體具有一突出部份與一散熱板；當安裝該散熱體時，係使該散熱板覆蓋於該第一晶片與各該子封裝系統之上，並使該突出部份被設置於該第一晶片與該散熱板之間。
  11. 如申請專利範圍第10項所述的方法，更包含：於該基板上附接複數個外部互聯導體，使該些外部互聯導體係與該晶片設於該基板的相反兩面。
  12. 如申請專利範圍第10項所述的方法，其中，該第一表面上更設有複數個接點，各該子封裝系統更包含複數個互聯導體，各該互聯導體與各該第二晶片係設於該介面板的相反兩面；當安裝各該子封裝系統時，係使各該子封裝系統的該些互聯導體分別耦接於該些接點與該介面板之間。
  13. 如申請專利範圍第10項所述的方法，其中該第二晶片為一裸晶，該第二晶片以覆晶(flip-chip)的方式安裝於該介面板上。
  14. 如申請專利範圍第10項所述的方法，其中該第二晶片為一已封裝之矽晶，該第二晶片藉由一焊球或一針腳安裝於該介面板上。
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