TW201301415A - 積體電路封裝之組裝方法及其封裝 - Google Patents
積體電路封裝之組裝方法及其封裝 Download PDFInfo
- Publication number
- TW201301415A TW201301415A TW101110350A TW101110350A TW201301415A TW 201301415 A TW201301415 A TW 201301415A TW 101110350 A TW101110350 A TW 101110350A TW 101110350 A TW101110350 A TW 101110350A TW 201301415 A TW201301415 A TW 201301415A
- Authority
- TW
- Taiwan
- Prior art keywords
- substrate
- wafer
- substrates
- carrier
- integrated circuit
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 49
- 230000008569 process Effects 0.000 title description 17
- 239000000758 substrate Substances 0.000 claims abstract description 421
- 238000000465 moulding Methods 0.000 claims abstract description 58
- 150000001875 compounds Chemical class 0.000 claims abstract description 42
- 235000012431 wafers Nutrition 0.000 claims description 180
- 230000002093 peripheral effect Effects 0.000 claims description 13
- 239000004033 plastic Substances 0.000 claims description 10
- 229920003023 plastic Polymers 0.000 claims description 10
- 238000004806 packaging method and process Methods 0.000 claims description 9
- 239000002991 molded plastic Substances 0.000 claims description 5
- 238000007747 plating Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 description 31
- 229910000679 solder Inorganic materials 0.000 description 22
- 238000012360 testing method Methods 0.000 description 17
- 229910052751 metal Inorganic materials 0.000 description 13
- 239000002184 metal Substances 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 7
- 239000011230 binding agent Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 239000000919 ceramic Substances 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 125000003700 epoxy group Chemical group 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- RNFJDJUURJAICM-UHFFFAOYSA-N 2,2,4,4,6,6-hexaphenoxy-1,3,5-triaza-2$l^{5},4$l^{5},6$l^{5}-triphosphacyclohexa-1,3,5-triene Chemical compound N=1P(OC=2C=CC=CC=2)(OC=2C=CC=CC=2)=NP(OC=2C=CC=CC=2)(OC=2C=CC=CC=2)=NP=1(OC=1C=CC=CC=1)OC1=CC=CC=C1 RNFJDJUURJAICM-UHFFFAOYSA-N 0.000 description 1
- 229920000954 Polyglycolide Polymers 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000003063 flame retardant Substances 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000010330 laser marking Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 235000010409 propane-1,2-diol alginate Nutrition 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000007666 vacuum forming Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/1319—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/1354—Coating
- H01L2224/13599—Material
- H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01087—Francium [Fr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
本發明涉及一種積體電路(IC)封裝及其組裝方法。形成包括多個基板的基板面板。分割所述基板面板,以分離成所述多個基板。將所分離的基板的至少子集連接在載體的表面。將一個或多個晶片連接裝在所述載體上的每一個所述基板。在所述載體上使用模塑膠對所述晶片和所述基板進行封裝。從所封裝的晶片和基板中拆卸所述載體,以形成模塑組裝,所述模塑組裝包括用於封裝所述晶片和基板的所述模塑膠。將多個互連連接在所述模塑組裝的表面上的每一個所述基板。分割所述模塑組裝,以形成多個IC封裝。每一個IC封裝包括至少一個所述晶片和基板。
Description
本發明涉及積體電路封裝的組裝。
通常使用可以連接到(attach)電路板的封裝將積體電路(IC)晶片或晶片與其他電路耦合(interface)。一種這樣類型的IC晶片封裝(IC die package)是球柵陣列(BGA)封裝。BGA封裝比許多其他如今可獲得的封裝解決方案提供更小的引腳印(footprint)。一種類型的BGA封裝含有一個或多個連接在封裝基板的第一表面的IC晶片,並且含有位於封裝基板的第二表面的焊球墊陣列。焊球連接在焊球墊上。焊球回流以使封裝連接在電路板上。
一種先進類型的BGA封裝是晶圓級BGA封裝。晶圓級BGA封裝在業界有幾個名字,包括晶圓片級晶片規模封裝(WLCSP)等。在晶圓級BGA封裝中,當IC晶片還沒有從其製造晶圓分割出來(singulate)時,焊球直接連接裝在IC晶片上。這樣,晶圓級BGA封裝不包括封裝基板。因此,相對包括傳統BGA封裝的其他IC封裝類型,晶圓級BGA封裝可以製造得很小,具有高引腳數(high pin out)。
對於用於晶圓級BGA封裝的IC晶片,通常直接在晶片上形成佈線。佈線在晶片的表面形成,以按佈線將晶片襯墊的信號發送至焊球連接在晶片上的位置。扇入(fan-in)佈線和扇出(fan-out)佈線是可在晶片上形成的兩種不同類型的佈線方式。扇入佈線是一類僅在每個半導體晶片的區域之內形成的佈線。扇出佈線是一類在半導體晶片的區域之外延伸的佈線。例如,對於每個晶片,可以在晶片半導體材料周圍使用一種材
料,所使用的材料是固體。然後,扇出佈線可以應用於晶片,通過所使用的材料,在晶片的區域之外延伸。這樣,扇出佈線提供優勢,包括使能在較大的區域上傳遞信號,從而為信號跡線提供更多空間。然而,目前的扇出佈線技術需要昂貴的資本投資。雖然這樣的資本投資可以在長期內提供資本效益,但不能在短期內提供成本效益。此外,由於目前該行業的趨勢,將越來越多的裝置移到晶圓級封裝上,目前的扇出佈線技術受到其能力的限制。這樣,儘管扇出晶圓級製造的成本在下降,扇出晶圓級製造也難以趕上日益增加的壓力來降低價格並保持利潤率。
本發明提供了製造積體電路封裝的方法、系統和設備,結合至少一幅附圖進行了詳細描述,並在申請專利範圍中得到了更完整的闡述。
根據本發明的一個方面,提供一種方法,所述方法包括:形成包括多個基板的基板面板(substrate panel),每一個所述基板包括佈線;分割(singulating)所述基板面板,以分離所述多個基板;將所分離的基板的至少子集連接在載體的表面;將一個或多個晶片貼裝在所述載體上的每一個所述基板;在所述載體上使用模塑膠(molding compound)對所述晶片和所述基板進行封裝;從所封裝的晶片和基板中拆卸所述載體,以形成模塑
組裝,所述模塑組裝包括用於封裝所述晶片和基板的所述模塑膠;將多個互連(interconnect)連接在所述模塑組裝的表面上的每一個所述基板;及分割所述模塑組裝,以形成多個積體電路封裝,每一個積體電路封裝包括至少一個所述晶片和基板。
較佳地,所述方法進一步包括:使用柱塞(stud)對在所述基板面板中的所述基板進行電鍍,以形成用於將所述晶片貼裝在所述基板的導電觸點。
較佳地,所述形成包括多個基板、且每個基板包括佈線的基板面板包括:形成所述基板面板來包含陣列中的所述基板,除了圍繞所述陣列的所述基板面板的周邊邊緣區域之外,所述陣列填滿所述基板面板。
較佳地,所述將所分離的基板的至少子集連接在載體的表面包括:對所分離的基板進行定位,使其在所述載體的所述表面上間隔地分開。
較佳地,所述在所述載體上使用模塑膠對所述晶片和所述基板進行封裝包括:填充位於帶有所述模塑膠的所分離的基板之間的空間。
較佳地,所述分割所述模塑組裝,以形成多個積體電路封裝包括:分割所述模塑組裝,使得每一個積體電路封裝包括圍繞所包含的基板的外部邊緣的模塑膠的周邊環(peripheral
ring)。
較佳地,所述互連是凸點互連。
較佳地,所述方法進一步包括:測試在所述基板面板中的所述基板,以確定一套工作基板;其中,所述將所分離的基板的至少一個子集連接在載體的表面包括:將所述一套工作基板的所分離的基板連接到所述載體的所述表面。
根據本發明的一個方面,提供一種方法,所述方法包括:接收多個分離的基板;將所述基板連接在載體的表面;將一個或多個晶片貼裝在所述載體上的每一個所述基板;在所述載體上使用模塑膠對所述晶片和所述基板進行封裝;從所封裝的晶片和基板中拆卸所述載體,以形成模塑組裝,所述模塑組裝包括用於封裝所述晶片和基板的所述模塑膠;將多個互連連接在所述模塑組裝的表面上的每一個所述基板;及分割所述模塑組裝,以形成多個積體電路封裝,每一個積體電路封裝包括至少一個所述晶片和基板。
較佳地,所述將所述基板連接在載體的表面包括:對所述基板進行定位,使其在所述載體的所述表面上
間隔地分開。
較佳地,所述在所述載體上使用模塑膠對所述晶片和所述基板進行封裝包括:填充位於帶有所述模塑膠的所述基板之間的空間。
較佳地,所述分割所述模塑組裝,以形成多個積體電路封裝包括:分割所述模塑組裝,使得每一個積體電路封裝包括圍繞所包含的基板的外部邊緣的模塑膠的周邊環。
較佳地,所述互連是凸點互連。
較佳地,所述方法進一步包括:測試在所述基板面板中的所述基板,以確定一套工作基板;其中,所述將所述基板的至少子集連接在載體的表面包括:將所述一套工作基板的所述基板連接到所述載體的所述表面。
根據本發明的一個方面,提供一種積體電路封裝,所述積體電路封裝包括:基板,其含有相對的第一和第二表面;晶片,其連接在所述基板的所述第一表面;及模塑膠,用於封裝所述基板的第一表面上的所述晶片,且形成圍繞所述基板的外部邊緣的周邊環。
較佳地,所述積體電路封裝包括:多個互連凸點,其連接在所述基板的所述第二表面。
較佳地,所述積體電路封裝包括:多個柱塞,將所述晶片的接線端連接到所述基板的第
一表面上的導電形體(feature)上。
較佳地,所述積體電路封裝包括:多個焊接凸點,用於將晶片的接線端耦合至所述基板的所述第一表面上的導電形體(conductive feature)上。
附圖作為說明書的一部分,用於說明本發明,並結合具體實施方式進一步解釋本發明的原理,以使本領域技術人員能夠實施本發明。
下面將結合附圖對本發明進行詳細描述。在附圖中,相同標號一般表示相同或功能相似的部件。另外,附圖標記最左邊的數位表明該附圖標記首次出現時的那幅附圖的編號。
本說明書公開了一個或多個包含本發明特點的實施例。公開的實施例僅僅用於舉例說明。本發明的保護範圍並不限於所公開的實施例。本發明由所附申請專利範圍來限定。
說明書中針對“一個實施例”、“實施例”、“示例實施例”等的引用,指的是描述的該實施例可包括特定的特徵、結構或特性,但是不是每個實施例必須包含這些特定特徵、結構或特性。此外,這樣的表述並非必定指的是同一個實施例。進一步,在結合實施例描述特定的特徵、結構或特性時,不管有沒有明確的描述,已經表明將這樣的特徵、結構或特性結合到其它實施例中是在本領域技術人員的知識範圍內的。
此外,應當理解,本發明所使用的空間描述(例如,“在…上面”、“在…下面”、“向上”、“左邊”、“右邊”、“向下”、“頂部”、“底部”、“垂直”、“水準”等)僅僅為了說明的目的。本發明描述的結構的實施例可以以任何方向或方式進行空間安排。
本發明的實施例使能有效地和經濟地組裝積體電路(IC)封裝,例如球柵陣列(BGA)封裝。在實施例中,形成IC封裝包括將一個或多個晶片和基板封裝在封裝材料(例如,模塑膠)中。在IC封裝中,將一個或多個晶片貼裝在封裝基板,以及將凸點互連或其他類型的互連連接在封裝基板以使封裝連接裝在電路板上。
可以使用現有的基板生產設施來組裝IC封裝實施例,而不需要扇出佈線,根據扇出佈線,通過使用晶片周圍的額外區域來擴大晶片的區域,並通過額外的材料來將扇出佈線路由出去。然而,用於擴大晶片的區域和使用扇出佈線的製造工藝是是昂貴的和費時的。本發明的實施例由於不需要扇出佈線的昂貴設備,顯著地減輕了資本投資的約束。在本發明的實施例中,提高基板利用率,以顯著地提高輸送量,提高原料利用率,並降低成本。在這樣的實施例中,增加了每個基板面板產生的封裝的數量。此外,不需要標記基板面板/條中的非工作基板。
在本發明的一個實施例中,形成的基板可能尺寸過小,這可通過模塑膠來彌補。例如,可能需要7mm*7mm的封裝尺寸。可以形成6.6mm*6.6mm的基板,而圍繞基板外部邊緣的模塑膠可以有0.2mm的厚度,以使得封裝有以7mm
*7mm的尺寸。這種方式可以更進一步地提高基板面板的利用率。
在本發明的實施例中,可以使用現有的或已制定的重建過程。例如,可以利用取放技術來將已知的好基板和晶片放置在載體上,並使用已建立的技術來對基板和晶片進行封裝,來重建面板。
在本發明的實施例中,可以利用現有的扇出晶圓級封裝的組裝技術,但可以使用多層基板來代替重新分配層,使能避免重新分配層形成過程的步驟(以及相關昂貴的設備),轉換成更具成本效益的解決方案。
這樣的實施例具有成本效益和可生產性,並使能製造出含有大量引腳的小尺寸封裝。本發明所描述的實施例僅用於說明的目的,並不限制本發明。雖然在下面的描述中主要以球柵陣列封裝為例來進行說明,本發明的實施例可以適合於各種不同類型的積體電路封裝類型,且這樣的封裝可以包括一個以上的積體電路晶片。在本發明的示教下,進一步的結構性和操作性實施例,包括修改/更改的實施例,對於本領域技術人員來說是顯而易見的。
根據本發明的實施例,可以在基板面板中形成IC封裝使用的基板。例如,圖1示出了根據本發明實施例的形成封裝基板的流程100。為了說明的目的,下面結合圖2-6來對流程100進行描述。根據本發明提供的討論,進一步的結構性和操作性實施例,對於本領域技術人員來說是顯而易見的。
流程100開始於步驟102。在步驟102中,形成包括
多個基板的基板面板,每個基板包括佈線。在本發明的實施例中,形成的基板面板可包括與封裝基板相對應的多個區域。形成的基板面板包括一個或多個佈線層和一個或多個絕緣層,並形成穿通絕緣層的導電孔。在基板面板的第一表面上的導電墊(用於傳輸晶片的信號)經過佈線層和孔,穿通基板面板,連接至基板面板的第二表面上的焊球墊。本領域的技術人員知悉,可以根據標準的或專有的基板面板製造技術來製造基板面板。
例如,圖2示出了示例基板面板200的表面圖,基板面板200包括多個基板條部分202a-202l。每個基板條部分202a-202l包括多個基板204。雖然圖2所示的基板面板200包括12個基板條部分202a-202l(2乘6陣列),在其他實施例中,基板面板200可以包括其他數量的基板條部分202。此外,雖然圖2所示的每個基板條部分202a-202l包括24個基板204(2乘12陣列),每個基板條部分202可以包括其他數量的基板204。
根據一種類型的IC封裝的組裝技術,可以分離(例如,鋸切割等)基板面板200以形成分離的基板條,每個基板條包括多個基板204。可以測試每個基板條中的基板204,並標記任何非工作基板204(測試失敗的基板)。對於特定的基板條,可以將晶片連接裝在工作基板204(在基板條中沒有標記為失敗的基板),可以將晶片封裝在基板條上,可以將凸點互連連接在基板條,以及可以將基板條分割成分離的積體電路封裝。
然而,這樣的IC的組裝技術也有缺點。例如,如圖2所示,在基板條部分202a-202l之間和周圍的基板面板200
的額外的部分是未利用的。在分離基板面板200之後,丟棄基板面板200的未利用的部分,導致浪費材料和成本。此外,在測試期間,如果確定某一基板條包括特定數量的非工作基板204(例如,大於基板條中的基板總數的10%,大於基板條中的基板總數的20%等),可以丟棄整個基板條,將其當作對進一步的處理來說是無效的。這樣,在丟棄的基板條中的任何工作基板也被丟棄,導致進一步浪費材料和成本。
本發明的實施例使能減少基板面板的浪費。例如,在一個實施例中,流程100的步驟102可以包括圖3所示的步驟302。在步驟302中,形成基板面板,使其被充分地填滿多個基板。在這樣的實施例中,大幅減少或完全消除基板面板的未利用的部分。在這種方式中,幾乎沒有基板材料被丟棄,節省了材料和成本和提高了基板面板的利用率。
例如,圖4和圖5分別示出了根據本發明的實施例的充分被基板204填滿的基板面板400和500。在圖4中,基板面板400包括基板204的陣列402,和圍繞陣列402的基板面板的周邊邊緣部分404。陣列402中的基板204彼此相鄰,使得基板面板400沒有未使用部分出現在基板204之間。當從基板面板400中將基板204分割出來時,邊緣部分404是基板面板400唯一被丟棄的重要部分。圖4所示的基板面板400為矩形的,但是,在其他實施例中,可以有其他形狀。此外,圖4所示的陣列402為18乘26陣列的基板204(208個基板204),但是,在其他實施例中,可以有其他尺寸和/或其他數量的基板204。
在圖5中,基板面板500包括基板204陣列。在基板
面板500中沒有基板面板邊緣部分。基板面板500中的基板204彼此相鄰,使得基板204之間或周圍沒有基板面板500的未使用部分。當從基板面板500中將基板204分割出來時,沒有基板面板500的重要部分被丟棄。圖5所示的基板面板500為矩形的,但是,在其他實施例中,可以有其他形狀。此外,圖5所示的基板面板500為18乘26陣列的基板204(208個基板204),但是,在其他實施例中,可以有其他尺寸和/或其他數量的基板204。
形成基板面板,例如基板面板200、400和500,使得基板204的每一個都包括一個或多個導電層,該導電層被一個或多個絕緣層隔開。導電層可以包括跡線/佈線、接合指(bond fingers)、接觸墊,和/或其他導電特性。例如,可以形成含有一個導電層、兩個導電層或四個導電層的BGA基板。導電層可以由導電材料如金屬或金屬組合物/合金,包括銅、鋁、錫、鎳、金、銀等所做成的。在實施例中,基板面板可以是剛性的或可以是柔韌的(例如,“柔性”基板或柔性電路)。絕緣材料可以由陶瓷、玻璃、塑膠、膠帶和/或其他合適的材料所做成。例如,基板面板的絕緣層可以由有機材料如BT(雙馬來醯亞胺三嗪)層壓材料/樹脂、柔性膠帶材料如聚醯亞胺、阻燃劑玻璃纖維複合基板材料(例如,FR-4)等所做成的。導電和非導電層可以堆疊和層壓在一起,或互相耦合在一起,以本領域的技術人員所知悉的方式,形成基板面板中的基板204。
在步驟104中,分割基板面板以分離成多個基板。在實施例中,本領域的技術人員知悉,可以以任何方式分割基板面板,例如基板面板200、400和500,以形成分離的
基板204。例如,可以使用鋸子(例如,鋸切割)、鐳射,或根據任何其他分割技術,來分割基板面板。圖6示出了根據本發明實施例的從基板面板分割出來的第一基板204a和第二基板204b的側面圖。
在實施例中,圖1的流程100可以包括進一步的圖7所示的步驟702。在步驟702中,可以在基板面板中測試基板,以確定一套工作基板。在實施例中,可以在基板面板,例如基板面板200、400和500中的一個中測試基板204,以確定工作基板(通過測試的基板204)和非工作基板(測試失敗的基板204)。本領域的技術人員知悉,可以在基板204上執行任何類型和數量的測試。例如,可以執行功能測試(例如,通過探針接觸基板204的導電形體,來提供測試信號和衡量測試結果),還可以執行環境測試等。
在實施例中,對基板面板中的在步驟702中被確定為非工作基板204進行標記。例如,可以使用油墨、鐳射打標,或其他類型的標記,來對非工作基板進行標記,以標示它們是非工作的。在這種方式中,識別出任何非工作基板,使得不對它們進行進一步的處理/使用。應當注意的是,從基板面板中將基板204分割出來(在圖1的步驟104),而不是在基板條內(例如,如結合圖2的基板面板200所進行的描述)就對基板204進行處理形成IC封裝,可以將個別的非工作基板從進一步的處理/使用中移除,而不是潛在地將整個含有一些工作基板的基板條丟棄。在這種方式中,不浪費工作基板。
正如上面所述,IC封裝可以包括一個或多個IC晶片。
本領域的技術人員知悉,可以在晶圓中製造IC晶片,並以任何方式將其從晶圓中分離出來。
例如,可以根據圖8所示的步驟802產生這樣的晶片。在步驟802中,將晶圓分割成多個積體電路晶片,每一個積體電路晶片包括積體電路區域。例如,圖9示出了示例晶圓900的俯視圖。晶圓900可以是矽、砷化鎵或其他晶圓類型。如圖9所示,晶圓900含有由多個積體電路區域902(圖9中所示的小矩形)定義的表面。將每一個積體電路區域902封裝在IC封裝中,例如球柵陣列封裝。晶圓900中可以包括許多積體電路區域902,包括10s、100s、1000s,甚至更大的數量。
圖10示出了晶圓900的剖視圖,示出第一積體電路區域902a和第二積體電路區域902b。如圖10所示,積體電路區域902a和902b的每一個都包括多個接線端1002(例如,接線端1002a-1002c),接線端1002是積體電路區域902的電信號(例如,輸入-輸出信號、電源信號、接地信號、測試信號等)的接入點(例如,也被稱為“晶片墊”、“I/O墊”等)。在晶圓900的表面上可以有任何數量的接線端1002適用於每一個積體電路區域902,包括10s、100s,甚至更大數量的接線端1002。
可以通過背面研磨使晶圓900隨意地變薄。例如,如果需要和/或必須,可以在晶圓900上執行背面研磨處理,來減少晶圓900的厚度,以得到所需的量。然而,不一定需要在所有的實施中執行晶圓900的變薄處理。本領域的技術人員知悉,可以以任何方式使晶圓900變薄。晶圓900可以製造得盡可能薄,以幫助使得到的封裝的厚度減至最
低,該結果的封裝包括積體電路區域902。此外,可以在晶圓900中測試每一個積體電路區域902。例如,測試探針接觸晶圓900中的接線端1002,來提供測試輸入信號和接收測試結果信號,以測試每一個積體電路區域902。
本領域的技術人員知悉,根據圖8的步驟802,可以以任何適當的方式將晶圓900分割/切塊,使得積體電路區域彼此物理地分開。例如,可以以常規或其他方式使用鋸子、刳刨機、鐳射等來分割晶圓900。圖11示出了已分別從彼此中分割出來形成晶片1102a和1102b的積體電路區域902a和902b的剖視圖。根據晶圓900的積體電路區域902的數量,可以將晶圓900分割成10s、100s、1000s,甚至更大數量的晶片1102。
在實施例中,組裝/製造的IC封裝包括基板(例如基板204)和IC晶片(例如晶片1102)。應當注意的是,可以在製造IC封裝的設施的同一設施中形成和/或分割用於製造IC封裝的基板和/或晶片。或者,也可以在與製造IC封裝的設施獨立/不同的設施中形成和/或分割用於製造IC封裝的基板和/或晶片。如果在與製造IC封裝的設施不同的設施中分割基板和晶片,僅需將所分割的通過測試的基板和/或晶片(即工作基板和/或工作晶片)運送到製造IC封裝的設施。在這種方式中,IC封裝的製造工藝並不需要耗費資源,避免使用非工作基板和/或晶片。例如,當在基板條中形成IC封裝時,在條中的一些基板是非工作的,IC封裝的製造工藝為了避免浪費工作晶片,避免將工作晶片連接在基板條中的非工作基板上。在本發明所描述的實施例中,在以
下情況下是不需要這種避免的,當基板已經分割好時,在將晶片連接到所分割的基板之前,丟棄非工作的所分割的基板。
在實施例中,可以以各種不同的方式製造IC封裝。例如,圖12示出了根據本發明實施例的組裝IC封裝的流程1200。為了說明的目的,下面結合圖13-23來對流程1200進行描述。在本發明提供的討論下,其他的結構性和操作性實施例,對於本領域技術人員來說是顯而易見的。此外,不一定需要按所示的循序執行流程1200的步驟,而可以按其他順序來執行。流程1200如下所述。
流程1200開始於步驟1202,在步驟1202中,將所分離的基板的至少子集連接在載體的表面。在一個實施例中,將從上面所述的基板面板中分割出來的封裝基板如基板204連接在載體的表面。在一個實施例中,將從基板面板中分割出來的通過測試的基板的子集(例如,如結合圖7進行描述的工作基板)連接在載體上。不將沒有通過測試的基板(例如,非工作基板)連接在載體上。
可以使用任何合適類型的載體,包括由陶瓷、玻璃、塑膠、半導體材料(例如,矽、砷化鎵等)、金屬或其他材料組成的載體,來接收所分離的基板。載體可以具有用於接收基板204的平坦的表面。這樣的載體可以具有任何外形輪廓,包括圓形、矩形或其他形狀。例如,圖13和圖14示出了根據本發明實施例的示例載體基板。圖13示出了圓形的載體1302。在一個實施例中,載體1302可以是半導體晶圓(例如,矽或砷化鎵),或可以由其他材料如塑膠、陶瓷、玻璃、金屬等組成。圖14示出了方形的載體1402。例
如,在一個實施例中,載體1402可以由材料如塑膠、陶瓷、玻璃、金屬等組成。
圖15示出了根據本發明實施例的載體1302的示意圖,載體1302具有連接多個基板204的平坦的表面1502。為了說明的目的,圖15(和另外的附圖)示出了載體1302,但在其他實施例中,可以使用圖14的載體1402或其他載體。可以以任何方式,包括通過利用取放設備、自動對準工藝或其他技術,來將基板204放置和/或定位在載體1302的表面1502上。在將基板204放置在表面1502之前,可以使用黏合劑材料黏到表面1502和/或基板204的表面,以使基板204黏附於表面1502。可以使用任何合適的黏合劑材料,包括環氧樹脂、膠膜等。
在圖15的示例中,示出了21個連接在載體1302的表面1502的基板204。然而,在實施例中,可以將任意數量的基板204連接在載體的表面,包括10個、100個,或甚至數千個基板204。在一個實施例中,可以將基板204彼此相鄰(彼此接觸)地定位在載體1302的表面1502上。在另一個實施例中,可以將基板204間隔地分開定位在載體1302的表面1502上,如圖15所示。根據具體的應用,基板204可以以任何距離間隔地分開,該局裡被確定用於特殊的應用。
參考回圖12,在步驟1204中,將一個或多個晶片貼裝在載體上的每一個基板。在實施例中,可以將一個或多個晶片,例如圖11的晶片1102a和/或晶片1102b,貼裝在連接於載體的每一個基板204。例如,圖16示出了根據本發明一個實施例的連接上基板204的且每一個基板204連接
上IC晶片1102的載體1302的示意圖。可以以任何方式,包括通過利用取放設備、自動對準工藝或其他技術,來將晶片1102放置和/或定位在基板204上。晶片1102的接線端可以與基板204上的導電焊盤墊對準,以將晶片1102的信號耦合至基板204的佈線。例如,可以使用焊料或其他導電材料(例如,金屬或金屬組合物/合金)將接線端耦合至導電墊。在將晶片1102放置在基板204之前,使用黏合劑材料黏到基板204的表面和/或晶片1102的非活性表面。可以使用黏合劑材料以將晶片1102黏附於基板204。可以使用任何合適的黏合劑材料,包括常規的鏡片連接材料、環氧樹脂、膠膜等。
例如,圖17示出了根據本發明實施例的部分載體1302的剖視圖。如圖17所示,將基板204a和204b連接在載體1302的表面1502。基板204a和204b的每一個含有相對的第一表面1702和第二表面1704,其中第二表面1704連接在載體1302的表面1502。將晶片1102a連接在基板204a的第一表面1702,並在這個過程中將晶片602b連接在基板204b的第一表面1702。在圖17的示例中,使用多個柱塞1708作為在每一個晶片1102和基板204之間的互連。例如,如圖17所示,在基板204b的第一表面1702上的導電特性(例如,導電墊、佈線等)上形成(例如,電鍍)多個柱塞1708。柱塞1708形成用於將晶片1102a和1102b連接裝到基板204a和204b的導電觸點(conductive contacts)。對晶片1102b的接線端1706進行定位,使其與柱塞1708接觸,以及可以回流焊柱塞1708,以將晶片1102b的接線端1706連接至基板204b的第一表面1702上的導電
形體(另外,或者是黏合劑材料)。如圖17所示,晶片1102a的接線端1706與基板204a的第一表面1702上的柱塞1708接觸和相連接,以將晶片1102a的接線端1706連接至基板204a的第一表面1702上的導電形體。柱塞1708可以是由任何合適的導電材料包括金屬(例如,金(Au)、銅(Cu)等)、金屬組合物/合金(例如,焊料等)、導電塗層材料的聚合形成等來做成的。
此外,應當注意的是,晶片1102的接線端1706包括晶片1102的信號墊,以及可以包括在晶片墊上形成的一個或多個金屬層,被稱為凸點下金屬(UBM)層。UBM層通常是一個或多個金屬層形成的(例如,金屬沉積-電鍍、濺射等),提供在晶片墊和額外的佈線和/或封裝互連機制如柱塞或焊球之間的強壯的介面。
圖18示出了根據本發明另一個實施例的載體1302的部分的剖視圖。如圖18所示,將基板204a和204b連接在載體1302的表面1502。基板204a和204b的每一個含有相對的第一表面1702和第二表面1704,其中第二表面1704連接在載體1302的表面1502。將晶片1102a連接在基板204a的第一表面1702,並在這個過程中將晶片602b連接在基板204b的第一表面1702。在圖18的示例中,使用多個凸點互連(焊接凸點)作為在每一個晶片1102和基板204之間的互連。例如,如圖18所示,在晶片1102b的接線端1706上形成多個凸點互連1802。對晶片1102b的接線端1706/凸點互連1802進行定位,使其與基板204b的第一表面1702上的導電形體接觸(另外,或者是黏合劑材料),以及可以回流焊凸點互連1802,以將接線端1706連接至基
板204b的第一表面1702上的導電特性。如圖18所示,通過回流焊凸點互連1802,將晶片1102a的接線端1706連接至基板204a的第一表面1702上的導電形體。
應當注意的是,圖16-18所示的由基板204和晶片1102形成的連接在載體(例如,載體1302或1402)上的結構可稱為“重建面板”。這是至少部分地因為貼裝在載體上的基板204可以看作是基板面板例如基板面板200、400和500(圖2、4和5)的重建形式。
此外,應當注意的是,按圖12所示的循序執行步驟1202和1204,或按相反的順序,這樣在步驟1202之前執行步驟1204。例如,在將基板204(和晶片1102)連接在載體1302的表面1502之前,將圖16所示的晶片1102連接在基板204。在一個實施例中,可以將晶片1102連接在分割的基板204(即,已彼此分離的基板204)。或者,在另一個實施例中,當基板204仍然是以面板形式時(即,基板204仍然在基板面板中彼此相連接),可以將晶片1102連接在基板204。
參考回圖12,在步驟1206中,在載體上使用模塑膠對晶片和基板進行封裝。例如,圖19示出了根據本發明實施例的含有封裝好的晶片和基板的載體1302的側面剖視圖。如圖19所示,將多個基板204a-204e連接在載體1302的表面1502,並將多個晶片1102a-1102e連接在基板204a-204e。此外,在載體1302上,模塑膠1902對基板204a-204e和晶片1102a-1102e進行封裝。模塑膠1902是可用於在載體1302上對基板204a-204e和晶片1102a-1102e進行封裝的封裝材料的例子。模塑膠1902可以以任何方式
應用於載體1302,包括根據真空成型工藝等。例如,在一個實施例中,模子定位在載體1302(連接有基板和晶片)的表面1502上,以及可以將模塑膠1902插入到模子中(例如,以液態形式),並使其固化以在載體1302上對基板204a-204e和晶片1102a-1102e進行封裝。合適的封裝材料,包括模塑膠,是本領域的技術人員知悉的,還包括樹脂,環氧樹脂等。
在步驟1208中,從所封裝的晶片和基板中拆卸載體,以形成模塑組裝,該模塑組裝包括用於封裝晶片和基板的模塑膠。例如,圖20示出了根據本發明實施例的已從所封裝的晶片和基板中移除或拆卸出來的載體1302的側面剖視圖。在圖20中,基板204a-204e、晶片1102a-1102e和模塑膠1902形成從載體1302中拆卸出來的模塑組裝2002。基板204a-204e的第二表面1704齊平於並暴露於模塑組裝2002的表面(圖20中的底部表面)。否則,在模塑組裝2002中通過模塑膠1902對晶片1102a-1102e和基板204a-204e進行封裝。可以以任何方式從模塑組裝2002中拆卸載體1302。例如,可以從載體1302中將模塑組裝2002剝落下來,可以對模塑組裝2002和/或載體1302進行加熱或冷卻,引起或使能載體1302從模塑組裝2002中拆卸出來等。在一個實施例中,模塑膠1902貼附於基板204a-204e比連接附於載體1302更為牢固(例如,比將基板204a-204e連接在載體1302的黏合劑材料更為牢固),以使能基板204a-204e和模塑膠1902一起從載體1302中拆卸出來,而不是在拆卸後基板204a-204e仍留在載體1302上。
在步驟1210中,將多個互連連接在模塑組裝的表面上
的每一個基板。例如,在實施例中,將多個互連連接在模塑組裝2002中的基板204的第二表面1704。可以使用互連來使能將模塑組裝2002貼裝在電路板(例如,印刷電路板等)而產生IC封裝。這些互連的例子包括BGA封裝的凸點互連(例如,焊球)、引腳(例如,陳列引腳封裝(PGA)的)、貼(post),或其他類型的互連。模塑組裝2002的基板204可以以任何方式,包括根據常規和專有的技術,來採用這些互連。
例如,圖21示出了根據本發明實施例的連接有焊球2102的圖20的模塑組裝2002的側面剖視圖。如圖21所示,將多個焊球2102連接在每一個基板204a和204b的第二表面1704。將每一個焊球2102連接在相對應的焊球墊。這樣,每個IC晶片1102的接線端的信號通過在IC晶片1102和基板204之間的互連(例如,柱塞或凸點)、基板204的表面1702上的佈線、導通基板204的通孔、隨意存在於基板204的進一步的佈線層的額外佈線和基板204的表面1704到焊球墊的佈線,與焊球2102電連接。
參考回圖12,在步驟1212中,分割模塑組裝,以形成多個積體電路封裝,每一個積體電路封裝包括至少一個晶片和基板。例如,圖22示出了從圖21的模塑組裝2002中分割出來的第一IC封裝2202a和第二IC封裝2202b。可以從模塑組裝中分割出許多IC封裝2202,包括10s、100s、甚至數千個IC封裝2202。如圖22所示,IC封裝2202a包括連接在基板204a的晶片1102a、在基板204a上封裝晶片1102a的模塑膠1902,以及連接在基板204a的第二表面1704的焊球2102。此外,IC封裝2202b包括貼裝在基板
204b的晶片1102b、在基板204b上封裝晶片1102b的模塑膠1902,以及連接在基板204b的第二表面1704的焊球2102。
本領域的技術人員知悉,可以以任何適當的方式從模塑組裝2002中分割IC封裝2202,使得它們彼此物理地分開。例如,可以以常規或其他方式使用鋸子、刳刨機、鐳射等來分割IC封裝2202。可以通過切透模塑膠1902以使IC封裝2202a和2202b彼此分離和與其他IC封裝2202(圖21未示出)分離,從圖21的模塑組裝2002中分割出圖22的IC封裝2202a和2202b。在一個實施例中,可以在基板204a和204b的周邊邊緣鄰近直接執行切割,使得模塑膠1902不留在IC封裝2202a和2202b中的基板204a和204b的周邊邊緣的周圍(即,暴露周邊基板邊緣)。或者,如圖22所示,可以在離基板204a和204b的周邊邊緣一定的距離執行切割,使得一些模塑膠1902留在IC封裝2202a和2202b中的基板204a和204b的周邊邊緣的周圍(即,不暴露周邊基板邊緣)。
例如,圖23示出了從模塑組裝2002中分割出來的IC封裝2202a的側面剖視圖。如圖23所示,基板204a的外部邊緣鄰近的空間2302填滿模塑膠1902(例如,基板204a的四周邊緣),形成圍繞基板204a的模塑膠1902的環。在這種方式中,僅僅是基板204a的第二表面1704是暴露的(即,沒有被模塑膠1902覆蓋)。這使能通過模塑膠1902保護基板204a的外部邊緣免受環境的影響。
此外,模塑膠1902的周邊環使能隨意地形成尺寸過小的基板204,使用模塑膠1902來彌補所減少的尺寸。例如,
需要7mm*7mm尺寸的IC封裝2202a。這樣,可以以6.6mm*6.6mm的尺寸形成基板204a,並對基板204a周圍的空間2302中的模塑膠1902進行切割(在分割過程中,或者之後)以使其具有0.2mm的厚度,來使得IC封裝2202a有以7mm*7mm尺寸。在這種方式中,通過在基板面板中包括較小的基板,進一步提高基板面板的利用率,因此,在基板面板中可以包含大量的基板。此外,當基板204a不能完全擴展到IC封裝2202a的邊緣時,IC封裝2202a包括更少的基板204a,而包括更多的模塑膠1902,降低了IC封裝2202a的總成本(因為相同體積的模塑膠1902要比基板204a便宜)。
儘管以上對本發明的各個實施例進行了描述,但應該理解的是,它們僅用於示例說明而非限制目的。對本領域技術人員而言顯而易見的是,在不背離本發明的精神和範圍的情況下可對其形式和細節作出各種改變。因此,本發明的寬度和範圍並不應受限於上述任一示例性實施例,而僅應該依照以下所附的申請專利範圍及其等效替換來限定。
200‧‧‧基板面板
202a-202l‧‧‧基板條部分
204‧‧‧基板
204a-204e‧‧‧基板
400‧‧‧基板面板
402‧‧‧陣列
404‧‧‧邊緣部分
500‧‧‧基板面板
900‧‧‧晶圓
902‧‧‧集成電路區域
902a‧‧‧第一集成電路區域
902b‧‧‧第二集成電路區域
1002a-1002c‧‧‧接線端
1102‧‧‧晶片
1102a-1102e‧‧‧晶片
1302‧‧‧載體
1402‧‧‧載體
1502‧‧‧表面
1702‧‧‧第一表面
1704‧‧‧第二表面
1706‧‧‧接線端
1708‧‧‧柱塞
1802‧‧‧凸點互連
1902‧‧‧模塑料
2002‧‧‧模塑組裝
2102‧‧‧焊球
2202a‧‧‧第一IC封裝
2202b‧‧‧第二IC封裝
2302‧‧‧空間
圖1是根據本發明實施例的形成積體電路封裝基板的流程圖。
圖2是包含多個基板條的基板面板的示例的俯視圖。
圖3是根據本發明實施例的形成積體電路封裝基板的過程的示意圖。
圖4和圖5是根據本發明實施例的被充分地填滿基板
的基板面板的示意圖。
圖6是根據本發明實施例的第一和第二分割基板的側面圖。
圖7是根據本發明實施例的測試基板面板的基板的過程的示意圖。
圖8是根據本發明實施例的分割晶圓以形成積體電路晶片的過程的示意圖。
圖9是晶圓的示例的俯視圖。
圖10是圖9中的晶圓的剖視圖,示出了第一和第二積體電路區域。
圖11是根據本發明實施例的積體電路區域分割成分離的晶片的剖視圖。
圖12是根據本發明實施例的形成積體電路封裝的流程圖。
圖13和圖14是根據本發明實施例的載體基板的示例的示意圖。
圖15是根據本發明實施例的連接上基板的載體的表面的示意圖。
圖16是根據本發明實施例、圖15中的基板連接上晶片的示意圖;圖17和圖18是根據本發明實施例的將晶片連接在載體上的基板的剖視圖。
圖19是根據本發明實施例的貼裝有基板和晶片的載體的剖視圖,其中,使用應用於載體的封裝材料來封裝基板和晶片。
圖20是根據本發明實施例的圖19中的載體已從封裝
材料、基板和晶片中分離出來的剖視圖。
圖21是根據本發明實施例的含有應用於封裝基板的凸點互連的模塑組裝的剖視圖。
圖22是根據本發明實施例的從圖21的模塑組裝中分割出來的積體電路封裝的側面剖視圖。
圖23是根據本發明實施例的包含環繞封裝基板的邊緣的封裝材料的積體電路封裝的側面剖視圖。
Claims (10)
- 一種積體電路封裝之組裝方法,所述方法包括:形成包括多個基板的基板面板,每一個所述基板包括佈線;分割所述基板面板,以分離成所述多個基板;將所分離的基板的至少子集連接在載體的表面;將一個或多個晶片貼裝在所述載體上的每一個所述基板上;在所述載體上使用模塑膠對所述晶片和所述基板進行封裝;從所封裝的晶片和基板中拆卸所述載體,以形成模塑組裝,所述模塑組裝包括用於封裝所述晶片和基板的所述模塑膠;將多個互連連接在所述模塑組裝的表面上的每一個所述基板;及分割所述模塑組裝,以形成多個積體電路封裝,每一個積體電路封裝包括至少一個所述晶片和基板。
- 如申請專利範圍第1項所述的積體電路封裝之組裝方法,其中所述方法進一步包括:使用柱塞對在所述基板面板中的所述基板進行電鍍,以形成用於將所述晶片貼裝在所述基板的導電觸點。
- 如申請專利範圍第1項所述的積體電路封裝之組裝方法,其中所述形成包括多個基板、且每個基板包括佈線的基板面板包括:形成所述基板面板來包含陣列中的所述基板,除了圍繞所述陣列的所述基板面板的周邊邊緣區域之外,所述陣列填 滿所述基板面板。
- 如申請專利範圍第1項所述的積體電路封裝之組裝方法,其中所述將所分離的基板的至少一個子集連接在載體的表面包括:對所分離的基板進行定位,使其在所述載體的所述表面上間隔地分開。
- 如申請專利範圍第4項所述的積體電路封裝之組裝方法,其中所述在所述載體上使用模塑膠對所述晶片和所述基板進行封裝包括:填充在所分離的基板與所述模塑膠之間的空間。
- 如申請專利範圍第5項所述的積體電路封裝之組裝方法,其中所述分割所述模塑組裝,以形成多個積體電路封裝包括:分割所述模塑組裝,使得每一個積體電路封裝包括圍繞所包含的基板的外部邊緣的模塑膠的周邊環。
- 一種積體電路封裝之組裝方法,所述方法包括:接收多個分離的基板;將所述基板連接在載體的表面;將一個或多個晶片貼裝在所述載體上的每一個所述基板;在所述載體上使用模塑膠對所述晶片和所述基板進行封裝;從所封裝的晶片和基板中拆卸所述載體,以形成模塑組裝,所述模塑組裝包括用於封裝所述晶片和基板的所述模塑膠;將多個互連連接在所述模塑組裝的表面上的每一個所述基板;及 分割所述模塑組裝,以形成多個積體電路封裝,每一個積體電路封裝包括至少一個所述晶片和基板。
- 如申請專利範圍第7項所述的積體電路封裝之組裝方法,所述將所述基板連接在載體的表面包括:對所述基板進行定位,使其在所述載體的所述表面上間隔地分開。
- 如申請專利範圍第8項所述的積體電路封裝之組裝方法,所述在所述載體上使用模塑膠對所述晶片和所述基板進行封裝包括:填充位於帶有所述模塑膠的所述基板之間的空間。
- 一種積體電路封裝,所述積體電路封裝包括:基板,其含有相對的第一和第二表面;晶片,其貼裝在所述基板的所述第一表面;及模塑膠,用於封裝所述基板的第一表面上的所述晶片,且形成圍繞所述基板的外部邊緣的周邊環。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/071,799 US8367475B2 (en) | 2011-03-25 | 2011-03-25 | Chip scale package assembly in reconstitution panel process format |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201301415A true TW201301415A (zh) | 2013-01-01 |
TWI541918B TWI541918B (zh) | 2016-07-11 |
Family
ID=46876665
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW101110350A TWI541918B (zh) | 2011-03-25 | 2012-03-26 | 積體電路封裝之組裝方法及其封裝 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8367475B2 (zh) |
KR (1) | KR101402868B1 (zh) |
CN (1) | CN102709202B (zh) |
HK (1) | HK1169744A1 (zh) |
TW (1) | TWI541918B (zh) |
Families Citing this family (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9620413B2 (en) | 2012-10-02 | 2017-04-11 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of using a standardized carrier in semiconductor packaging |
US9496195B2 (en) * | 2012-10-02 | 2016-11-15 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of depositing encapsulant along sides and surface edge of semiconductor die in embedded WLCSP |
US9704780B2 (en) | 2012-12-11 | 2017-07-11 | STATS ChipPAC, Pte. Ltd. | Semiconductor device and method of forming low profile fan-out package with vertical interconnection units |
US9240331B2 (en) | 2012-12-20 | 2016-01-19 | Stats Chippac, Ltd. | Semiconductor device and method of making bumpless flipchip interconnect structures |
US9287204B2 (en) | 2012-12-20 | 2016-03-15 | Stats Chippac, Ltd. | Semiconductor device and method of bonding semiconductor die to substrate in reconstituted wafer form |
US9245770B2 (en) | 2012-12-20 | 2016-01-26 | Stats Chippac, Ltd. | Semiconductor device and method of simultaneous molding and thermalcompression bonding |
US9704824B2 (en) | 2013-01-03 | 2017-07-11 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming embedded wafer level chip scale packages |
US9721862B2 (en) | 2013-01-03 | 2017-08-01 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of using a standardized carrier to form embedded wafer level chip scale packages |
KR20150023202A (ko) * | 2013-08-23 | 2015-03-05 | 강경순 | 프로세스 모듈 및 그 제조 방법과, 프로세스 모듈을 이용한 기판 처리 방법 |
TWI658543B (zh) * | 2013-12-05 | 2019-05-01 | 新加坡商史達晶片有限公司 | 在半導體封裝中使用標準化載體的半導體裝置及方法 |
US9524942B2 (en) * | 2013-12-18 | 2016-12-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip-on-substrate packaging on carrier |
US9704769B2 (en) | 2014-02-27 | 2017-07-11 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming encapsulated wafer level chip scale package (EWLCSP) |
US20150303170A1 (en) * | 2014-04-17 | 2015-10-22 | Amkor Technology, Inc. | Singulated unit substrate for a semicondcutor device |
KR101563909B1 (ko) | 2014-08-19 | 2015-10-28 | 앰코 테크놀로지 코리아 주식회사 | 패키지 온 패키지 제조 방법 |
US9972593B2 (en) * | 2014-11-07 | 2018-05-15 | Mediatek Inc. | Semiconductor package |
US9443785B2 (en) * | 2014-12-19 | 2016-09-13 | Advanced Semiconductor Engineering, Inc. | Semiconductor package |
KR102335106B1 (ko) | 2015-06-19 | 2021-12-03 | 삼성전자 주식회사 | 발광 소자 패키지 및 그 제조 방법 |
JP2017054888A (ja) * | 2015-09-08 | 2017-03-16 | 株式会社ディスコ | ウエーハの加工方法 |
CN105329850B (zh) * | 2015-10-21 | 2017-03-08 | 美新半导体(无锡)有限公司 | 圆片级芯片尺寸封装的测试方法 |
KR101685849B1 (ko) * | 2015-11-04 | 2016-12-13 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 모듈 제조 방법 및 이를 이용한 반도체 패키지 모듈 |
US10535611B2 (en) * | 2015-11-20 | 2020-01-14 | Apple Inc. | Substrate-less integrated components |
KR20170085833A (ko) * | 2016-01-15 | 2017-07-25 | 삼성전기주식회사 | 전자 부품 패키지 및 그 제조방법 |
DE102017215177A1 (de) * | 2016-09-02 | 2018-03-08 | Idex Asa | Verfahren zur Herstellung eines Abdeckungselements geeignet für einen Fingerprint Sensor |
WO2018072183A1 (en) * | 2016-10-20 | 2018-04-26 | Texas Instruments Incorporated | Method and apparatus for detecting and removing defective integrated circuit packages |
US10304716B1 (en) * | 2017-12-20 | 2019-05-28 | Powertech Technology Inc. | Package structure and manufacturing method thereof |
CN116169110A (zh) | 2018-02-24 | 2023-05-26 | 华为技术有限公司 | 一种芯片及封装方法 |
JP7189672B2 (ja) * | 2018-04-18 | 2022-12-14 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
US10593630B2 (en) * | 2018-05-11 | 2020-03-17 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and method for manufacturing the same |
WO2019222330A2 (en) * | 2018-05-17 | 2019-11-21 | Corning Incorporated | Singulated electronic substrates on a flexible or rigid carrier and related methods |
US10643957B2 (en) * | 2018-08-27 | 2020-05-05 | Nxp B.V. | Conformal dummy die |
US10755994B2 (en) | 2018-10-29 | 2020-08-25 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and semiconductor substrate |
CN109545694B (zh) * | 2018-11-13 | 2020-11-17 | 无锡中微高科电子有限公司 | 一种破损基板的模封方法 |
CN110444480A (zh) * | 2019-07-24 | 2019-11-12 | 浙江荷清柔性电子技术有限公司 | 制作柔性芯片的方法、柔性芯片 |
Family Cites Families (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5829128A (en) | 1993-11-16 | 1998-11-03 | Formfactor, Inc. | Method of mounting resilient contact structures to semiconductor devices |
US5897326A (en) | 1993-11-16 | 1999-04-27 | Eldridge; Benjamin N. | Method of exercising semiconductor devices |
US5832601A (en) | 1993-11-16 | 1998-11-10 | Form Factor, Inc. | Method of making temporary connections between electronic components |
US5878486A (en) | 1993-11-16 | 1999-03-09 | Formfactor, Inc. | Method of burning-in semiconductor devices |
US5806181A (en) | 1993-11-16 | 1998-09-15 | Formfactor, Inc. | Contact carriers (tiles) for populating larger substrates with spring contacts |
US6741085B1 (en) | 1993-11-16 | 2004-05-25 | Formfactor, Inc. | Contact carriers (tiles) for populating larger substrates with spring contacts |
US5983493A (en) | 1993-11-16 | 1999-11-16 | Formfactor, Inc. | Method of temporarily, then permanently, connecting to a semiconductor device |
US5852870A (en) | 1996-04-24 | 1998-12-29 | Amkor Technology, Inc. | Method of making grid array assembly |
US5859475A (en) | 1996-04-24 | 1999-01-12 | Amkor Technology, Inc. | Carrier strip and molded flex circuit ball grid array |
US6492203B1 (en) | 1997-04-30 | 2002-12-10 | Hitachi Chemical Company, Ltd. | Semiconductor device and method of fabrication thereof |
US6111324A (en) | 1998-02-05 | 2000-08-29 | Asat, Limited | Integrated carrier ring/stiffener and method for manufacturing a flexible integrated circuit package |
US6214640B1 (en) | 1999-02-10 | 2001-04-10 | Tessera, Inc. | Method of manufacturing a plurality of semiconductor packages |
US6388335B1 (en) * | 1999-12-14 | 2002-05-14 | Atmel Corporation | Integrated circuit package formed at a wafer level |
US6593644B2 (en) * | 2001-04-19 | 2003-07-15 | International Business Machines Corporation | System of a package fabricated on a semiconductor or dielectric wafer with wiring on one face, vias extending through the wafer, and external connections on the opposing face |
US6903278B2 (en) * | 2001-06-29 | 2005-06-07 | Intel Corporation | Arrangements to provide mechanical stiffening elements to a thin-core or coreless substrate |
TW560018B (en) | 2001-10-30 | 2003-11-01 | Asia Pacific Microsystems Inc | A wafer level packaged structure and method for manufacturing the same |
US7023347B2 (en) | 2002-08-02 | 2006-04-04 | Symbol Technologies, Inc. | Method and system for forming a die frame and for transferring dies therewith |
US6903456B2 (en) * | 2003-10-08 | 2005-06-07 | Tong Hsing Electric Industries, Ltd. | Package carrier having multiple individual ceramic substrates |
US7358119B2 (en) | 2005-01-12 | 2008-04-15 | Asat Ltd. | Thin array plastic package without die attach pad and process for fabricating the same |
US7538438B2 (en) * | 2005-06-30 | 2009-05-26 | Sandisk Corporation | Substrate warpage control and continuous electrical enhancement |
US7807505B2 (en) * | 2005-08-30 | 2010-10-05 | Micron Technology, Inc. | Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods |
US7378733B1 (en) | 2006-08-29 | 2008-05-27 | Xilinx, Inc. | Composite flip-chip package with encased components and method of fabricating same |
US7985621B2 (en) * | 2006-08-31 | 2011-07-26 | Ati Technologies Ulc | Method and apparatus for making semiconductor packages |
US8193034B2 (en) * | 2006-11-10 | 2012-06-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertical interconnect structure using stud bumps |
US7683380B2 (en) | 2007-06-25 | 2010-03-23 | Dicon Fiberoptics, Inc. | High light efficiency solid-state light emitting structure and methods to manufacturing the same |
US7923298B2 (en) * | 2007-09-07 | 2011-04-12 | Micron Technology, Inc. | Imager die package and methods of packaging an imager die on a temporary carrier |
US20090091025A1 (en) | 2007-10-04 | 2009-04-09 | Agency For Science, Technology And Research | Method for forming and releasing interconnects |
US8124447B2 (en) | 2009-04-10 | 2012-02-28 | Advanced Semiconductor Engineering, Inc. | Manufacturing method of advanced quad flat non-leaded package |
US8143097B2 (en) * | 2009-09-23 | 2012-03-27 | Stats Chippac, Ltd. | Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP |
US8569894B2 (en) | 2010-01-13 | 2013-10-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
-
2011
- 2011-03-25 US US13/071,799 patent/US8367475B2/en active Active
-
2012
- 2012-03-23 KR KR1020120030128A patent/KR101402868B1/ko not_active IP Right Cessation
- 2012-03-26 TW TW101110350A patent/TWI541918B/zh not_active IP Right Cessation
- 2012-03-26 CN CN201210082855.4A patent/CN102709202B/zh active Active
- 2012-10-18 HK HK12110351.8A patent/HK1169744A1/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
CN102709202B (zh) | 2015-07-01 |
US20120241955A1 (en) | 2012-09-27 |
CN102709202A (zh) | 2012-10-03 |
KR20120109410A (ko) | 2012-10-08 |
US8367475B2 (en) | 2013-02-05 |
TWI541918B (zh) | 2016-07-11 |
HK1169744A1 (zh) | 2013-02-01 |
KR101402868B1 (ko) | 2014-06-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI541918B (zh) | 積體電路封裝之組裝方法及其封裝 | |
US10797024B2 (en) | System-in-package with double-sided molding | |
US8889484B2 (en) | Apparatus and method for a component package | |
TWI608578B (zh) | 具有仿真銅圖案的嵌入式印刷電路板單元之均衡表面的半導體裝置和方法 | |
US7888172B2 (en) | Chip stacked structure and the forming method | |
US20230260920A1 (en) | Chip package and manufacturing method thereof | |
US11205603B2 (en) | Semiconductor package and method manufacturing the same | |
US11508712B2 (en) | Method of manufacturing a package-on-package type semiconductor package | |
US20120187545A1 (en) | Direct through via wafer level fanout package | |
US20160056094A1 (en) | Ball grid array package with more signal routing structures | |
KR101803605B1 (ko) | 패키지화된 반도체 디바이스 및 그 패키징 방법 | |
CN113725096B (zh) | 半导体封装方法及半导体封装结构 | |
KR101375818B1 (ko) | 직접 관통하는 비아 웨이퍼 레벨 팬아웃 패키지 | |
CN115148715A (zh) | 半导体封装方法及半导体封装结构 | |
CN115148714A (zh) | 半导体封装方法及半导体封装结构 | |
CN114446800A (zh) | 堆叠半导体封装方法及堆叠半导体封装结构 | |
CN114446798A (zh) | 半导体封装方法及半导体封装结构 | |
TW201714234A (zh) | 模封互連基板之面板組合構造及其製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |