TW201216430A - Pad configurations for an electronic package assembly - Google Patents
Pad configurations for an electronic package assembly Download PDFInfo
- Publication number
- TW201216430A TW201216430A TW100119804A TW100119804A TW201216430A TW 201216430 A TW201216430 A TW 201216430A TW 100119804 A TW100119804 A TW 100119804A TW 100119804 A TW100119804 A TW 100119804A TW 201216430 A TW201216430 A TW 201216430A
- Authority
- TW
- Taiwan
- Prior art keywords
- row
- pads
- die
- pad
- electronic package
- Prior art date
Links
- 229910000679 solder Inorganic materials 0.000 claims abstract description 37
- 238000000465 moulding Methods 0.000 claims description 13
- 150000001875 compounds Chemical class 0.000 claims description 12
- 239000013078 crystal Substances 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000008188 pellet Substances 0.000 claims description 3
- 230000008878 coupling Effects 0.000 claims description 2
- 238000010168 coupling process Methods 0.000 claims description 2
- 238000005859 coupling reaction Methods 0.000 claims description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims 2
- 241000255925 Diptera Species 0.000 claims 1
- 229910052786 argon Inorganic materials 0.000 claims 1
- 238000000034 method Methods 0.000 description 30
- 239000000758 substrate Substances 0.000 description 28
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 238000009826 distribution Methods 0.000 description 4
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- UHNRLQRZRNKOKU-UHFFFAOYSA-N CCN(CC1=NC2=C(N1)C1=CC=C(C=C1N=C2N)C1=NNC=C1)C(C)=O Chemical compound CCN(CC1=NC2=C(N1)C1=CC=C(C=C1N=C2N)C1=NNC=C1)C(C)=O UHNRLQRZRNKOKU-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 244000025254 Cannabis sativa Species 0.000 description 1
- 102100040428 Chitobiosyldiphosphodolichol beta-mannosyltransferase Human genes 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000008187 granular material Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 210000003813 thumb Anatomy 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- Electric Connection Of Electric Components To Printed Circuits (AREA)
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Description
201216430 六、發明說明: 【相關申請案的交叉參考】 本公開要求2010年6月4日提交的美國臨時專利申請N〇. 61/351,471的優先權,就各方面而言,在此通過引用的方式包 含其整個說明書的全部内容,除了可能存在的與本說明書不一 致的那些部分。 【發明所屬之技術領域】 本公開的實施方式涉及電子封裝組件領域,並且更特別地 涉及用於電子封裝組件的墊的技術、結構以及配置。 【先前技術】 在此出於一般地呈現本公開的上下文的目的而提供了背景 技術描述。在該背景技術部分中所描述的#前署名的發明人的 工作、以及本說明書中的並未以其他方式被判定為巾請時的現 有技術的各方面,均不表示明確地或隱含地縣認為相對於本 公開的現有技術。 積體電路器件(諸如電晶體)形成在其尺寸持續縮減為更 小維度的晶粒或晶片上。晶粒的緊縮維度和相關聯的容納晶粒 的封裝組㈣當前歸路由錄絲自 θ,古 傳統塾結構和/配置如了織。 ㈣彳。就的 【發明内容】 在個實施方式中’本公開包括一種電子封裝組件,該電 201216430 子封裝組件包括:焊接遮罩層,該焊接遮罩層具有至少一個開
口;以及_合_焊接遮罩層的多健,其巾鮮個塾中的I 少-個墊包括⑴第-側,⑻第二側,該第—側佈置為與該 第二侧相對’(iii)端子部分以及(iv)延伸部分,其中在該端 子部分處的該第-側配置為通過轉接遮罩射的該至少一個 開口接納封裝互連結構,該封裝互連結翻以在晶粒與該電子 封裝組件外部的另—電子II件之間路由電錢,並且其中在該 延伸部分處_第二側配置為接絲自該晶粒的-個或多個^ 連接。 在另-實施方式中,本公開包括一種裝置,該裝置包括電 子封裝組件以及印刷電路板,該電子封裝組件包括:谭接遮罩 層,該焊接遮罩層具有至少一個開口;以及輕合到該焊接遮罩 層的多個墊,其中該多個墊中的至少—健包括⑴第一側, (11)第二側’該第一側佈置為與該第二側相s,(iii)端子部 ^以及(iv)延伸部分,其中在該端子部分處的該第一側配置 為通過該焊接遮罩層中的該至少—_σ接納封裝互連結構, 並在該延伸部分處的該第二側配置為接納來自該晶粒的 :個或多個電連接,該印刷電路板使用該封裝互連結難合到 個墊的該端子部分處的該第—側,該封裝互連結構 用以在B曰粒與該印刷電路板之間路由電信號。 早式中’本公開包括-種㈣裝組件,該電 子封裝組件包括:焊接遮罩層,其中鱗接遮罩層罝有至少一 合到該焊接遮罩層的多 個墊中該多個墊中的至少一個塾包括⑴第一側,⑻第 二侧,該第-侧佈置為與該第二侧相對,㈤端子部分 201216430 ^二分。在該端子部分處的該第—侧配置為通過 一個或多個開口接納封裝互連結構。該封襄互連4: :粒與該細裝組件外部的另一電子器件之間路由=在 部分處的該第二側配置為接納來自該晶粒二固 或多個電連接。該電子封裝組件進一 的晶粒墊。該多健包括第—行墊 行==晶粒 粒墊相鄰。糊她_觸^=^該晶 二行墊’該第一行墊佈置為比节第一鄰平仃的第 Α/ 帛—订妓靠近_晶粒墊。 2少兩個墊中的第一墊佈置在該第一行墊 墊中的第二墊佈置在該第二行塾中。 ^個 在另-實施方式中’本公開提供了—㈣作電子封裝崎 ^ 其巾該方法包括提供齡基板並在频牲基板上形成 ,分佈層。該再分佈層包括多個墊並且墊配置為容納晶粒。該 多個墊的至少兩個墊中的每—個包括:⑴第—侧,⑻ 側,該第-側佈置為與該第二側相對,(m)端子部分以及^ 延伸部分。在該端子部分處_第_她合至該犧牲基板,以 及在該延伸部分處的該第二嫩置為接納來自該晶粒的一個或 多個電連接。該多健包括第—行墊,該第—行墊佈置為與該 晶粒墊相鄰。該多個墊包括佈置為與該第一行墊相鄰且平行= 第二行塾’該第-行塾佈置為比該第二行墊更靠近於該晶粒 墊。該至少兩個墊中的第一墊佈置在該第一行墊中,而該至少 兩個墊中的第二墊佈置在該第二行墊中。 在另一實施方式中,本公開包括一種電子封裝組件,該電 子封裝組件包括焊接遮罩層。該焊接遮罩層具有至少一個開 口。該電子封裝組件進一步包括耦合到該焊接遮罩層的多個 201216430 =二端子部分處的該第二=及= =部=該第二側配置為接納來自該晶粒的-‘㊁ 封裝組件進一步包括配置為接納該晶粒的晶粒 鄰二二括帛一打墊,該第一行墊佈置為與該晶粒墊相 墊^第為與該第—行墊相鄰且平行的第二行 塾該第-订藝佈置為比該第二行 的方式中,本公開提供了—種製作電子封裝組件 再八靜^料包括提顯牲紐並德犧牲基板上形成 : 括多個墊並且塾配置為接納晶粒。該 夕:墊的至少一個塾包括:⑴第一侧,⑻第二側,該第一 側佈置為與該第二側相對,㈤端子部分以及㈤延伸部分。 處_第,合至該犧牲基板,以及在該延伸 第一行墊,該第-行墊佈置為與 2。該多健包括佈置為與該第—行墊轉且平行的第二行 |二第一行塾佈置為比該第二行塾更靠近於該晶粒墊。該至 >-個塾的延伸部分在不垂直於該第—行墊的方向中延伸。 子射杜實施方式中,本公開提供—種包括烊接遮罩層的電 子封裝組件。該焊接縣層具有至少—侧^。 件進-步包括搞合到該焊接遮罩層的多個墊。該多個墊中^至 201216430 =一個塾包括⑴第-侧,⑻第二側,該第—侧佈置為與該 第-側姆,(m)端子部分以及(iv) ^伸部分。在該端 =處的該第-側配置為通過該焊接遮罩層中的該至少一個開口 ^封裝互賴構。該雜互連結構在晶粒與該電子封裝組件 獨另-電子ϋ件之間路由電信^在該延伸部分處的該第 -則配置為接納來自該晶粒的—個或多個電連接。該電子封裝 ^牛進-步包括配置為接納該晶粒的晶粒墊。該多健包括第 行墊該帛行墊佈置為與該晶粒塾相鄰 該第-行,鄰且平行的第二行塾,該第—行 ^ 一行墊更錢霞晶粒墊。該多個墊包括佈置為與該第 ^行墊相鄰且平行的第三行墊,該第二行塾佈置為比該第三行 墊更靠近於該晶粒塾。該延伸部分具有在該第一行墊和該第二 行墊之間佈置的終止端。 在另-實施方式中,本公開提供了—種製作電子封裝組件 的方法’其中該方法包括提供犧牲基板並在該犧牲基板上形成 ,分佈層。該再分佈層包括多個墊並且墊配置為接納晶粒。該 多個塾的至少-個墊包括:⑴第—侧,⑻第二侧,該第一 側佈置為與該第二術目對,(iii)端子部分以及⑻延伸部分。 在該端子部分處的該第-_合至該犧牲基板,以及在該延伸 部分處的該第二側配置為接納來自該晶粒的—個或多個電連 接。該多個藝包括第-行塾,該第一行墊佈置為與該晶粒塾相 鄰。該多健包括佈置域該第—行墊相鄰且平行的第二行 塾,該第-行塾佈置為比該第二行墊更靠近於該晶粒塾。該多 個墊包括佈置域对二行墊神且平行料三行墊,該第二 行墊佈置為比該第三行墊更靠近於該晶粒墊。該延伸部分具有
S 201216430 在該第一行墊和該第二行墊之間佈置的終止端。 子封實,式中,本公開提供—種包括_遮草層的電 件進^接遮罩層具有至少—個開σ。該電子封裝組 該焊接遮罩層的多個塾。該多個墊中的一 個或者夕個墊包括(i)第一侧,(丨丨)第二 盥該第-#丨;<:日#+ η 一側,該第一側佈置為 …第-撕目對’(111)端子部分以及(iv)延伸部分 =部=處的該第-侧配置為通過該焊接遮罩層中的該至少一個 互連結構。該封裝互連結構在晶粒與該電子封裝 電子器件之間路由電信號。在該延伸部分處的 該第-側配置為接納來自該晶粒的一個或多個電連接。該電子 進—步包括配置為接納該晶粒的晶粒墊。該多個墊包 括佑署該第—π墊佈置為與該晶粒墊轉。該多個墊包 署該第一行墊相鄰且平行的第二行墊,該第-行墊佈 ^〜一仃墊更靠近於該晶粒墊。該多個墊包括佈置為盥 該第二行塾相鄰且平行的第三行塾,該第二行 第 三行墊更靠近於該晶錄。該延伸部分實質上在包』多個1 的平面上與該端子部分遠離的所有方向中擴展。 在另-實施方式中,本公開提供了一種製作電子封裝組件 $法’其中該方法包括提供犧牲基板並在該犧牲基板上形成 ,分佈層。該再分佈層包括多個墊並且墊配置為接納晶粒。該 夕個塾的-個或者多個墊包括:⑴第一側,(ii)第二側,該 第-側佈置為與該第二側相對,㈤端子部分以及⑼)延伸 部分。在該端子部分處的該第一側耦合至該犧牲基板,以及在 該延伸部分處的該第二侧配置為接納來自該晶粒的—個或多個 電連接。該多個墊包括第一行塾,該第一行藝佈置為與該晶粒 201216430 = 目鄰。該多個墊包括佈置為與該第-行墊相鄰且平行的第二 第—行墊佈置為比該第二行墊更靠近於該晶粒塾。該 夕^括佈置為與該第二行墊相鄰且平行的第三行塾,該 „置為比該第三行塾更靠近於該晶粒墊。該延伸部竹 質上在與該端子部分遠離騎有方向中擴展。 實施方式中,本公開提供—種包括焊接遮罩層的電 T封裝組件。該焊接遮罩層具有至少一個開口。該電子封餘 件進-步包括輕合到該焊接遮罩層的多健。該多個墊中^至 Γ個塾包括⑴第—側,⑻第二側,該第—側佈置為與該 Γ)端子部分以及(iv)延伸部分。在該端子部 二通過轉接遮罩層中的該至少一個開口 外邱^互結構。雜裝互連結構在晶粒與該電子封裳組件 間路由電信號。在該延伸部分處的該第 -側配置為接絲自該晶粒的—個❹個電連接。該電 步包括配置為接納該晶粒的晶粒墊以及佈置為與該曰曰: m目鄰的一個或者多個環狀段結構個或者多個環狀段 π構為該晶粒提供電源連接和/或接地連接。 在另-實施方式中,本公職供了—種製作電 其巾該方法包括提供犧牲基板並在該犧牲基板上形 =:。該再_包括⑴多個塾,⑻配置為接納晶: ΐ二Γ佈置為與該晶粒塾相鄰的-個或者多個 ^ η 者多個環狀段結構配置為為該晶粒提供 ^原連接和/或接地連接。該多健的—個或者多健包括:⑴ 第-側’⑷第二侧,該第一侧佈置為與該第二侧相對,⑽) 端子部分以及㈤延伸部分。在朗子部錢賴第一側輕 201216430 合至該犧牲基板’以及在該延伸部分處_第二娜置為接納 來自該晶粒的一個或多個電連接。 【實施方式】 本公開的實施方式描述了用於電子難組件的墊的技術、 結構以及配置。在以下詳細描述中,參考了作為其—部分的附 圖’其中貫穿附圖,類似的參考標號表示類似的部分。在不脫 離本公開範_情況下,可以_其他實施方式,並且可以進 =結構上和邏輯上的改變。因此,以下詳細描述不應理解為限 1性的’並且實施方式的範圍由騎權利要求書及其等同方案 限定。 圖1示意性地示_合_卩刷電路板15G的電子封裝組件 =〇的橫截面視圖。電子封農組件觸包括如圖所示地麵合的 焊接遮罩層114和-個或多個再分佈層1〇6。 其他一般地包括阻焊材料’諸如環氧樹脂。在 f他實施方式巾’可以制其他合適的魏賴料 還可哺為阻焊_,形成在 焊接遮罩層m中以提供對—個或多個再分佈層1G6的訪問。 的多個再分佈層106酉己置為路由電子封震組件⑽ 的-個或多個晶粒1G8的電信號。例如,該—個或多個再 層106能夠提供在一個或多個晶粒1〇8與-個或多個封裳互連 ^構116之間對輸入/輸出⑽信號和/或電源/接地信號的路 該一個或多個再分佈層106 -般地包括導電材料, 諸如金 201216430 在-個實施方式中,該—贼多個再分佈層1G6包括多個 塾102和晶粒塾104。在某些實施方式中,如所示出,墊102 2粒塾1G4是該-個或多個再分佈㉟的同—再分佈層的 塾102 一般地具有第一侧A1和佈置為與第-侧A1相對的 第二側A2。第一侧A1和第二侧A2通常指代墊1〇2的相對表 面,以方便描述在此描述的各種配置。 八該多個塾102中的至少一個塾包括端子部分101和延伸部 分103。端子部分1〇1配置為接納該一個或多個封裝互連結構 μ中的至少-個封裝互連結構。也就是說,端子部分1〇1的第 一侧A1用作該一個或多個封襄互連結構116的接點塾(1_吨 Pad)、,正如可以看到的那樣。該一個或多個封裝互連結構116 可以通過形成在焊接遮罩層m中的一個或多個開口 lb直接 接合到端子部分101的第一侧A1。 延伸部分1G3配置為接納來自—個或多個晶粒⑽的一個 或多個電連接。在-個實施方式中,—根或多根接合線⑽輕 合到延伸部分103的第二側A2以路由該一個或多個晶粒1〇8 的電信號。 -個或多個晶粒齡到該-個或多個再分佈層1〇6。 f 一個實施方式中’該-個或多個晶粒⑽_到晶粒塾1〇4。 a曰粒墊1〇4包括如下表面,該一個或多個晶粒1〇8附接在該表 Γ上。該—個或錢晶粒1G8可以使祕何合適的技術(諸如 晶粒粘合技術)來耦合到晶粒墊104。
S 12 201216430 •該個或多個晶粒108 一般地包括半導體材料,諸如石夕。 該-個或多個晶粒1G8 —般地具有有賴和非有源側,有源側 包括如下表面,在該表面上形成多個積體電路(ic)器件(未 不出),諸如用於邏輯和/或記憶體的電晶體,並且非有源側佈 置為與有源側相對。該—個或多個晶粒的有源側使用一根 或夕根接合線no電耦合到一個或多個再分佈層1〇6,正如可以 看到的那樣。 在某些實施方式中,晶粒墊1〇4用作接地墊以提供用於該 一個或多個晶粒1〇8的電接地連接。該—個或多個晶粒·;r 以使用一根或多根接合線11〇電耦合到晶粒墊1〇4,正如可以 到的那樣。 模塑料(molding compound)112形成為實質上封住該一個或 多個晶粒108、該一根或多根接合線11〇以及墊1〇2,正如可以 看到的那樣。麵料(mQldingeGmpc)Und)112 -舰包括電絕緣 材料,諸如熱固性樹脂,其佈置為保護該一個或多個晶粒1〇8 和電子封衷組件100的其他部件不受到與處理相關聯的破碎、 氧化或者潮濕的影響。 電子封裝組件100電搞合到電子封裝組件1⑻外部的另一 電子器件’諸如印刷電路板15G。在某些實施方式中,印刷電 路板150可以包括主機板。 電子封裝組件100使用該一個或多個封裝互連結 麵合到印刷電路板15G。該-個或多個封裝互連結構116 一般地 包括諸如金屬的導電材料。該一個或多個封裝互連結構ιι6可 以形成為各種各樣的形狀(包括球面、平面或者多邊形形狀), 並且可以定位在各種各樣的位置(包括在一行中,或者在含多 13 201216430 行的陣列中)。在-個實施方式中’該—個❹個封裝互連結構 116包括焊球。 根據各種實财式,電子職組件i⑻可·置在球拇陣 列、針柵陣列、接點柵格陣列、_四方扁平封裝、雙列直插 式、混合刻線框架球⑽B) _或者其合適驗合中。在 其他實施方式中,可以使用其他合適的封裝配置。 電子封裝組件的塾1G2可叫各種各樣的方式來排 列’以提供各種各樣的益處。例如,在此描述的塾結構和/或配 置可以允許或促_小的接合縣度、·電子雖組件· 的增加的I/O結構(例如墊)數量、由於用於接合的塾ι〇2的 增加的面積或特定定㈣引起的在·接合位置方面(例如接 合線角度、間隙(clearance))的增加的靈活性、接合線到同一 墊的多重接合、和/或對單-電子封裝佈局的使用可·多個不 同應用’或者其組合。圖2A至圖7繪製了根據各種實施方式 可以使用的某些示例塾配置。 圖2A示意性地示出具有塾酉己置的電子封裝組件施的一 部分260的頂視圖。為清楚起見,未繪製模塑料(—a㈣ compound) ° 電子封裝組件2GG包括-個或多個晶粒⑽,該一個或多 ,曰曰粒108包括多個接合墊1〇9。該一個或多個晶粒⑽的接 口墊109使用-根或多根接合線11〇電輕合到相應的塾脱。該 根或多根接合線11〇的一端可以直接輕合到接合塾1〇9,該一 根或多根接合線U0的另一端可以直_合到墊1〇2的端子部 分101或延伸部分103,正如可以看到的那樣。 塾102的第-行202佈置為與晶粒塾1〇4相鄰,正如可以 201216430 的第二行204佈置為與第-行2。2相鄰且 =墊1〇2的第三行2〇6佈置為與第二行2〇4相鄰且 j塾1〇2的第四行208佈置為與第三行206相鄰且平行’正 如可以看到的那樣。第—行2()2佈置為比 晶粒塾104,塾102的第二行204佈置為比&三行2〇6 2 = ==04,並且墊的第三行_佈置為比 ^ 可以看到的那樣。在其他實施_ 第第三行206中的塾102相對於第二行204和 == 錯,正如可以看到的那樣。也就是說, 在實質上垂直於行202、2〇4、2G6、⑽的方向上,第 和第三行206中的㈣2的端子部分1〇1並未盘第二行2 第四行2〇8中的墊102的端子部分1〇1對準。實質上垂直 ίϋν。6、208的方向用箭頭25。標出。第一行2。2和第 行:中,第二行204和第四 如可以看到的那樣奸Μ1和延伸部分⑽兩者,正 子和第四行2〇8中的墊1〇2的延伸部分103從端 =ί伸到第一行2〇2與第三行206的謂之間 分103在朝向晶粒塾104和7或該一個或多個晶 延伸。延伸部分103可以在實質上垂直於該一 2多個晶粒⑽的終止邊緣的方向上延伸,該終止邊緣與墊 相鄰且平行’正如可以看到的那樣。所繪製的端 其他實财射,可骑對軒部分⑼ 15 201216430 其他合適的形狀。 在圖2A的頂視圖中’形成在焊接遮罩層114中的一個或多 個開口 115以虛線形式繪製,以表明該一個或多個開口 115位 於墊102的端子部分1〇1之下。儘管所繪製的電子封裝組件2〇〇 的該一部分260僅示出了與一個或多個晶粒1〇8的終止邊緣之 一相鄰的墊102的配置,但是應當理解,可以沿著該一個或多 個晶粒108的其他或所有終止邊緣類似地配置墊1〇2和接合墊 109。 圖2B示意性地示出電子封裝組件2〇〇的該一部分26〇沿著 圖2A的段XY的橫截面視圖。圖2B的線211 一般地對應於圖 2A的線211,其一般地表明圖2A和圖2B中墊1〇2的共同維度^ 電子封裝組件2GG包括如®所示地輕合的具有端子部分1〇1和 延伸部分的多個墊102、晶粒墊1〇4、一個或多個晶粒1〇8、一 根或多根接合線110、模鋪(mGiding eGmpQund)112以及具有 一個或多個開口 115的焊接遮罩層114。 圖3示意性地示出具有另一塾酉己置的電子封裝組件3〇〇的 -部分·的頂視圖。電子封裝姆3⑻包括排列為第一行 202、第二行2〇4、第三行206和第四行208的多個墊1〇2。行 202、204、206、208對應於塾1〇2的端子部分1(H,正如可以 看到的那樣。在其他實施方式中,可贿用附加行。 第-行202和第二行204相對於彼此交錯,並且第一行2〇2 和第二行2〇4中的墊1G2的延伸部分⑽延伸為使得每個延伸 部分103的終止端對準以形成實質上平行於第-行2G2和第二 行204的行終止端3〇2。第三行2〇6和第四行2⑽相對於彼 此交錯,並且第三行206和第四行2〇8中_ 1〇2的延伸部分 201216430 =延伸為使得每個延伸部細的終止端(例如接點區域305) ί準以形成實質上平行於第三行2〇6和第四行的另一行終 止端304行302和304實質上彼此平行。儘管所繪製的延伸 部分103實質上是線性的,但在其他實施方式中,可以針對延 伸部分103使用其他非線性形狀。 、正如可以看到的那樣,延伸部分1〇3包括··接點區域3〇5, 以促進將-根或多根接合線11〇連接到延伸部分;走線區 307 ’以促進塾1〇2之間的路由,接點區域3〇5比走線區挪更 寬丄例如’該更寬接點區域3G5可靴置為接_—根或多根 接口線110’正如可以看到的那樣。儘管該更 綠製為圓形,但在其他實施方式中,可以針對該更寬接點區域 305使用其他形狀。延伸部分1〇3可以促進縮短一根或多根接 線110的導線長度,或者允許將塾1〇2放置在接合線夠不到 的位置上(例如超出導線長度製造能力)。 泣圖4示意性地示出具有另一墊配置的電子封裝組件4⑽的 邛分460的頂視圖。電子封裝組件4〇〇包括排列為第一行 和第二行204的多個墊102。在其他實施方式中,可以使用附 加行。 墊102包括端子部分101和延伸部分1〇3,延伸部分1〇3 在遠離端子部分1〇1的相反方向上延伸’正如可以看到的那 樣。延伸部分1〇3可以在遠離端子部分101的單一方向上延伸, 而不疋在运離h子部分101的兩個方向上延伸。在某此實施方 式中,延伸部分103在實質上平行於一個或多個晶粒1〇8的終 止邊緣的方向上延伸’該終止邊緣與墊1〇2的第一行2〇2相鄰 且平行。在其他實施方式中’延伸部分1〇3在與一個或多個晶 17 201216430 粒108的相鄰終止邊緣既不平行又不垂直的方向上延伸。第一 行202和第二行2〇4中的墊並不相對於彼此交錯。 延伸口103可以配置為在不垂直於一個或多個晶粒⑽ 的相鄰終止邊緣的方向上延伸以增加選擇接合位置方面的靈活 性(例如接合線角度、間隙)。在一個實施方式中,延伸部分 103在不垂直於第一行2〇2和/或第二行的方向上延伸正 如可以看到畴樣,以提供所希望的接合線肖度或離…根 或多根接合線110可以輜合到塾1〇2的端子部分1〇1和/或延伸 部分103 〇 圖5示忍性地示出具有另一墊配置的電子封裝組件$⑻的 -部分56G的頂視圖。電子封裝組件5⑻包括排列為第一行 202、第二行204和第三行206的多個墊1〇2。在其他實施方式 中,可以使用附加行。 行202、204、206並不相對於彼此交錯。也就是說,行2〇2、 204 206中的墊1〇2的端子部分在實質上垂直於行加、 204、206的方向上對準。實f上垂直於行观、2()4、的方 向由箭頭250標出。在此情況下,墊1〇2的延伸部分丨〇3可以 以非線性方式在更靠近於晶粒塾1〇4或該一個或多個晶粒1〇8 的行的墊102之間延伸。例如,在所繪製的實施方式中,第三 行206的墊1〇2的延伸部分1〇3以非線性方式在第二行2〇4的 整102之間延伸’從而使得延伸部分1〇3的終止端(例如接點 區域305)佈置在佈置於第一行2〇2與第二行2〇4令的墊 的端子部分101之間。在某些實施方式中,塾1〇2的每個延伸 部分103延伸為使得每個延伸部分1〇3的終止端(例如接點區 域305)對準,以形成實質上平行於第一行藝2〇2和第二行墊 201216430 204的一行終止端502。 正如可以看到的那樣’延伸部分1〇3包括:接點區域3〇5, 以促進將一根或多根接合線11〇連接到延伸部分1〇3 ;走線區 307,以促進在墊1〇2之間進行路由,接點區域3〇5比走線區 307更寬。例如,該更寬接點區域3〇5可以配置為接納該一根 或多根接合線110,正如可以看到的那樣。儘管該更寬接點區域 305繪製為矩形’但在其他實施方式中,可以針對該更寬接點 區域305使用其他形狀。電子封裝組件的配置允 許利用墊102之間的區域來進行多重接合或者允許在選擇用於 一根或多根接合線的接合位置方面的增加的靈活性。 個墊 102。行 202、204、206、208、2 如可以看到的那樣。在其他實施方式中 圖6不意性地示出具有另一墊配置的電子封裝組件60〇的 -部分660的觀圖。電子封裝崎_包括湖為第一行 202、第一行204、第三行2Q6、第四行和第五行21〇的多 210相對於彼此交錯,正 _,可以使用附加行。 伸部分103,延 離端子部分101 第一仃202、第二行204和第三行206中的墊1〇2包括延 延伸部分1G3在包括墊1G2的平面上在實質上遠 ° 77 1的所有方向上延伸。該平面例如可以與墊1〇2 ,^^、"^&(例如聯繫圖8的方法_而插述的犧牲層) 5 1G2所輕合到的表面(例如焊接遮罩層114)共面。
19 201216430 約束或可靠性問題(諸如墊之間的電短路),從製造角度而言, 將諸如墊102之類的導電特徵定位在小於最小間隔s的距離處 甚至是不可行的。在所繪製的實施方式中,延伸部分1〇3進一 步在平行於行(例如第一行202、第二行204等)的方向上、 而不是在垂直於行的方向上延伸。垂直於行的方向用箭頭25〇 標出。一個或多個開口 115以虛線形式繪製,以表明該一個或 多個開口 115位於墊1〇2的端子部分101之下。 在單一電子封裝組件200中可以使用多種不同結構的墊 102。第四行208包括僅具有端子部分1〇1的墊1〇2。第五行21〇 包括如下墊102,該墊1〇2包括端子部分1〇1和延伸部分1〇3, 延伸部分103朝向晶粒墊1〇4或一個或多個晶粒1〇8延伸。在 其他實施方式巾’可贿用採用多種不同結構的墊1Q2的其他 配置。例如’在某些實施方式中,聯繫圖1-圖7而描述的針對 墊102的結構和配置的實施方式可以適當地組合在單一的 封裝組件中。 圖7不意性地示出具有一個或多個環狀段結構720的電子 封裝組件700的-部分76〇的頂視圖。電子封裝組件包括 適合於在此插述的用於任何塾1〇2的實施方式的多個塾1〇2。 墊1 〇2排列在第一行202和第二行204中。在其他實施方式甲, 可以使用附加行。 ί個或多個環狀段結構720配置為為該一個或多個晶粒 供電源連接和/或接地連接。根據各種實施方式,該一個 個狀^'結構720佈置在第一行202與該一個或多個晶粒 108之間’正如可以看到的那樣。 使用-根或多根接合線11〇來將該一個或多個晶粒的
S 20 201216430 接合墊109電為人私,# D該―個或多個環狀段結構72〇和墊102, ==Γ樣。該一根或多根接合線η”以進-步用 在—二^個環狀段結構72〇中的分離環狀段結構電耦合 看到的那樣’該一個或多個環狀段結構72〇 一般 晶粒108⑽ΤΙ相鄰行(例如第一行2〇2)或該-個或多個 二、緣的方向上伸長,該終止邊緣與該一個或多 4二又、’口 720相鄰。該一個或多個環狀段結構720可以沿 者1個或多個晶粒_的—個或多個(例如所有)終止邊緣 而佈置’以實質上圍繞該—個或多個晶粒⑽,正如可以看到 的那樣在個實施方式中,該一個或多個環狀段結構別是 用於形成墊102和/或晶粒墊(例如圖6的晶粒塾1〇4)的同一 金屬層(例如圖1的再分佈層1G6)的部分。 該一個或多個環狀段結構720提供將同-設計用於多種或 ^種類型的||件(例如—個或多個晶粒間的靈活性。也就 是說’使用該-個或多個環狀段結構72G允許用於電子封裝組 件的單一佈局可用於多個不同的應用。 儘管相應的電子封裝組件200、300、400、500、600、700 的所繪製的部分260、360、460、560、660、760僅示出了與一 個或多個晶粒108的終止邊緣之一相鄰的墊1〇2的配置,但應 當清楚,可以沿著該一個或多個晶粒108的其他或所有終止邊 緣類似地配置墊102和接合墊1〇9。應當理解,在此描述的各 種墊配置可以用於四方扁平無引腳(QFN)封裝或其他類型的 封裝。 圖8示意性地示出用以製作在此描述的電子封裝組件(例 21 201216430 如電子封裝組件100)的方法800的工藝流程圖。在802處, 方法800包括提供基板。該基板包括如下表面,在該表面上形 成一個或多個再分佈層(例如圖1的一個或多個再分佈層 106)。該基板是在最終電子封裝組件中被去除的犧牲基板。最 終電子封裝組件是準備好運輸或由客戶使用的組件。該基板可 以包括各種各樣的合適的材料。在一個實施方式中,該基板包 括諸如銅的金屬。 在804處,方法800進一步包括在基板上形成再分佈層(例 如圖1的一個或多個再分佈層1〇6>該再分佈層包括多個墊(例 如圖1的墊102)。再分佈層可以進一步包括晶粒墊(例如圖丄 的晶粒墊104)。再分佈層可以通過任何合適的技術來形成,這 些技術包括例如電鍍、沉積、附接、對基板進行圖案化(如刻 蝕)或者其他合適的工藝來形成,以提供在此描述的墊的結構 或配置。 在806處,方法800進一步包括將晶粒(例如圖丨的一個 或多個晶粒108)麵合到再分佈層。在一個實施方式中,晶粒 的非有源表面個晶㈣合趣合到晶粒墊,晶粒的有源表面 使用一根或多根接合線(例如圖1的一根或多根接合線丨1〇)電 耦合到形成在基板上的多個墊。在其他實施方式中,可以使用 其他合適的技術來將晶粒耦合到再分佈層。 在808處,方法8〇〇進一步包括形成模塑料(例如圖i的 模塑料112 )。該模塑料(molding comp〇und) 一般地形成為封住晶 粒、該-根或多根接合線錢再分佈層^根據各種實施方式, 模塑料(moldingcompound)通過將固態形式(例如,粉末)的樹 脂(例如,熱固性樹脂)沉積到模具中並施加熱量和/或麼力以
S 22 201216430 熔化該樹脂而形成。在其他實施方式中,可以使用其他公知的 用於形成模塑料(molding compound)的技術。 在81〇處,方法800 it-步包括去除基板以暴露再分佈層。 基板可以例如通過使用諸如刻蝕工藝之類的工藝選擇性地去除 基板材料來去除。模塑料(molding compound)可以用作在去除^ 板的刻蝕工藝期間的機械載體。 承土 在812處,方法800進一步包括在暴露的再分佈層上形成 焊接遮罩層(例如圖1的焊接遮罩層m)。焊接遮罩層可以通 過任何公知的工藝來沉積。例如可以使用任何公知^案 曝光/顯影工藝在焊接遮罩層形成—個衫個開口(例 的 一個或多個開口 115)。 、 在似處,方法_進一步包括通過焊接遮單層將一個或 構(例如圖1的一個或多個封裝互連結構ιΐ6) 多個墊中的相應墊。該—個或多個難互連結構(例如 知球)可贿贿何合適_積技術來形成或放置。在一 ’該-個或多個封裝互連結構通過I 二個或多個開口附接到塾的端子部分(例如圖丨的= 在麵合該-個或多個封裝互連結構之後,電子 印刷電路板。 以將一個或多個晶粒的電信號路由到 各種操作以最有助於理解所要求保護的主題的方式被据述 23 201216430 為按次?㈣娜雜作。細,觀的順料應當理解為暗 不沒些操作必然是依賴於順序的。特別地,這些操作可以不以 所呈現_序執行。所贿_作可咖無描賴實施方式 不同的順序來執行。可喊行各種附加的操作和/或所描述的操 作在附加實施方式中可以省略。 、 本指述可以制基於透視的贿,諸如向上/向下、之上/ 之下’和/,或頂部/底部、。這種描述僅用於方便討論,而並非旨在 〜 〜低邓。延裡描述僅用於方便討論, 將在此描述的實施方式的應祕制為任何特定方向 出於本公開的目的,短語“,,意思是A或B。出於本 ^的,短語“A和/或B”意思是“(A)、(B)或者(A和b )。 的目的’短語“A、B * c中的至少一個,,意思是 bL^ 、(師3)、(八和〇、(料〇、或者(八、 )。出於本公開的目的,短語“(Α)Β,,意思是“(β)或 (ΑΒ) ”,也就是說,Α是可選元素。 者類使用短語“在—個實施方式中,,、“在實施方式中,,或 言,其均可以指代—個或多個相同或不同的實施方 更和/或糾付财錢纽 5式因Π旨/樹此討論物糊任何調整或變 其等同H喻旨機懈删及
S 24 201216430 【圖式簡單說明】 通過結合附圖的以下詳4 施方式。為方便進行這一^田述’將很容易理解本公開的實 構性元件。這裡的實施方類似的參考標號表示類似的結 是限制的方式示出。^在附圖的各圖中以示例的方式而不 截面=地不峰合到印刷電路板的電子封裝組件的橫 的頂:2,示意性地示出具有塾配置的電子封裝組件的-部分 分的2Α所鍋綱餘件的該一部 圖3示意性地示出具有另—塾配置的電子封裝 分的頂視圖。 圖4不意性地不出具有另一塾配置的電子封裝組件的-部 分的頂视圖。 圖5不意性地示出具有另一塾配置的電子封裝組件的一部 分的頂視圖。 圖6示思性地示出具有另一墊配置的電子封裝組件的一部 分的頂视圖。 圖7示意性地示出具有一個或多個環狀段結構的電子封裝 組件的一部分的頂視圖。 :’y '.tf 圖8示意性地示出用以製作在此描述的電子封裝組件的方 法的工藝流程圖。 25 201216430 【主要元件符號說明】 A1 :第一侧 101 :端子部分 A2 :第二側 102 :墊 100 :電子封裝組件 103 :延伸部分 200 :電子封裝組件 104 :晶粒墊 300 :電子封裝組件 106 :再分佈層 400 :電子封裝組件 108 :晶粒 500 :電子封裝組件 109 :接合墊 600 :電子封裝組件 110 :接合線 700 :電子封裝組件 112 :模塑料 260 : —部分 114 :焊接遮罩層 360 : —部分 115 :開口 460 : —部分 116 :封裝互連結構 560 : —部分 150 :印刷電路板 660 : —部分 211 :線 760 : —部分 250 :箭頭 202 :第一行 302 :行 204 :第二行 304 :行 206 :第三行 305 :接點區域 208 :第四行 307 :走線區 502 :行 720 :環狀段結構
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Claims (1)
- 201216430 七、申請專利範圍: 1. 一種電子封裝組件,包括: 焊接遮罩層,所述焊接遮軍層具有至少一個開口;以及 搞合到所述焊接遮罩層的多個墊,其中所述多個墊中的至少一 個墊包括⑴第-側,⑻第二側,所述第—側佈置為與所述 第二側相對,㈤端子部分以及(iv)延伸部分, 其中在所述端子部分處的所述第—做置為通過所述焊接遮罩 層中的所述至少-個開口接納封裝互連結構,所述封裝互連結 構用以在晶粒與所述電子封裝組件外部的另一電子器件之間路 由電信號,並且 其巾麵舰伸部分處騎述第二繼置為接絲自所述晶粒 的一個或多個電連接。 2. 根據請求項丨所述的電子封裝組件,進—步包括配置為接納所 述晶粒的晶粒墊,其中: 所述多個墊包括第-行墊,所述第—雜_與所述晶粒塾 相鄰;以及 所述多個墊包括佈置為與所述第一行塾相鄰且平行的第二行 塾’所述第-行墊佈置為比所述第二行塾更靠近於所述晶粒 墊。 3. 根據請求項2所述的電子封裝組件,其中: 所述至少一個墊佈置在所述第二行墊中。 根據請求項3所述的電子封裝組件,其中所述第一行塾和戶斤述 27 201216430 第二行墊相對於彼此交錯。 5. 根據請求項2所述的電子封裝組件,其中·· 所述多個墊包括佈置為與所述第二行塾相鄰且平行的第三行 塾,所述第二行墊佈置為比所述第三行墊更靠近於所述晶粒墊; 所述多個墊包括佈置為與所述第三行塾相鄰且平行的第四行 墊’所述第三行墊佈置為比所述第四行墊更靠近於所述晶粒 墊;以及 所述至少-個塾佈置在⑴所述第三行墊或(u)所述第四行 整> 中。 6. 根據請求項5所述的電子封裝組件,其中所述第三行塾和所述 第四行墊相對於彼此交錯。 7. 根據請求項5所述的電子封裝組件,其中: 如果所述至少一個墊佈置在所述第三行墊中,則所述至少一個 墊的所述延伸部分在(i)所述第二行墊的墊之間延伸;或者如 果所述至少一個墊佈置在所述第四行墊中,則所述至少一個墊 的所述延伸部分在(ii)所述第三行墊的墊之間延伸。 8. 根據請求項1所述的電子封裝組件,其中所述延伸部分在遠離 所述端子部分的相反方向上延伸。 9. 根據請求項1所述的電子封裝組件,其中所述延伸部分實質上 是非線性的。 10. 根據請求項2所述的電子封裝組件,進一步包括: 所述晶粒佈置在所述晶粒墊上,所述晶粒具有接合墊,所述接 S 28 201216430 合墊使用接合線電耦合到所述至少一個塾。 11.根據請求項10所述的電子封裝組件,其中所述接合線附接到 (1)所述接合墊以及(11)在所述至少一個墊的所述延伸部分 處的所述第二侧。 12·根據請求項10所述的電子封裝組件,其中: 所述晶粒墊是接地螯,所述接地墊用以提供用於所述晶粒的接 地連接;以及 所述晶粒通過使用另一接合線被電耦合到所述接地墊。 13. 根據請求項1〇所述的電子封裝組件,其中所述延伸部分在不 垂直於所述晶粒的邊緣的方向上延伸’所述晶粒的所述邊緣與 所述第一行墊相鄰且平行。 14. 根據請求項1〇所述的電子封裝組件,進一步包括: 模塑料’佈置為實質上封住所述晶粒和所述接合線,所述模塑 料布置在所述至少一個墊的所述第二侧上;以及 所述_互連結構’所述封裝互連結構通過所述至少一個開口 耦合到在所述至少一個㈣所述端子部分處的所述第一側。 15. 根據請求項10所述的電子封裝組件,進一步包括:佈置在⑴ 所述第-行墊與⑻所述晶粒之間的一個或多個環狀段結構, 所述-個或多個環狀段結構在實質上平行於與所述一個或多個 環狀段結構相鄰的所述晶粒的邊緣的方向上伸長,其中: e 所述晶粒的所述接合墊使麟述接合線電輕合到所述一個或 多個環狀段結構; 一 29 201216430 所述一個或多個環狀段結構使用附加的接合線電耦合到所述 至少一個墊;以及 所述一個或多個環狀段結構為所述晶粒提供電源連接或接地 連接。 16·根據請求項2所述的電子封裝組件,其中所述晶粒塾和所述多 個墊是同一金屬層的部分。 17. —種電子裝置,包括: 電子封装組件,包括: 焊接遮罩層,所述焊接遮罩層具有至少一個開口;以及 耦合到所述焊接遮罩層的多個墊,其中所述多個墊中的至少 -個墊包括⑴第-側’(ii)第二側,所述第一側佈置為與所 述第二侧相對’(出)端子部分以及(iv)延伸部分, 其中在所述端子部分處騎述第—做置為通過所述焊接遮罩 層中的所述至少一個開口接納封裝互連結構,並且 其中在所述延㈣分處騎述第二娜置為接納來自所述晶粒 的一個或多個電連接;以及 印刷電路板’通過使用所述封裝互連結構搞合到在所述至少一 個墊的所述端子部分處的所述第一側,所述封裝互連結構用以 在所述晶粒與所述印刷電路板之間路由電信號。 18 ·根據請求項17所述的電子裝置,其中所述電子封裝組件進一 步包括: 耦合到所述焊接遮罩層的晶粒墊; 201216430 所述晶粒佈置在所述晶粒墊上,所述晶粒具有接合墊,所述接 合墊使用接合線電輕合到所述至少一個墊;以及 模塑料,佈置為實質上封住所述晶粒和所述接合線,所述模塑 料布置在所述至少一個墊的所述第二側上。 19 ·根據請求項18所述的電子裝置,其中: 所述多個墊包括第-行藝,所述第一行墊佈置為與所述晶粒塾 相鄰;以及 所述夕個墊包括佈置為與所述第一行塾相鄰且平行的第二行 墊’所述第-行塾佈置為比所述第二行塾更靠近於所述晶粒甏 所述多個塾包括佈置為與所述第二行墊相鄰且平行的第三行 墊,所述第二行墊佈置為比所述第三行蚊靠近於所述晶粒塾; 所述多個墊包括佈置為與所述第三行墊相鄰且平行的第四行 墊’所述第三行塾佈置為比所述第四行墊更靠近於所述晶粒 墊;以及 所述至少-個墊佈置在⑴所述第三行墊或⑻所述第四 墊中。 如·根據請求項所述的電子震置,其中所述接合線附接到⑴ 所^接合塾以及(ii)所述至少一個塾的所述延伸部分的所述第 31
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TW100119804A TWI458062B (zh) | 2010-06-04 | 2011-06-07 | 電子封裝組件及電子裝置 |
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US (3) | US8860193B2 (zh) |
CN (1) | CN102270619B (zh) |
TW (1) | TWI458062B (zh) |
Families Citing this family (6)
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US8860193B2 (en) * | 2010-06-04 | 2014-10-14 | Marvell World Trade Ltd. | Pad configurations for an electronic package assembly |
US9035435B2 (en) | 2012-11-14 | 2015-05-19 | Power Integrations, Inc. | Magnetically coupled galvanically isolated communication using lead frame |
US20150206829A1 (en) * | 2014-01-17 | 2015-07-23 | Yin Kheng Au | Semiconductor package with interior leads |
EP3125285B1 (en) * | 2014-03-24 | 2019-09-18 | Photonics Electronics Technology Research Association | Pad-array structure on substrate for mounting ic chip on substrate, and optical module having said pad-array structure |
CN105826285B (zh) * | 2015-01-04 | 2018-07-03 | 华为技术有限公司 | 芯片及电子设备 |
US9653419B2 (en) | 2015-04-08 | 2017-05-16 | Intel Corporation | Microelectronic substrate having embedded trace layers with integral attachment structures |
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JPH09232465A (ja) * | 1996-02-27 | 1997-09-05 | Fuji Kiko Denshi Kk | 半導体実装用プリント配線板 |
US5977615A (en) * | 1996-12-24 | 1999-11-02 | Matsushita Electronics Corporation | Lead frame, method of manufacturing lead frame, semiconductor device and method of manufacturing semiconductor device |
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JP3506211B2 (ja) * | 1998-05-28 | 2004-03-15 | シャープ株式会社 | 絶縁性配線基板及び樹脂封止型半導体装置 |
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US8860193B2 (en) * | 2010-06-04 | 2014-10-14 | Marvell World Trade Ltd. | Pad configurations for an electronic package assembly |
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2011
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- 2011-06-03 CN CN201110153456.8A patent/CN102270619B/zh active Active
- 2011-06-07 TW TW100119804A patent/TWI458062B/zh active
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2014
- 2014-10-10 US US14/511,948 patent/US9331052B2/en active Active
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2016
- 2016-04-25 US US15/137,776 patent/US9543236B2/en active Active
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US20110298117A1 (en) | 2011-12-08 |
US9543236B2 (en) | 2017-01-10 |
CN102270619A (zh) | 2011-12-07 |
CN102270619B (zh) | 2014-03-19 |
US20150035160A1 (en) | 2015-02-05 |
US8860193B2 (en) | 2014-10-14 |
US9331052B2 (en) | 2016-05-03 |
US20160240459A1 (en) | 2016-08-18 |
TWI458062B (zh) | 2014-10-21 |
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