TW201108376A - Integrated circuit chip - Google Patents

Integrated circuit chip Download PDF

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Publication number
TW201108376A
TW201108376A TW099122962A TW99122962A TW201108376A TW 201108376 A TW201108376 A TW 201108376A TW 099122962 A TW099122962 A TW 099122962A TW 99122962 A TW99122962 A TW 99122962A TW 201108376 A TW201108376 A TW 201108376A
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Taiwan
Prior art keywords
layer
integrated circuit
metal layer
top metal
circuit chip
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TW099122962A
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English (en)
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TWI411077B (zh
Inventor
Ming-Tzong Yang
Yu-Hua Huang
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Mediatek Inc
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Publication of TW201108376A publication Critical patent/TW201108376A/zh
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Publication of TWI411077B publication Critical patent/TWI411077B/zh

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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

201108376 六、發明說明： 【發明所屬之技術領域】 本發明有’半導體技術，且特別有關於積體電路晶片 之改進型接合墊結構。 【先前技術】 “當前’業界對於具有多功能及高性能之小型、廉價之電子產品有 著迫切之需求。電路設計之主要趨勢係將儘可能多的電路器件整合至 積體電路之中，以降低每晶圓之成本。 積體電路藉由树晶圓之表面形成半導體器件來製造。多層内連 接（multi-levd interconnetion)係形成於器件上，與器件主動元件（崎^ 鲁dement)接觸，且將其線連接（wiring)以生成需要的電路。導線層 (wiring layer)可藉由以下步驟形成：於器件上沉積（dep〇sit)介電 層（出咖她layer);於介電層中成型（pattern)且_ (etch)接觸 開口（contact opening);而後於開口中沉積導體材料。導體層 (conductive layer)應用於介電層之上且被成型以形成器件接觸之間 之導線内連接（wiring interc〇nneti〇n)，以此形成基本電路之第一層。 電路更藉由利用位於附加的介電層之上且具有導體介層窗（W心之附 • 加的導線層來内連接。 201108376 取決於積體電路整體之複雜度，多層之導線内連接可被使用。於 最頂層（uppermost level)，導線終止於金屬銲墊，晶片之向外導線連 接（external wiring connection)接合（b〇nd)於金屬銲墊。頂部金屬 層（topmetallayer)或者鋁層（aluminumiayer)可用於積體電路中， 例如，用於製造整合電感器（integrated induct〇r)、金屬-氧化層-金屬 (MOM)電容器、電阻器、或者重分佈層㈤—㈣邙，皿) 等RF器件。 接合墊（bonding pad)亦存在於頂部金屬層。於導線接合製程中， 由於其上之壓力的影響，會發生非預期之顯著的變形。變形之接合塾 可導致覆蓋（e_〇於接合餅目（p_eiy)找化層（ρ_ν_η layer)之斷躲陷。為克服此_，通常制增大銲㈣口及/或兩個 薛墊之間的空間之方法。細，增大㈣開口及銲墊間距（_)將 導致晶片尺寸與成本的增加。 【發明内容】 有鑑於此’特提供以下技術方案： 本發明之-實施例提供-種積體電路晶片，包含基板、頂部金 層、下部金屬層以及至少-接合塾。其中頂部金屬層位於基板之上 下部金屬層位於基板之上且低於頂部金屬層；至少—接合塾位於 金屬層之内。 、 201108376 本發明之另—實施例提供—種積體電路晶片’包含基板、頂部金 屬層、電《、下部金屬層以及至少—接合塾。其中頂部金屬層位於 基板之上4感器形成於頂部金屬層之内，位於積體電路晶片之電感 祕成區域’下部金屬層位於基板之上，且低於頂部金屬詹；至少一 接合塾形成於下部金屬層，位於接合塾形成區域。 以上所述之碰電路晶片’提供—麵型接合墊結構，可解決先 前技術中於導線接合製程中接合塾顯著變形的問題。 、 【實施方式】 為使本發明之上述和其他目的、特徵、和優點能更易懂，下 文特舉出較佳實施例，並配合所關式，作詳細說明如下。♦注意， 以下所述實施例僅用以例示本發明之目的，其並非本發明之限制。本 發明之權利範圍應以申請專利範圍為準。 •下文將結合所附圖式，對本發明之實例及實施例作詳細之說明。 於本發明之說明書和圖式中，符號‘‘％，，意指為金屬層之頂層 ^pmost layer) ’例如鋁重分佈層，製造於積體電路晶片中。符^ “My”意指為低於頂層一層之金屬層，以此類推，其中，優選地，η 之範圍為2至10，但並不僅限於此。符號“V”意指為連接兩個相鄰 金屬層之介層窗。例如，V5：t指為内連接地與⑽之介層窗。 β參考第1圖’第1圖係根據本發明之—實施例之積體電路晶片 201108376 1之一部分之橫截面示意圖。應可理解，第丨圖之層或者元件未依據 尺寸畫出’且被修飾以使之更清楚。積體電路晶片1可包含用於合併 RF益件之頂部金屬層（Mj之卯積體電路，例如電感器或者適合於 RF電路之任-其他器件。用於RP器件之頂部金屬層（Mn)可為銘層、 銅層（copper layer)或者銅合金層（c〇pper au〇y iayer)，其中紹層為 優選方案。 頂部金屬層可降低寄生損耗（parasitic loss)，因此，其改善了 RF 積體電路之品質因數（qualityfact〇r，Q)。於本實施例中，頂部金屬層修 之厚度不小於0.5微米（micr〇meter)。於一些實施例中，頂部金屬層 叮具有不小於1.0微米之厚度。於另一些實施例中，頂部金屬層可具 有不小於3.0微米之厚度。 如第1圖所示，積體電路晶片1包含基板1〇，例如矽基板。基板 10可為任一適合的半導體基板，例如矽鍺（siGe)基板或者介電層上 覆矽（Silicon on Insulator，SOI)基板。基本層12包含但不限於器件 層’例如金氧半（MOS)或者雙極型器件；以及形成於基板10上之· 至少一層間介電（inter-layer dielectric ’ ILD)層《為簡潔起見，基本 層12内包含導線及接觸/介層窗之内連接未繪示。多個金屬間介電 (mter-metal dielectric ’ IMD)層 14、16、18 及 20，包含頂部 IMD 層 2〇 ’被提供於基本層12之上。每一該多個層14、16、18及20 了包含但不限於氧化石夕（silicon oxide)、氮化石夕（silicon nitride)、碳 化矽（silicon carbide)、氮氧化矽（siiicon 0Xy_nitri(ie )、低介電常數或 6 201108376 ^超低介電常數（Ultra丨。w_k，臓）材料，例如有機（例如，芳香族 反氫化口物（SiLK))或者無機（例如，含氫的石夕酸鹽⑽⑼材料 或者其任一組合。鈍化層22位於至少一部分IMD層20之上。鈍化層 22可為氧化硬、氮切、碳化梦、氮氧切、聚醯亞胺㈦恤也)曰 或者其任—組合或者類似物質。根據本實施例，鈍化層22具有〇.5至 6·〇微米之厚度，但並不僅限於此。 多層金屬内連接40可被製造於對應之IMD層14、16、18及20 #内為簡潔起見，僅Mn_2、vn_2、Mw及Mn層被明確繪示於圖式中。 RF器件，例如包含第-繞組（winding) 24及鄰近於第一繞組Μ之第 -％組26之電感器2〇〇，被製造於位於積體電路晶片！之電感器形成 區1〇1内之頂部金屬層（Mn) N。根據本發明之本實施例，頂部金屬 層（Mn)具有不小於G·5微米之厚度⑻。於-些實施例中，頂部金 屬層可具有不小於1.0微米之厚度。於另-些實施例中，頂部金屬層 可具有不小於3.0微米之厚度。電感器之第—繞組24與第二繞組 鲁26之側壁（S1dewaii)與頂面（t〇psurface)被鈍化層22覆蓋。儘管本 貫％例以電感器為例，本發明並不僅限於此。應可理解，其他奸器 件’例如MOM電容H或者電_可形成於頂部金屬層（Mn)。進二 步，頂部金屬層（Mn)可用於形成重分佈層。 根據本發明之本實施例，金屬層Μ。·!可由紹製成，其中至少—接 合墊118形成於金屬層Mn·,，而金屬層Mn2可由傳統的鋼鑲嵌 (damascene)方式形成，例如單鑲嵌（singledamascene)方式或者雙 201108376 鑲嵌（dual damascene)方式。例如，金屬層My可由單鑲嵌方式形成， 而金屬層My及積分介層窗層（integral via plug layer) Vn 2可由傳統 的鋁製程形成。此外，Mn_2可由鋁形成。如本技術領域中具有通常知 識者所知悉，銅鑲嵌方式提供一種形成耦接至積分介層窗之導線而不 需要乾式蝕刻（dry etch)銅之解決方案。單鑲嵌或者雙鑲嵌結構可用 於連接器件及/或積體電路之導線。 積體電路晶片1包含接合墊形成區1〇2。至少一接合墊118形成 於金屬層1，於接合塾形成區102之内。金屬層〜可薄於頂部金# 屬層（Mn) Μ列如，金屬層可具有約0.2-丨微米之厚度。接合墊開 口 202形成於純化層22及細層2〇中以暴露接合塾118之上表面⑽ surface)之至少-部分，使得接合線3〇可於封裝組裝階段卿 assembly stage)附著至接合墊118。接合墊開口 2〇2可具有約〇 8 6 〇 微米之深度。根據本發明之本實施例，接合塾118優選為轉塾，但 並不僅限於此。 可選地’支撐結構114及116可被形成於接合塾us之下。支撐籲 結構114及116可為任一合適之形狀或者組態⑽），以於 導線接合製程期間為接合塾118提供足夠的機械支揮。例如，支樓結 構114可為製造於金屬層I内之仿真金屬板（dummymetalplate)， 而支樓結構116可為多個介層窗，用於連接支樓結構H4與接合塾 此外接合塾118下之區域112之内，可形成主動電路（㈣π circuit)、電路元件或内連接（未繪示）。 8 201108376 *第2圖係依據本發明之另一實施例之積體電路晶片&之一部分之 橫截面之㈣圖’射她之標絲示她之層、區域或者元件。應 可理解，第2 m者元件核據財畫出，域料以使之更清 楚。、如第2圖所示’類似地，積體電路晶片ia包含基板ι〇。基本層 12以及夕個IMD層14、16、18及2〇,包含頂部細層2〇 ,被提供 於基板ίο之斤上。每-該多個細層14、16、18及2〇可包含但不限 於祕梦、a化砂、碳切、氮氧化⑦、低介電常數或者超低介電常 數材料例如有機（例如，芳香族碳氮化合物）或者無機（例如，含 氫的石夕酸鹽）材料或者其任—組合。鈍化層22位於至少—部分漏 層2〇之上。鈍化層22可為氧化碎、&化梦、碳化梦、氮氧化石夕、聚 醯亞胺或者其任-Μ合或者_物質。根據本實施例，鈍化層22具有 0.5至6.G微米之厚度’但並不僅限於此。 多層金屬内連接40可被製造於對應之励層14、16、18及20 春内為簡潔起見，僅Mn.rVnj'Mw及Μη層被明確緣示於圖式中。 RF益件’例如包含第_繞組24及鄰近於第一繞組24之第二繞組26 之電感器2GG，被製造於位於積體電路晶片1&之電感器形成區⑼内 之頂部金屬層（Mn)内。根據本發明之本實施例，頂部金屬層（則 具有不小於0.5微米之厚度（h)。於一些實施例中，頂部金屬層可具 有不小於1.0微米之厚度。於另_些實關巾，頂部金屬層可具有不 小於10微米之厚度。電感器200之第一繞組24與第二繞組26之側 壁與頂面被鈍化層22覆蓋。 201108376 積體電路晶片la更包含接合墊形成區i〇2。至少一接合塾214形 成於低於頂部金屬層Mn之任一金屬層之内，例如金屬層Mn2，於接 合墊形成區102之内。接合墊開口 302形成於鈍化層22及IMD層16、 18及20中以暴露接合塾214之上表面之至少一部分，使得接合線3〇 可於封裝組裝階段附著至接合墊214。接合墊開口 302可具有約1.〇_8.〇 从米之深度。請注意，如第2圖所示，接合塾214下之支撐結構可被 省略。 以上所述僅為本發明之較佳實施例，舉凡熟悉本案之人士援根據 本發明之精神所做之等效變化與修飾，皆應涵蓋於後附之申請專利範 圍内。以上所述實施例僅用以例示本發明之目的，其並非本發明之限 制。本發明之權利範圍應以申請專利範圍為準。 【圖式簡單說明】 第1圖係根據本發明之一實施例之積體電路晶片1之一部分之橫 戴面示意圖。 第2圖係依據本發明之另一實施例之積體電路晶片la之一部分之 橫戴面之示意圖。 【主要元件符號說明】 1、la·積體電路晶片；10:基板，12 :基本層； 201108376 14、16、18、20 : IMD 層；22 :鈍化層； 24 :第一繞組； 26:第二繞組； 30 :接合線； 40:多層金屬内連接； 101:電感器形成區；102:接合墊形成區； 112 :接合墊下之區域；114、116 :支撐結構； 118、214 :接合墊；200 :電感器；202、302 :接合墊開口。

Claims (1)

  1. 201108376 七、申請專利範圍： 1. 一種積體電路晶片，包含·· 一基板； 一頂部金屬層，位於該基板上方； 且低於該頂部金屬 ’更包含一開口， 一下部金屬層，位於該基板上或該基板上方， 層；以及 至少-接合塾’位於該下部金屬層之内。 2.如申請專利範圍第1項所述之積體電路晶片 用於暴露該接合塾之至少一部分。 3. 士申⑺專利糊第2項所述之積體電路晶片，更包含： 、及貞P金屬間"電層’位於該頂部金屬層與該下部金屬層之間； 純化層，位於該頂部金屬層之至少一部分之上； 其中，該開口被形成於該頂部金屬間介電層與該鈍化層之内。 —4.如申請專利範圍第3項所述之積體電路晶片，其中該純化層包 含氧化碎、氣切、碳化碎、氮氧化碎、聚醯亞胺或者其任一結合。 5.如申請專利範圍第3項所述之積體電路晶片，其中該純化層且 有0.5-6.0微米之一厚度。 曰 12 201108376 其中該頂部金屬 ’其中該頂部金屬 ’其中該頂部金屬 6.如申請專利範圍第i項所述之積體電路晶片 層係一紹層。 7·如申請專利範圍第1項所述之積體電路晶片 層係一重分佈層。 8·如申請專利範!〗項所述之積體電路晶片 層具有不小於0.5微米之一厚度。
    其中該下部金屬 9.如申請專利範圍第1項所述之積體電路晶片 層係一銘層。 更包含一支樓 1〇.如申請專利範圍第1項所述之積體電路晶片， 結構’位於該接合塾之下。 11· 一種積體電路晶片，包含： 一基板； 一頂部金屬層，位於該基板上方； -電感H ’形成於位於該積體電路晶片之電感器形成區域内之該 頂部金屬層内； 且低於該頂部金 一下部金屬層，位於該基板上或者該基板上方， 屬層；以及 内。 至少一接合塾，職於該下部金屬層，位於—接合塾形成區域 之 13 201108376 12. 如申請專利範圍第11項所述之積體電路晶片，更包含： 一頂部金屬間介電層，位於該頂部金屬層與該下部金屬層之間； 一純化層，位於該頂部金屬層之至少一部分之上；以及 一開口，位於該頂部金屬間介電層與該鈍化層之内，用於暴露該 接合墊之至少一部分。 13. 如申請專利範圍第12項所述之積體電路晶片，其中該鈍化層 包含氧化矽、氮化矽、碳化矽、氮氧化矽、聚酿亞胺或者其任一結合。 14. 如申請專利範圍第12項所述之積體電路晶片，其中該鈍化層 具有0.5-6.0微米之一厚度。 15. 如申請專利範圍第11項所述之積體電路晶片，其中該頂部金 屬層係一銘層。 16. 如申請專利範圍第11項所述之積體電路晶片，其中該頂部金 屬層係一重分佈層。 17. 如申請專利範圍第11項所述之積體電路晶片，其中該頂部金 屬層具有不小於0.5微米之一厚度。 18.如申請專利範圍第11項所述之積體電路晶片，其中該下部金 屬層係一铭層。 14 201108376 19. 如申請專利範圍第11項所述之積體電路晶片，更包含一支撐 結構，位於該接合墊之下。 20. 如申請專利範圍第11項所述之積體電路晶片，其中該積體電 路晶片包含使用該電感器之一射頻積體電路。 八、圖式：
    15
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