TW200929395A - Mountable integrated circuit package system with mountable integrated circuit die - Google Patents

Mountable integrated circuit package system with mountable integrated circuit die Download PDF

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Publication number
TW200929395A
TW200929395A TW097141321A TW97141321A TW200929395A TW 200929395 A TW200929395 A TW 200929395A TW 097141321 A TW097141321 A TW 097141321A TW 97141321 A TW97141321 A TW 97141321A TW 200929395 A TW200929395 A TW 200929395A
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TW
Taiwan
Prior art keywords
integrated circuit
package
die
circuit die
substrate
Prior art date
Application number
TW097141321A
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English (en)
Other versions
TWI478250B (zh
Inventor
Heap Hoe Kuan
Seng Guan Chow
Linda Pei Ee Chua
Dioscoro A Merilo
Original Assignee
Stats Chippac Ltd
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Application filed by Stats Chippac Ltd filed Critical Stats Chippac Ltd
Publication of TW200929395A publication Critical patent/TW200929395A/zh
Application granted granted Critical
Publication of TWI478250B publication Critical patent/TWI478250B/zh

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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Description

200929395 * 六、發明說明·· 相關申請案交互參照 • 本發明含有與 Heap Hoe Kuan、Seng Guan Chow、Linda Pei Ee Chua 和 Dioscoro A. Merilo 同時申請的 “Integrated Circuit Package System with • Interconnect Lock”美國專利申請案相關之標的。該相關 的申請案讓渡給STATS ChipPAC Ltd.，並被編為檔案編號 27-450。 ❹ 本申請案也含有與Seng Guan Chow、Heap Hoe Kuan 和 Linda Pei Ee Chua 同時申請的 “Integrated Circuit Package System with Offset Stacking and Anti-Flash Structure”美國專利申請案相關之標的。該相關的申請案 讓渡給STATS ChipPAC Ltd.，並被編為檔案編號27-492。 本發明復含有與 Seng Guan Chow、Linda Pei Ee Chua 和 Heap Hoe Kuan 同時申請的 “Integrated Circuit Package System with Offset Stacking” 美國專利申請案 ❹ 相關之標的。該相關的申請讓渡給STATS ChipPAC Ltd.， 並被編為檔案編號27-493。 【發明所屬之技術領域】 本發明一般係關於積體電路封裝件系統，並且尤關於 密封之積體電路封裝件系統。 【先前技術】 為了將積體電路與其它電路接合，通常設置其於導線 (lead)框架或基材之上。每一個積體電路具有接合墊 3 94509 200929395 (bonding pad)，其使用極度纖細的金或鋁線或傳導球（例 ^ 如焊球）個別連接至基材的接觸墊或終端墊。接著藉由個別 • 密封組合件於模製的塑膠或陶瓷本體内而予以封裝，以創 '造積體電路封裝件。 積體電路封裝技術見證了設置在單一電路板或基材上 的積體電路數目的增加。新的封裝設計是例如為封裝積體電 路的實體尺寸和形狀之更小形的形狀因子（f〇rm fact〇r)， 並提供大幅提升的整體積體電路密度。 © 然而’積體電路密度持續受到可用於設置個別積體電 路於基材上的“真實值（real estate)”所限制。即便是較 大型的形狀因子系統，例如：個人電腦（pers〇nal computer，PC)、電腦伺服機和儲存伺服機，都需要在同樣 或更小的“真實值”中有更多的積體電路。對於可攜式個 人電子裝置例如：手機、數位照相機、音樂播放器、個人 數位助理（personal digital assistant ; PDA)和適地性裴 ❹置（location-based device)來說特別迫切的這些需要已 進一步驅使對增加的積體電路密度的需要。 這個增加的積體電路密度已導致多晶片封裝件 (multi-chip package)的發展，其中封裝一個以上的積體 電路。每一個封裝件對個別的積體電路以及對使積體電路 電性連接至周圍電路的一層或多層之互速線層提供機械支 撐。 目前的多晶片封裝件，一般亦稱為多晶片模組，典型 地是由印刷電路板（PCB)基材所構成，其中一組分離的積體 94509 4 200929395 。電路組件直接附接於印刷電路板基材之上。已發現這種多 晶片封裝件提升積體電路的密度及微小化、改善訊號傳播 .速度、_整_體電路尺寸和重量、改善性能以及降低 成本--全部都是電腦工業的主要目標。 、多晶片封裝件不論是垂直或水平配置均可呈現問題， 因為在積體電路和積體電路連接件可以測試前，通常必須 要預先組裝封裝件。因此，當設置及連接積體電路在多晶 片模組中時，無法個別測試個別的積體電路和連接件，而 且在組裝到大型電路之前不可能辨識出已知合格的晶粒 (kn〇w~good—die ; _。所習知的多晶片封裝件導致 組裝製程的良率問題。這種無法辨識KGD的製造製程因此 較不可靠並且容易有組裝缺陷。 此外，在典型多晶片封裝件中的垂直堆疊積體電路會 、現那二水平配置的積體電路封裝件之外的問題，進一步 複雜化製造製程。要測試並因此確定個別積體電路的實際 ❹員型更困難。另外’基材和積體電路經常會在組裝或 J:肩間損壞，複雜化製造製程並提高成本。 ^於垂直和水平的多晶#封裝件來說，多晶片封裝件 間、/必須在多個積體電路之間、堆疊封裝積體電路之 或/、組合之間具有可靠的電性和機械附接。舉例來說， 製=柄裝積體1路⑽封㈣可料致污染，例如模 接’。r:或滲漏（mold flash or bleed)，因此妨礙可靠的附 件來另、一個例子，對於在密封中具有凹槽的積體電路封裝 說，使用輪廓模製槽（contoured mold Chase)來形成 94509 5 200929395 凹槽會有增加模製溢料的風險、經 *而增加對封裝件結構的損害以及在封裝膠 的凹槽設計特定的模製槽所增加的製造成未為了所需 善之=性=供低製造成本、改善之良率、改 音供應更多功能之 # 板上較少的覆蓋區域（f00tpri ‘ 在I刷電路 〇 找到這些問題的答案是越來越重要。㈣求來看’ 已經對於這些問題的解答研究了很久，但是沾恭 還無法教示或建議任何解答， ^ ' 已長久地困擾著本發明所屬μ 對思二問題的解答 【發明内容】 領域中具有通常知識者。 署接ί發明提供可設置的積體電路封裝方法，其包含.机 封裝件==裝2體上;連接在積體電路晶粒： Ο 形成:連;以及將封裝件封裂膠體 =於封裝件载體和第-内部互連上，並且部分暴 褒件封裝膠體的凹槽内之積體電路晶粒。 、封 本發明的某些具體實施例具有除了上述態樣 ^述態樣的其它態樣。對於本發明所屬技術領域中= 通吊知識者來說，經由閱讀以下的詳細描述並參考隨^ 圖式，這些態樣為顯而易知的。 、、 【實施方式】 以下詳細充分描述的具體實施例將使本發明所屬 領域中具有通常知識者得以製作和使用本發明？要 94509 200929395 •基於本發明的内容能使其它的具體實施例為明顯的，且可 以在不偏離本發明的範疇之下做出系統、製程或機械的改 •'變 ο .. ' 在以下的描述中，會給予許多特定的細節以提供對本 發明的通盤暸解。然而，很明顯地，在沒有這些特定細節 時也可實施本發明。為了避免對本發明造成混滑，不詳、細 揭露一些習知的電路、系統構型和製程步驟。同樣地，顯 示系統的具體實施例的圖式僅只是半概略圖 ❹ （semi-diagrammatic)，並沒有依照實際的比例，特別是一 些尺寸為了表達清楚，而在圖式中大幅地誇大顯示。大體 上，本發明可以在任何方位操作。 此外，揭露和敘述的許多具體實施例具有一些共同的 特徵，為了清晰和容易說明、敘述及理解，所有彼此類似 及相同的特徵通常會以相同的元件符號予以敘述。具體^ 施例已經編號為第一具體實施例、第二具體實施例等等以 ❹便於敘述，並未意欲具有其它意義或對本發明提供限制… 為說明的原因，本文所使用的術語“水平 (horizontal)”係定義為平行積體電路的平面或表面之平 面’無淪其方位；術語“垂直（vertical)，，係指垂直所定 義的水平之方向。術語諸如：“在…上面（ab〇ve)”、“在^ 下面（below)，，、“底部（b〇tt〇m)”、“上方（t〇p)”、‘彻 邊”(如在“侧壁”）、“較高（higher)” 、“較低 則 (lower)’’ 、“上面的（upper)” 、“在…上（〇ver)，，以及 在··.下（under)” ，係相對水平平面而定義。術語‘‘在... 94509 7 200929395 之上（on)”係指在元件間有直接接觸。本文所使用之術語 “處理（processing)”係包含材料的沈積、圖案化 (patterning)、曝光、顯影、蝕刻、清潔、模製(m〇lding) 以及/或材料的移除或依照所需要的形成所述結構。本文所 使用之術語“系統（system)’’依照使用術語之上下文意指 且定義為本發明之方法及設備。 現在參照第1圖’其中顯示在本發明的第一具體實施 例中的可设置的積體電路封裝件系統1 0 0的俯視圖。可設 © 置的積體電路封裝件系統100包含例如為具有凹槽1〇4的 環,氧模製化合物（epoxy molding compound)的封裝件封裝 膠體102。積體電路晶粒106在封裝件封裝膠體102的凹 槽104内部分暴露。設置積體電路裝置1〇8係設置在凹槽 104内之積體電路晶粒106上。設置積體電路裝置1〇8可 包含覆晶（flip chip)或單一或多堆疊晶粒的封裝積體電 路。 ◎現在參照第2圖，其中顯示可設置的積體電路封裝件 系統100沿著第1圖的線2—2的剖面圖。剖面圖描述設置 於第一積體電路裝置210上之積體電路晶粒1〇6，而第一 積體電路裝置210設置至例如為層壓基材的封裝件載體 212。具有内部封裝膠體214的第一積體電路裝置21〇可包 含例如：單一或多堆疊晶粒的封裝積體電路裝置。例如為 連接線（bond wire)或帶形（ribbon)連接線的第一内部互 連216連接積體電路晶粒106和封裝件載體212。 積體電路晶粒106包含主動晶粒側（active die side) 94509 200929395 ⑽和相對於线錄侧218的社動晶粒側（聲act-die side)219 ，以及在主動晶粒側 218 上的電性接觸 22〇 。 積體電路晶粒106設置在第一積體電路裝置21〇上而 體電路晶粒1〇6的非主動晶粒侧219面朝例如為環氧 化合物的内部封裝膠體214。第一内部互連216電性連接 主動晶粒側218至封裝件載體212。 Ο Ο 封裝件封裝膠體102覆蓋封裝件载體212、第一積體 電路裝置21〇、第一内部互連216、並且部分暴露於封裝件 封裝膠體102的凹槽104内之積體電路晶粒1〇6的電性接 觸220。設置積體電路裝置108設置在凹槽1〇4内之電性 接觸220上。較佳地’.設置積體電路裝置1〇8包含例如為 焊料凸塊（solder bump)的設置互連222，設置互連222係 設置於電性接觸220之上。視需要地，可以提供底部填充 劑224以德、封設置互連222和電性接觸22〇。 業已發現本發明提供低外形的可設置的積體電路封裝 件系統，其經由部分暴露在封裝件封裝膠體的凹槽内具有 電性接觸的積體電路晶粒來設置積體電路裝置，而降少整 體封裝件高度。本發明的可設置的積體電路封裝件系統藉 由消除對額外的設置基材（設置積體電路裝置典型設置於 其上）之需要而又減少製造這些層疊封裝 (package-on-package)的處理和整體成本。 現在參照第3圖’其中顯示在本發明的第二具體實施 例中，由第1圖的俯視圖所例示的可設置的積體電路封裝 件系統300的剖面圖。剖面圖描述設置於第一積體電路裝 94509 200929395 » 置310上之積體電路晶粒3〇6，而 :置到例如為層_的封蝴體312 Π = ^ .覆日日日日粒。例如為連接線或帶形連 體312之間連接。積體電路晶粒306和封裝件载 第内4互連316也可在第一積體雷政 裝置叫封裝侧312之間連接也了在第積體電路 曰路晶粒讓包含主動晶粒侧318和相對於主動 〇 Γ卜的雷叫的非主動晶粒侧319，以及在主動晶粒侧318 ，上的電性接觸320。以例如為覆膜線黏著劑 =30= ^牆㈤Ve)的第一黏著劑326 ^ ^ ❹ 第—積體電路裝置.的第-主動側328上， 而=紙日日粒跡的非主動晶粒侧319面對第一主動側 内。P互連316連接主動晶粒側318和封裝 =並且也電性連接第-主動侧328和封裝件載體二 、第一黏著劑326係顯示為未覆蓋在第-主動側328之 上的第一内部互連316，但是瞭解到第一黏著 可 覆蓋包含第一内部互連別的第-主動侧328。 封裝件封裝膠體302覆蓋封裝件載體312、第一積體 電路裝置310、第-内部互連316，並且部分暴露在封裝件 封裝膠體302的凹槽304内之積體電路晶粒3〇6的電性接 觸320。設置積體電路裝置308，例如：覆晶或單一或多堆 疊晶粒的封裝積體電路，係設置在凹槽3〇4内之積體電路 晶粒306上。較佳地’設置積體電路裝置308包含例如為 焊料凸塊的設置互連322，設置互連322係設置於電性接 94509 10 200929395 觸320之上。視需要地，.可以提供底部填充劑324以密封 設置互連322和電性接觸320。 現在參照第4圖，其中顯示在本發明的第3具體實施 例中’由第1圖的俯視圖所例示的可設置的積體電路封裝 件系統400的剖面圖。剖面圖描述設置於第一積體電路裝 置410上之積體電路晶粒406，雨第一積體電路裝置410 設置到例如為層壓基材的封裝件載體412。具有内部封裝 膠體414的第一積體電路裝置可包含例如設置到諸如 © 為層麼基材的第一基材430之封裝積體電路。例如為連接 線或帶形連接線的第一内部互連416在積體電路晶粒406 和封裝件載體412之間連接。第一内部互連416也可在第 一積體電路裝置410和封裝件载體4i2之間連接。 積體電路晶粒406包含主動晶粒侧418和相對於主動 晶粒侧418的非主動晶粒侧419，以及在主動晶粒侧418 之上的電性接觸420。以例如為晶粒附接黏著劑 ❹（dle attach adhesive)的第一黏著劑426設置積體電路晶 粒彻於第一積體電路裳置41〇的第-基材430上，而積 體電路曰曰粒406的非主動晶粒側419面對第一基材㈣。 部互連416辅主動晶粒側418和封裝件载體412, 祕贫電性連接第一基材430和封裝件載體412。視需要 =第—内部互連416也可在主動晶粒側4 一臭 430之間連接。 々乐基材 封裝件封裝膠體402覆蓋封震件載 、 電路裝置41〇十㈣料416，並且部錄露在封^ 94509 11 200929395 封裝膠體402的凹槽404内之積體電路晶粒406的電性接 觸420。設置積體電路裝置408，例如：覆晶或單一或多堆 • 疊晶粒的封裴積體電路，係設置在凹槽404内之電性接觸 420上。較佳地’設置積體電路褒置4〇8包含例如為焊料 凸塊的設置互連422，設置互連422設置於電性接觸420 之上。視需要地’可以提供底部填充劑424以密封設置互 連422和電性接觸420。 現在參照第5圖’其中顯示在本發明的第4具體實施 © 例中’由第1圖的俯視圖所例示的可設置的積體電路封裝 件系統500的剖面圖。剖面圖描述設置於第一積體電路裝 置510上之積體電路晶粒5〇6，而第一積體電路裳置510 設置到例如為層壓基材的封裝件載體512。具有内部封裝 膠體514的第一積體電路裝置51〇可包含例如設置到諸如 為層壓基材^第一基材530之封裝積體電路。例如為連接 線或帶形連接線的第一内部互連516在積體電路晶粒5〇6 ❹和封裝件載體512之間連接。第一内部互連516也在第一 積體電路裝置510和封裝件載體512之間連接。 積體電路晶粒506包含主動晶粒侧518和相對於主動 晶粒侧518的非主動晶粒侧519。主動晶粒侧518和非主 動晶粒侧519包含電性接觸520，電性接觸52〇為例如在 再分配層（redistribution layer ; RDL)或具有傳導軌跡 (conductive trace)之直通矽盲孔（thr〇ugh silic〇n via，TSV)中以進一步電性連接。積體電路晶粒5〇6設置於 第一積體電路裝置510的第一基材wo上，而主動晶粒側 94509 12 200929395 w 518面對第基材530。以例如為焊料凸塊的第二内部互連 532汉置積體電路晶粒506,並且第二内部互連532在主動 晶粒側518之上的電性接觸52〇與第一基材53〇的第一基 材側53气之間電性連接。視需要地，可以提供底部填 526以岔封第二内部互連532。第一内部互連516連接非主 動晶粒侧519與封裝件載體512，且也電性連接第—基 侧534與封裝件載體512。 土 ο 封裝件封裝膠體502覆蓋封裝件载體512、第 電路裝置510、第一内部互連516，並且部分暴露在封裝件 封裝膠體502的凹槽5〇4内之非主動晶粒側519的電 :520。設置積體電路裝置_，例如為覆晶或單—或多堆 疊晶粒的封裝積體電路，係設置在凹槽504内之非主動晶 粒侧519的電性接觸卿上。較佳地，設置積體電路= 湖包含例如為焊料凸__ 522，設 ❹ 置在凹槽504内之電性接觸52〇之上。視需要地可= 供底部填充劑524以密f 二而要也了从 ^ ' 封°又置互連522和電性接觸52〇 〇 中，用於製2 6圖’其中顯示在本發明的具體實施例 的藉辦雷女免置的積體電路封裝件系統100的可設置 玫602中，执 〇〇的程圖。方法600包含：在方 積體電路裝c封裝黎體於封裝件载體、第- 帛_互連上’並且部分暴露在封裝件 94509 13 200929395 封裝膠體的凹槽内之積體電路晶粒。 本發明之另一個重要的態樣是其有價值的支持和提供 降低成本、簡化系統和提升性能的歷史趨勢。 八 2發明的這=及其它有價值之態樣因此推動技術狀 態到至少下一個水平。 要現本!明的可設置的積體電路封裝件系 性能和功能性態樣，用於電路系統的 升和降低成本。所得的製程和構型度提 不複雜、高度變化性、準確、靈敏、有成本效盃、 調整已知的組件來實施，以快速、有致，並且可以藉由 用與利用。 、、、有效和經濟地製造、應 儘管本發明係以特定的最 如 據上述描述，眾多替代、修飾式來插述，可瞭解到根 ❹ 域中具有通常知識者而言為顯而燹化對本發明所屬技術領 囊括落入所附之申請專利範圍=見的。據此，其係傾向 修飾及變化。在本文提出的=内的所有這類的替代、 解為說明而非用於限制。 事項或顯示於圖式者係理 【圖式簡單說明】 第1圖是在本發明的第— 體電路封褒件系統的俯視圖；6體實施例中的可設置的積 第2圖是可設置的積體 線2--2的剖面圖； 、件系統沿著第1圖的 第 圖是在本發_第2具料施例中，由第 94509 200929395 - 俯視圖所例示的可設置的積體電路封裝件系統的剖面圖； ‘ 第4圖是在本發明的第3具體實施例中，由第1圖的 ‘俯視圖所例示的可設置的積體電路封裝件系統的剖面圖； 第5圖是在本發明的第4具體實施例中，由第1圖的 俯視圖所例示的可設置的積體電路封裝件系統的剖面圖； 以及 第6圖是在本發明的具體實施例中，用於製造可設置 的積體電路封裝件系統的可設置的積體電路封裝方法的流 ❹ 程圖。 【主要元件符號說明】 100、300、400、500、600 可設置的積體電路封裝件系統 102、302、402、502 封裝件封裝膠體 〇 212、312、412、512 封裝件載體 104、304、404、504 106 、 306 、 406 、 506 108 、 308 、 408 、 508 210 、 310 、 410 、 510 凹槽 積體電路晶粒 設置積體電路裝置 第一積體電路裝置 214、414、514 内部封裝膠體 216、316、416、516 第一内部互連 218、 318、418、518 主動晶粒側 219、 319、419、519 非主動晶粒側 220、 320、420、520 電性接觸 222、322、422、522 設置互連 224、324、424、525、526 底部填充劑 15 94509 200929395 326 ' 426 第一黏著劑 328 430 > 530 第一基材 532 534 第一基材侧 602、604 第一主動側 第二内部互連 、6 0 6方塊 16 94509

Claims (1)

  1. 200929395 •七、申請專利範圍： 1. 一種可設置的積體電路封裝方法，包括： 設置積體電路晶粒於封裝件載體上； 連接在該積體電路晶粒與該封裝件載體之間的第 一内部互連； 以及 將封裝件封裝膠體形成於該封裝件載體和該第一 内部互連上，並且部分暴露在該封裝件封裝膠體的凹槽 ❹ 内之該積體電路晶粒。 2. 如申請專利範圍第1項之方法，復包括將設置積體電路 裝置設置於該積體電路晶粒上。 3. 如申請專利範圍第1項之方法，其中，設置該積體電路 晶粒包含設置該積體電路晶粒於第一積體電路裝置上。 4. 如申請專利範圍第1項之方法，其中，設置該積體電路 晶粒包含設置該積體電路晶粒於第一積體電路裝置的 第一基材上。 ® 5.如申請專利範圍第1項之方法，其中，設置該積體電路 晶粒包含： 設置該積體電路晶粒於第一積體電路裝置的第一 基材上；以及· 連接在該積體電路晶粒與該第一基材之間的第二 内部互連。 6. —種可設置的積體電路封裝件系統，包括： 積體電路晶粒，設置於封裝件載體上； 17 94509 200929395 β 第一内部互連，連接在該積體電路晶粒與該封裝件 載體之間；以及 ‘ 封裝件封裝膠體，於該封裝件載體、該第一内部互 連上，並且該積體電路晶粒在該封裝件封裝膠體的凹槽 内部分暴露。 7. 如申請專利範圍第6項之積體電路封裝件系統，復包括 設置於該積體電路晶粒上的設置積體電路裝置。 8. 如申請專利範圍第6項之積體電路封裝件系統，其中， ❹ 該積體電路晶粒設置於第一積體電路裝置上。 9. 如申請專利範圍第6項之積體電路封裝件系統，其中， 該積體電路晶粒設置於第一積體電路裝置的第一基材 上。 10. 如申請專利範圍第6項之積體電路封裝件系統，其中： 該積體電路晶粒設置於第一積體電路裝置的第一 基材上；以及 ^ 復包括： 在該積體電路晶粒與該第一基材之間連接的第二 内部互連。 18 94509
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