TW200915510A - Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer - Google Patents

Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer Download PDF

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Publication number
TW200915510A
TW200915510A TW097130213A TW97130213A TW200915510A TW 200915510 A TW200915510 A TW 200915510A TW 097130213 A TW097130213 A TW 097130213A TW 97130213 A TW97130213 A TW 97130213A TW 200915510 A TW200915510 A TW 200915510A
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Taiwan
Prior art keywords
die
metal
semiconductor
semiconductor wafer
contact pads
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TW097130213A
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English (en)
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TWI371842B (en
Inventor
Byung-Tai Do
Heap Hoe Kuan
Linda Pei Ee Chua
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Stats Chippac Ltd
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Publication of TW200915510A publication Critical patent/TW200915510A/zh
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Publication of TWI371842B publication Critical patent/TWI371842B/zh

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Description

200915510 九、發明說明： 【發明所屬之技術領域】 本發明一般係關於半導體封裝，並且更特別地，係關 於具有以背側重新分配層沿著切割道所形成的穿孔通路之 可堆疊半導體晶粒。 内優先縣 本發明係命名為「使用在切割道上之穿孔通路晶粒的 封裝上封裝」以及申請於2007年6月20曰之美國專利申 請案第1 1 / 768,844的一部分接續申請案，該申請案係命 名為「在切割道上之穿孔通路」以及申請於2〇〇7年5月4 曰之美國專利申請案第1 1 / 744,657的一部分接續申請 案，並且係主張依據35U.S.C§120之前述專利申請案的優 先權。 ' 步諳案之交互春照 本專利申請案係關於共同申請中美國專利申請案（律 師檔案編號第125155.00032)之優先權，其係命名為「具有 在以部分切割道所形成之切割道上的穿孔通路之半導體封 哀」並且同時與本發明一起由Byung Tai D〇等人所申請。 本專利申請案係進一步關於共同申請中美國專利申請案 (律師檔案編號第125 155.00034)之優先權，其係命名為「具 有穿孔通路在切割道上與具有穿孔通路晶粒之作用區的半 導體晶粒」並且同時與本發明一起由Byung Tai D〇等人 申請。 200915510 【先前技術】 半導體元件係被發現於現代社會所使用的許多產品 中。半導體係找到在諸如娛樂、通訊'網路、電腦、以及 家用商品市場之消費者商品中的應用。在工業或是商業市 場中，半導體係被發現於軍事、航空、自動汽車、工業控 制器、以及辦公室設備中。 該半導體/G件之製造係涉及一具有複數個晶粒之晶圓 的形成。每個晶粒係含有數百個或是數千個實行各種電氣 Γ 功能之電晶體以及其它主動元件與被動元件。對於一給定 晶圓來說，每個來自該晶圓之晶粒典型地係實行相同的電 氣功能。前端製造通常係指該等半導體元件在該晶圓上的 形成。該完成的晶圓係具有一作用側邊，其係含有該等電 晶體以及其它主動元件與被動元件。後端製造係指將該完 成的晶圓切割或是單粒化成為個別晶粒，並且接著係封裝 該晶粒以用於結構性支持及/或環境隔離。 牽涉穿孔通路（through _ hole vias，THV )的使用。該等 穿孔通路典型地係位在環繞於沿著該晶粒之切割道導槽的 半導體製造係逐漸地採用 三維（3D)互連的封裝技術。 寸降低、降低的互連長度、以 的優勢至全部的三維封裝内。 在該等半導體元間之間牵涉 該等三維互連係提供諸於尺 及元件與不同功能性之整合 實施三維互連之一個方式係 周圍。大部分（假如不是全部的話），半導體封裝係使用 該等穿孔通路以將訊號路由在相鄰晶粒之間。然而，單獨 的穿孔通路係限制訊號路由選擇並且係降低訊號路由密 200915510 度。目前，高密度封裝係需要高密度以及彈性互連的能力， 其透過該等穿孔通路來達成係困難的。 係存在一種在一具有該等穿孔通路之半導體晶圓中增 加訊號路由選擇以及密度的需求。 【發明内容】 在一個實施例中，本發明係一種形成一半 方法’該方法係包含下列步驟：形成_具有複數個晶^ +導體晶圓的步驟’其中接觸銲塾係被佈置在每個晶粒的 第表面上，且其中該半導體晶圓係在每個晶粒之間具 有切割道導槽（guide);在該等切割道導槽中形成一溝渠 (trench) ·’以有機材料來填滿該溝渠；在該有機材料中 形成複數個通路孔洞；在該等接觸銲塾以及該等通路孔洞 之間形成跡線；將導電材料沉積在該等通路孔洞中以形成 金屬通路；在該晶粒相對該第一纟面之一第二表面上形成 重新分配層（RDL);在該晶粒之第二表面上的重新分配 層之間形成重新鈍化層；以及沿著該等切割道導槽來單粒 化該半‘體晶圓，以將該晶粒分離成為個別單元。 在另-個實施例中，本發明係一種包含複數個晶粒的 半導體晶圓’纟中接觸銲墊係被佈置在每個晶粒的一第一 表面上。該半導體晶圓係在每個晶粒之間具有切割道導 槽。複數個金屬通路係被形成在該等切割道導槽中，並且 係由有機材料所圍繞。複數條料係連接料接觸鲜塾以 及金屬通路。複數層重新分配層係被形成在該晶粒相對該 200915510 第一表面之一第二表面上。潘机 ^ 衣®上複數層重新鈍化層係被形成在 以晶粒之第二表面的重新分配層之間。 曰在另一個實施例中，本發明係一種包含複數個經堆叠 曰曰粒料導體封裝。每個晶粒係包含複數個被佈置在該晶 粒之-第-表面上的接觸銲墊、複數個沿著該晶粒之一周 圍所形成的金屬通路、複數條電氣連接該等金屬通路至該 等接觸銲塾的跡線、複數層被形成在該晶粒相對該第一表 =之一第二表面上的重新分配層、以及複數層被形成在該 晶粒之第二表面的重新分配層之間的重新鈍化層。該等重 新分配層係提供該經堆疊晶粒之間的電氣互連。 在另一個實施例中，本發明係一種包含一第一半導體 晶粒的半導體封裝，其中該第一半導體晶粒係具有沿著該 晶粒之一周圍的一第一表面上所形成之接觸銲墊以及金屬 通路’該晶粒係透過複數條跡線而電氣連接至該等接觸銲 塾。該第一半導體晶粒係進一步包含複數層被形成在該晶 粒相對該第一表面之一第二表面上的重新分配層，以及複 數層被形成在該晶粒之第二表面上的重新分配層之間的重 新鈍化層。一第二半導體晶粒係被佈置為相鄰該第一半導 體晶粒，並且係透過該重新分配層而被電氣連接至該第一 半導體晶粒。 【實施方式】 本發明係被敘述在下文關於該等圖式之描述的一個或 更多實施例中，其中相同的元件符號係代表相同或是類似 200915510 的元件。儘管本發明係㈣於達成本發明目的之最佳模式 的角度來敘述’熟習本項技術人士仍將理解到係打算包括 如可被包含於本發明之精神與料内的替代例、修改例、 以及對等例，丨中本發明之精神與料係如由該等下述揭 不内容與圖式所支持的該等後附申請專利範圍 例來定義。 等 該半導體元件之製造係涉及一具有複數個晶粒之晶圓 的形成。每個晶粒係含有數百個或是數千個實行—個或更 多電氣功能之電晶Μ以及其它主動元件與被動元件。對於 -給定晶圓來說，每個來自該晶圓之晶粒典型地係實行相 同的電氣功能。前端製造通常係指該等半導體元件在該晶 圓上的形成。該完成的晶圓係具有一作用侧邊，其係 該等電晶體以及其它主動元件與被動元件。後端製造係指 將忒完成的晶圓切割或是單粒化成為個別晶粒，並且接著 係封装該晶粒以用於結構性支持及/或環境隔離。 一半導體晶圓通常係包含一作用前側表面，其係具有 佈置在其上的半導體元件；以及—㈣表面，其係以諸如 矽之大量半導體材料所形成。該作用前側表面係含有複數 個半導體晶粒。該作用表面係藉由各種半導體製程所形 成，其係包含層疊（layering) '圖案化、掺雜、以及熱處 理。在該層疊製程中，半導體材料係藉由牽涉熱氧化作用、 氮化作用、化學氣相沉積、蒸鍍以及濺鍍之技術而被成長 以及沉積在該基板上。該圖案化係涉及光蝕刻微影 (Photolithography)之使用，以遮罩該表面區域以及蝕刻 200915510 :要的材料來形成特定結構。該摻雜製程係藉由熱擴散或 是離子植入而注入摻雜劑濃度。該作用*面係Α致上與諸 如接合銲墊之電氣互連平面並且均勻的。 覆曰曰半導體封裝以及晶圓級晶片尺寸封裝（) 一 般上係與要求高速、高密度、以及絕佳腳位總數之積體電 ()起使用。覆晶形式封裝係牵涉將該晶粒之一作 用區面向下地黏著至—晶片載體基板或是印刷電路板 (CB ) °亥作用區依據該晶粒之電氣設計係含主動元件 乂及被動元件、導電層、以及介電層。該電氣互連以及機 械互連係透過—包括大量個別導電銲錫凸塊或是銲錫球之 '干錫凸塊基板而達成。該等銲錫凸塊係被形成在該等凸塊 鲜塾上’其係被^置在該作龍上。料凸塊銲墊係藉由 »亥作用1中的導電執跡或是$電跡線而連接至該等作用電 路β亥等銲錫凸塊係藉由一銲錫回流製程而電氣地以及機 械地被連接至该載體基板上的接觸銲墊。 裝係提供自該晶粒上之主動幻牛至該载體基板上之導純 跡的-短路電氣連接，以爲降低訊號傳播、減低電容、以 及達成整體較佳的電路效能。 在本發明討論中’ 一晶圓級晶片尺寸封裝係被提供為 具有沿著切割道所形成的穿孔通路（THV )。該晶圓之背 側係具有用於由重新鈍化層所分離之互連彈性的重新分配 層（RDL )。具有沿著切割道所形成的穿孔通路係被敘述 在〒名為「切割道上的穿孔通路」之美國專利申請案第 11/744,657中，並且係進一步被敘述在命名為「使用切割 11 200915510 這上之穿孔通路晶粒的封裝上封裝」之美國專利申請案第 !】/768,844中，其之内容係以引用方式納入本文中。 轉向圖1 a ’ 一半導體晶圓3 〇係被顯示具有複數個晶 粒。該晶粒係由埋晶粒晶圓區域36 $分離，其一般係被 稱為切』道導槽。該等切割道導槽係被路由環繞於該晶 圓使得在該晶圓上每個晶粒之每一側邊上係存有一切割 I也就疋·環繞於該晶粒之一周圍。每個晶粒32係具 有複數個被形成在該晶粒之一作用側邊上的接觸銲墊％。 接觸I于墊3 8係、由紹質、銅質、或是链質/銅質合金所製作。 接觸鋅墊38係透過該晶粒32上所形成之導電軌跡或是導 電層而電氣連接至主動元件以及被動元件。該等接觸銲墊 係能被並排地佈置為距該晶粒之邊緣離開一第一距離，其 如圖la所示。另或者，該等接觸銲塾係以多重列來偏移， ，得一第一列接觸銲墊係被佈置為距該晶粒之邊緣離開一 第一距離’並且與㈣-列交㈣一第二列接觸鲜塾係被 佈置為距該晶粒之邊緣離開一第二距離。一銲錫凸塊或是 銲線接合稍後係將被形成而連接至每個金屬接觸銲墊，以 用於電氣互連以及機械互連至一晶片載體基板或是印刷電 路板（PCB)。 圖lb係為沿著圖la中之線lb_lb所取得的晶圓 之一橫截面視圖，其係顯示由切割道導溝36所分離的晶 粒32。在一個實施例中，該晶粒32係可具有範圍從2χ2 耄米（mm)至l5xl5毫米的維度。該等切割道係提供切割 區域以將該晶圓單粒化成為個別晶粒。一第—晶粒3 2係 12 200915510 被佈置在最左邊切割道36之左側…第二晶粒32係被佈 置在該切割道36之間。—第三晶粒32係被佈置在最右邊 切割道36之右側。一旦單粒化該晶圓，每組被佈置在各 別晶粒上的接觸銲塾係將提供該電氣互連以及機械互連予 5亥晶粒。 在圖h中，半導體晶圓30係再次顯示具有其之複數 個由切割道導溝36所分離的晶粒32。切割膠黏片4〇係被 施加至半導體晶圓30之背部，+ ^ ^ 从用於在接下來的製造操 f K, 作期間該晶圓的結構性支持，其係如圖孔中沿著圖h之 線2b-2b所取得的-橫截面視圖所顯示。該切割道％係 由切開工具44所切關。太—加杏丄 ^ 吓刀開在個實施例中，該切開工具44 係能為-鋸刀或是雷射。注意到該切開工具係完整地切斷 穿過該晶圓30以形成一井部或是溝渠42。該溝渠42之底 部係由該切割膠黏片40所定界。該溝渠42之形成係產生 自該晶圓之-第一單粒化’其係建立一溝渠寬度少於該切 割道導溝36之通道的一寬度。 在圖3a巾，半導體晶圓3(Μ系顯示具有其之複數個由 切開的切割道導溝36所分離的晶粒32。該晶圓3〇係經歷 -晶圓擴張步驟以增加該切割道導溝％的寬度。圖扑係 為/口著線3b 3b所取得之晶圓3〇的橫截面視圖，其係 顯示該晶粒使用如由方向箭帛46所示之-晶圓擴張台而 被拉開。另或者，粒係能被拾取以及放置於一晶圓支 持系統内。在任何情況中’該晶粒在圖弥至％的步驟之 後係被定位地更分開以建立較寬的切割道導溝。在一個實 13 200915510 施例中’該晶粒分離係從5〇微米（A m )增加至2〇〇微米。 S玄經擴張維度係取決於該設計實施例’亦即：半通路、全 通路、單列通路、或是雙列/多重列通路。 在圖4a中，半導體晶圓30係顯示具有其之複數個由 切開的切割道導溝36所分離的晶粒32。有機材料48係藉 由紅轉塗佈（spin _ e〇ating )或是針頭配料（neede dispensing)而被沉積在溝渠42中。該有機材料係能為 求環丁烯（benzoCyclobutene，BCB )、聚醯亞胺（p〇iyimide， PI)、或是丙烯酸樹脂（acrylic resin)。圖外係為一沪 ::4b—4b所取得之晶圓3〇的橫截面視圖，其係顯示該 令機材料48被沉積在該溝渠42中。該有機材料48係自 :切割膠黏片40將該溝渠42填滿直至該晶粒Η的一頂 表面。 以节右！5a中’半導體晶圓30係顯示具有其之複數個由 晶=2機材料48來填滿之㈣的㈣道導溝36所分離之 該有機好Γ通路孔洞5G係、沿著該切割道導溝36而被切入 材料48。該通路切開操作係使 刻製程。m心,、n 用冑射鑽孔或是蝕 銲塾3以日係被放置於沿著相鄰該等接觸 直徑以及、^粒3\處。在—個實施例中，取決於該通路之 二以及冰度，該等接觸銲墊38盥 約20微米至15〇微半… 洞50係具有大 150微未的—最小分離距離。 圖，：：:為广所取得之晶圓3。的橫截面視 …。該雷射鑽孔操作係集中於該切割道導溝的通 200915510 道’並且使一孔洞具有少於該溝帛42之寬度的一直徑， 其係留下—層環繞該通路孔洞5G之有機㈣4卜該溝渠 :之寬度係取決於該切割道之寬度，但典型地係小於該： K寬度。取決於所需要之通路深度，該通路孔洞之 直徑典型地係大约丨0微米至〗〇〇微米。 在圖6a巾，半導體晶圓3Q_示具有其之複數個由 具有通路孔洞50的切割道導溝36所分離之晶粒Μ…金
屬軌跡m線係自每個接觸㈣38而被路由至相對應 通路孔洞50。該跡線52係藉由—金屬圖案化製程所形成， 以連接該等接觸銲& 38至在—猶後步驟中將要以導電材 料所填滿的通路額5卜該等跡線52係如所示提供每個 接觸辉塾與通路孔洞配對。一些通路孔洞5〇係為不實行 電氣功能的仿真通路。據此，金屬跡線52係取決於該元 件功而不需要被路由至每一個通路。圖6^係為—沿著 線6b—6b所取得之晶圓30的橫載面視圖，其係顯示連接 該等接觸銲墊38至該等通路孔洞50的金屬跡線52。 在圖7a中，半導體晶圓30係顯示具有其之複數個由 具有經金屬填滿通路54的切割道導溝36所分離之晶粒 32。一金屬軌跡或是跡線係自每個接觸銲墊38而被路由 至相對應通路孔洞50。一導電材料係透過諸如電鍍 (plating)或是堵塞（plugging)之一沉積製程而被沉積 入該等通路孔洞50以形成金屬通路54。該導電材料係能 為鋼質（Cu)、鋁質（A1)、鎢質（w)、或兩者之合金、 或是其它導電採料之混合。該等金屬通路54係被形成在 15 200915510 ::有機材料48中或是由該有機材料48所環繞。該等金屬 通路54係經由該跡線52而連接至該等接觸銲墊μ。該等 跡線係如所示提供每個接觸銲墊與金屬通路配對。圖X 7匕 係為-沿著線7b—7b所取得之晶圓3〇的橫截面視圖，盆 係顯不該經金屬填滿通路54通過該跡線52而電氣連接該 等接觸銲$ 38。該金屬通路54之底部係與該 = 40重合。 月 在圖8a中，半導體晶圓30係顯示具有其之複數個由 八有瀘金屬填滿通路54的切割道導溝3ό所分離之晶粒 32。該切割膠黏片40係被移除。該晶圓3()係被顛倒^得 該等接觸銲墊38以及跡線52為面向下。圖8b係為一沿 著線8b~~8b所取得之晶圓3〇的橫截面視圖。晶圓支持結 構56係被附接至該晶圓3〇的底侧。該晶圓支持結構％ 係能由玻璃、矽質基板、或是其它適合結構性支持該晶圓 之材料所製作。一背侧重新分配層58係被形成在該晶圓 的背側。該重新分配層58係以鎳質（Ni )、鎳釩（nickle vanadium，Niv )、銅質、或是銅質合金所製作。該重新 分配層58係操作為一中間導電層，以將電氣訊號路由至 該晶粒的各種區域（包含主動電路以及被動電路並且 係在諸如圖15至18中所示封裝整合期間提供各種電氣互 連的選擇。重新鈍化層6〇係被形成在該重新分配層58的 個別節點之間以用於電氣隔離。該重新鈍化層係能以氮化 石夕（SiN )、一氧化石夕、氮氧石夕石（siiicon 〇Xynitride，SiON )、 苯環丁烯（BCB )、聚醯亞胺、聚苯噁唑（p〇iybenz〇xaz〇ie， 200915510 PBO)、或是其它絕緣材料所製作。 在圖9a中半導體晶圓3〇係顯示具有其之複數個由 具有複數個晶粒32的切割道導溝％所分離之晶粒&其 中該複數個晶粒32係具有經由該跡線Μ而被連接至金屬 通路64的接觸料38。該晶圓3()係再次被顛倒使得該等 接觸料38以及跡線52為面向上，其如圖9b中所顯示 為沿者線9 b — 9 b所取得夕曰私q λ， 所取侍之S曰粒30的橫截面視圖。該切割 膠黏片62係被附接至該半導體晶圓30的底侧，以用於該 晶圓在第二或是最後單粒化成為分離晶粒32肖間的結構 性支持。該等金屬通路54係如圖％所示藉由切開工具7〇 而被切開穿過中央區4 68。在-個實施例中，該切開工具 70係能為一鋸刀或是雷射。該切開係沿延伸向下穿過該重 新分配層58至切割膠黏片62，以完整地將該等金屬通路 54切斷成為兩個相等的半圓通路64。一取放操作係將該 曰曰圓32作為個別單元而移除自該切割膠黏片。 在圖10a中，半導體晶粒32係顯示具有藉由該等跡線 52而被連接至金屬通路64的接觸銲墊38。圖i〇b係為一 沿著線10b— 10b所取得之晶粒32的橫截面視圖，其係顯 示如藉由圖1至9的製造步驟所產生之切割道上一金屬通 路的組態。銲錫凸塊或銲錫球72係被形成在該重新分配 層58上。 在圖11 a中，半導體晶粒3 2係顯示具有藉由該等跡線 52而被連接至金屬通路80的接觸銲墊38。圖lib係為一 沿著線lib — lib所取得之晶粒32的橫截面視圖，其係顯 17 200915510 不沿著該等切割道36的金屬通路80。除了像是5〇之兩個 通路孔洞並排地被形成在該有機材料48中以外，該等金 屬半圓通路係藉由圖1至9中所述步驟所產生。銲錫凸塊 或銲錫球72係被形成在該重新分配層58上。該並排地通 路孔洞50係藉由該有機材料48所分離。導電跡線52係 連接該等接觸銲墊38以及該等通路孔洞。該並排地通路 孔洞係以導電材料所填滿來形成該等金屬通路8〇。 在圖12a中，半導體晶粒32係顯示具有藉由該等跡線 (52而被連接至金屬通路8〇的接觸銲墊38。切割膠黏片係 被施加至該半導體晶圓30之背部’以用於在最後單粒化 成為分離晶粒32期間該晶圓的結構性支持，其係如圖nb 中沿著線12b — 12b所取得的一橫截面視圖所顯示。該第 二或是最後單粒化以分離該複數個晶粒32係以一像是7〇 的切開工具而沿著該等並排通路8〇之間的線82切開穿過 該有機材料48。該等通路80之間的單粒化係造成該等金 屬通路在切割道上的組態。 I， 在圖13a中，半導體晶粒32係顯示具有藉由該等跡線 52而被連接至該等金屬通路8〇的接觸銲墊38。圖13乜係 為一沿著線13b — 13b所取得之晶粒32的橫截面視圖，其 係顯不一金屬通路在切割道上的組態。該等金屬整圓通路 係藉由圖1至9與圖11至12中所述步驟所產生。該像是 5〇的並排通路孔洞係藉由該有機材料48所分離。像是52 的導電跡線係連接該等接觸銲墊以及該等通路孔洞。該並 排地通路孔洞係以導電材料所填滿來形成該等金屬通路 18 200915510 80。該最後單粒化以分離該 等並排金屬通路80之間 阳粒32係切開穿過該 通路在切割道上的組態。、冑材料48 ’來造成該等金屬 圖14係說明使用直接 堆疊。該複數個晶# 32传如屬接合的直接晶粒至晶粒 應用。該等金屬半通路被堆叠以適合-特定 金屬接合製程或是銲錫黎糊上直接通路 在一起。另或者，具有金屬全通路:體之;不般被連結 f
V 能使用—直接通路金屬接合製程或是銲料wi係 90所連結在一起。該頂部 由、、。口體 月惻篁新分配層58以用於互 其它元件以及封裝（未圖示）。該重新分配層Μ係由今 重新鈍化f 6〇而被分離並且被電氣隔離。該底部半導體 晶粒32係具有被形成在該重新分配| 58上的銲錫凸塊 ”，其中該重新分配層58係被該重新純化層6〇所分離以 用於電氣隔離。該重新分配層58係提供從該等銲錫凸塊U 至該底部半導體晶粒32之作用表面的中間互連。在該等 重新分配層之間以晶粒至晶粒堆疊方式的互連係能使用或 是不使用該等銲錫凸塊72。 在圖15至18中係顯示各種封裝應用，其係部分地使 用一具有在帶有背側重新分配層之切割道上所形成的穿孔 通路之互連技術。圖15係具有透過銲錫凸塊1〇2而連接 至該晶粒32之背側重新分配層58的半導體晶粒1 〇〇。該 背侧重新分配層58係電氣連接至該晶粒32上的主動電 19 200915510 路’以及係提供互連至該晶粒丨θθ β該晶粒32係由基板1 〇4 所支持。該等接觸銲墊38及/或該等金屬通路64或是8〇 係透過導電層108而電氣連接至銲錫凸塊ι〇6β該封裝係 由環氧類樹脂囊封材料（ep〇Xy encapSUlant ) 1〗〇所密封。 圖16係顯示一半導體晶粒120，其係透過接合銲線122 以及導電層124而電氣連接至該等接觸銲墊38及該等金 屬通路64或是80。該背侧重新分配層58係電氣連接至該 晶粒32的主動電路，其依次係透過導電層13〇而連接至 銲錫凸塊128。該晶粒32係由基板132所支持。該封裝係 由環氧類樹脂囊封材料134所密封。一未填滿材料136係 能被用於壓力減緩。 圖17係顯示一半導體晶粒14〇，其係透過接合銲線142 而電氣連接至該半導體晶粒32之背側重新分配層58。該 背側重新分配層58係電氣連接至該晶粒32上的主動電 路，以及係提供互連至該晶粒140。被動元件144係亦利 用銲錫膠糊146而連接至該背側重新分配層58。該等金屬 通路64係透過導電層147而電氣連接至銲錫凸塊145。該 晶粒32係由基板148所支持。該封裝係由環氧類樹脂囊 封材料149所密封。 圖18係顯示一半導體晶粒15〇，其係經由接合銲線Η] 而電氣連接至該等金屬通路64或是8〇。銲錫凸塊154係 電氣連接該重新分配層58之背側至導電層156，其係經由 接合銲線164、接合銲線166、以及導電層168而將半導 體晶粒16〇與銲錫凸塊162相連接。該晶粒32係由基板17〇 20 200915510 所支持。該封裝係由環氧類樹脂囊封材肖i72所密封… 未填滿材料1 74係能被用於壓力減緩。 …、’’β來犮，可堆疊半導體晶粒係已經與在該等切割道 中所形成的穿孔通路一起被敘述。該半導體晶粒係使用一 由一重新純化層所分離的重新分配層，以增加訊號路由選 擇以及密度1 了該等穿孔通路之外，該重新分配層係亦 於封裝内乂供更多訊號路由功能性以及彈性。 ^在本發明之一個或更多實施利已經被詳細地說明時， 熟習本項技術人士係將了解到：對於該些實施例之多個修 改以及調適係可被製作，而沒有悖離如後述中請專利範圍 所提及之本發明的範疇。 【圖式簡單說明】 圖la至lb係說明一種具有複數個由切割道導槽所分 開之晶粒的半導體晶圓之俯視圖以及侧視圖。 。圖2a至2b係說明具有切開的切割道導槽之半導體晶 圓的俯視圖以及側視圖。 圖3a至3b係說明該等切割道之一擴張的俯視圖以及 側視圖。 圖4a至4b係說明以有機材料所填滿之經擴張切割道 的俯視圖以及側視圖。 圖5a至5b係說明形成通路孔洞穿過該等切割道導槽 中之有機材料的俯視圖以及側視圖。 圖6a至6b係說明在該等接觸銲墊與通路孔洞之間形 21 200915510 成導電跡線的俯視圖以及側視圖。 圖7a至7b係說將導電材料沉積在該等通路孔洞中的 俯視圖以及側視圖。 圖8a至8b係說明形成背側重新分配層與重新鈍化層 的俯視圖以及側視圖。 圖9a至9b係說明將該等金屬通路切開成為兩個半圓 通路的俯視圖以及侧視圖。 圖1 0a至1 Ob係說明一種具有沿著該等切割道所形成 Γ 之金屬通路的半導體晶粒之俯視圖以及側視圖。 圖11a至11b係說明沿著該等切割道所形成之在該晶 粒的Θ侧上具有重新分配層之兩個並排金屬通路的俯視圖 以及側視圖。 圖12a至12b係說明切開在該等兩個並排金屬通路之 間的有機材料以分離該晶粒之俯視圖以及側視圖。 圖13a至13b係說明一種具有沿著該等切割道之金屬 通路的半導體晶粒之俯視圖以及側視圖。 、 圖14係說明使用直接金屬至金屬通路接合的晶粒至晶 粒堆疊。 圖15係說明具有金屬通路之半導體晶粒被連接至具有 銲锡凸塊之一第二晶粒。 圖16係說明具有金屬通路之半導體晶粒被連接至具有 接合銲線之一第二晶粒。 圖17係說明使用在切割道以及背側重新分配層上之金 屬通路來互連晶粒的另一個實施例。 22 200915510 圖1 8係說明使用在切割道以及背側重新分配層上之金 屬通路來互連晶粒的另一個實施例。 【主要元件符號說明】 30 半導體晶圓 32 複數個半導體晶粒（第一晶粒，第二晶粒，第三晶粒） 36 埋晶粒晶圓區域，切割道（導溝） 38 接觸銲墊 f 40 切割膠黏片 42 溝渠 44 切開工具 46 方向箭頭 48 有機材料 50 通路孔洞 52 跡線，金屬跡線 54 金屬通路 ί ' 56 晶圓支持結構 58 (背側）重新分配層 60 重新鈍化層 62 切割膠黏片 64 半圓通路，金屬通路 68 中央區域 70 切開工具 72 録錫凸塊/鲜錫球 23 200915510 80 (並排）金屬通路 82 線 90 結合體 100半導體晶粒 102,106 銲錫凸塊 104 基板 108 導電層 110 環氧類樹脂囊封材料 120 半導體晶粒 122 接合銲線 124,130 導電層 126,128 銲錫凸塊 132 基板 134 環氧類樹脂囊封材料 136 未填滿材料 140 半導體晶粒 142 接合鲜線 144 被動元件 145 銲錫凸塊 146 銲錫膠糊 148 基板 147 導電層 149 環氧類樹脂囊封材料 150,160 半導體晶粒 24 200915510 152,164,166 接合銲線 154,162 銲錫凸塊 156，168 導電層 170 基板 172 環氧類樹脂囊封材料 174 未填滿材料 lb-lb 至 13b-13b 線 f 25

Claims (1)

  1. 200915510 十、申請專利範圍： l一種形成-半導體晶圓的方法，該方法係包括. 形成-具有複數個晶粒之半導體晶圓的步 . 觸銲墊係被佈置在每個晶粒的一第一表面上，且立中 導體晶圓係在每個晶粒之間具有切割道導槽；/、 在s亥等切割道導槽中形成一溝渠； 以有機材料來填滿該溝渠； 在該有機材料中形成複數個通路孔洞； 在該等接觸鋅墊以及該等通路孔洞之間形成跡線，· 將導電材料沉積在該等通路孔洞中以形成金屬通路； 在該晶粒相對該第-表面之一第二表面上形成重新分 配層（RDL); 在該晶粒之第二表面上的重新分配層之間形成重新鈍 化層；以及 沿著該等切割道導槽來單粒化該半導體晶圓，以將該 晶粒分離成為個別單元。 2·如中請專利範圍帛u之方法，其中該重新分配層 係提供電氣互連至相鄰晶粒。 土 3.如申印專利範圍第1項之方法，其中該晶粒係為可 隹疊的，並且在經堆疊時係可由該重新分配層以及該等金 屬通路所連結。 ' 4·如申請專利範圍帛1項之方法，其中至少-個金屬 通路係被形成在相鄰晶粒上的接觸銲墊之間。 5.如申請專利範圍第4項之方法’其中該半導體晶圓 26 200915510 係透過該至少一個金屬通路而被單 散早粒化，以形成經由該等 跡線而電氣連接至該等接觸銲墊的金屬通路。 6. 如申請專利範圍第1項 炙万法，其中兩個金屬通路 係並排地被形成在相鄰晶粒上的接觸銲墊之間。 7. 如申請專利範圍第6項之方 ，疋方法，其中該半導體晶圓 係沿著該等兩個金屬通路之間的 一 4 J切割道導槽而被單粒化， 以形成經由該等跡線而電氣連接 设主这等接觸銲墊的金屬通 路。 /··" i »·—種半導體晶圓，其係包括： 複數個具有接觸鮮塾的晶叙 日日粒其中該等接觸銲墊係被 佈置在母個晶粒的一第一表面 该+導體晶圓係在每個 日日粒之間具有切割道導槽； 、，複數個金屬通路，其係被形成在該等切割道導槽中， 並且係由有機材料所圍繞； 複數條跡線，其係連接該等接觸鲜塾以及金屬通路； 複數層重新分配層（RDL)， t, ^ . 丹係被形成在該晶粒相 對5亥苐一表面之—第二表面上；以及 :數層重新鈍化層’其係被形成在該晶粒之第二表面 的重新分配層之間。 ’其中該重新 ’其中該晶粒 新分配層以及 / 9·如巾請專利範圍第8項之半導體晶圓 分配層係提供電氣互連至相鄰晶粒。 10.如申請專利範圍第8項之半導體晶圓 係為可堆疊的，並且在經堆疊時係可由該重 5亥等金屬通路所連結。 27 200915510 11. 如申請專利範圍第8項之半導體晶圓，其中至少一 個金屬通路係被形成在相鄰晶粒上的接觸銲塾之間。 12. 如申請專利範圍第丨丨項之半導體晶圓，其中該半 導體晶圓係透過該至少一個金屬通路而被單粒化，以形成 經由該等跡線而電氣連接至該等接觸銲墊的金屬通路。 13. 如申請專利範圍第8項之半導體晶圓，其中兩個金 屬通路係並排地被形成在相鄰晶粒上的接觸銲墊之間。 14. 如申請專利範圍第1 3項之半導體晶圓，其中該半 f 導體晶圓係沿著該等兩個金屬通路之間的切割道導槽而被 單粒化，以形成經由該等跡線而電氣連接至該等接觸銲墊 的金屬通路。 15. 如申請專利範圍第8項之半導體晶圓，其係進一步 包含鲜錫凸塊’該等銲錫凸塊經電氣連接至該重新分配 層。 16. —種半導體封裝，其係包括： 複數個經堆疊晶粒，每個晶粒係包含： ( (a )複數個接觸銲墊，其係被佈置在該晶粒之一第一 表面上； (b )複數個金屬通路’其係沿著該晶粒之一周圍所形 成； (c )複數條跡線’其係電氣連接該等金屬通路至該等 接觸銲墊； (d )複數層重新分配層（rdl )，其係被形成在該晶 粒相對該第一表面之一第二表面上；以及 28 200915510 (e)複數層重新鈍化層，其係被形成在該晶粒之第二 表面的重新分配層之間； 其中該重新分配層係在經堆疊晶粒之間提供電氣互 連。 17·如申請專利範圍第16項之半導體封裝，其中至少 一個金屬通路係被形成在相鄰晶粒上的接觸銲塾之間。 18.如申請專利範圍第17項之半導體封裝，其中該半 導體晶圓係透過該至少一個金屬通路而被單粒化，以形成 (: 經由該等跡線而電氣連接至該等接觸銲墊的金屬通路。 19·如申請專利範圍第16項之半導體封裝’其中兩個 金屬通路係並排地被形成在相鄰晶粒上的接觸銲墊之間。 20·如申請專利範圍第19項之半導體封裝，其中該半 導體晶圓係沿著該等兩個金屬通路之間的切割道導槽而被 單粒化，以形成經由該等跡線而電氣連接至該等接觸銲墊 的金屬通路。 21.如申請專利範圍第16項之半導體封裝，其係進一 (/步包含銲錫凸塊，該等銲錫凸塊係經電氣連接至該重新分 配層。 22_—種半導體封裝，其係包括： 一第一半導體晶粒，其係具有沿著該晶粒之一周圍的 第表面上所开》成之接觸薛墊以及金屬通路，該晶粒係 透過複數條跡線而電氣連接至該等接觸銲墊，其中該第一 半導體晶粒係進—步包含複數層重新分配層（RDL)，其 係被形成在該晶粒相對該第一表面之一第二表面上，以及 29 200915510 複數層重新鈍化層，其係被形成在該晶粒之第二表面上的 重新分配層之間；以及 一第二半導體晶粒，其係被佈置為相鄰該第一半導體 晶粒’並且係透過該重新分配層而被電氣連接至該第一半 導體晶粒。 23. 如申請專利範圍第22項之半導體封裝，其係進一 步包含接合銲線，該等接合銲線係經電氣連接該第一半導 體晶粒以及該第二半導體晶粒。 24. 如申請專利範圍帛22項之半導體封裝，其係進一 步包含銲錫凸塊，該㈣錫凸塊係經電氣連接至該重 配層。 十一、圖式： 如次頁。 30
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