TW200703589A - Semiconductor package and method for manufacturing the same - Google Patents
Semiconductor package and method for manufacturing the sameInfo
- Publication number
- TW200703589A TW200703589A TW095114554A TW95114554A TW200703589A TW 200703589 A TW200703589 A TW 200703589A TW 095114554 A TW095114554 A TW 095114554A TW 95114554 A TW95114554 A TW 95114554A TW 200703589 A TW200703589 A TW 200703589A
- Authority
- TW
- Taiwan
- Prior art keywords
- wiring section
- wiring
- manufacturing
- substrate
- same
- Prior art date
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01077—Iridium [Ir]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Solid State Image Pick-Up Elements (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2005127266 | 2005-04-26 |
Publications (2)
Publication Number | Publication Date |
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TW200703589A true TW200703589A (en) | 2007-01-16 |
TWI305034B TWI305034B (zh) | 2009-01-01 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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TW095114554A TW200703589A (en) | 2005-04-26 | 2006-04-24 | Semiconductor package and method for manufacturing the same |
Country Status (5)
Country | Link |
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US (1) | US7838983B2 (zh) |
JP (1) | JP4635209B2 (zh) |
KR (1) | KR101189100B1 (zh) |
TW (1) | TW200703589A (zh) |
WO (1) | WO2006117961A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101930929B (zh) * | 2009-06-26 | 2012-07-18 | 日月光半导体(上海)股份有限公司 | 具有侧表面线路的封装用基板制造方法 |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7939916B2 (en) * | 2007-01-25 | 2011-05-10 | Analog Devices, Inc. | Wafer level CSP packaging concept |
US7843046B2 (en) * | 2008-02-19 | 2010-11-30 | Vertical Circuits, Inc. | Flat leadless packages and stacked leadless package assemblies |
JP5033682B2 (ja) * | 2008-03-12 | 2012-09-26 | 株式会社テラミクロス | 半導体素子およびその製造方法並びに半導体装置およびその製造方法 |
JP2009277970A (ja) * | 2008-05-16 | 2009-11-26 | Fujikura Ltd | 回路配線基板実装体 |
JP2009277969A (ja) * | 2008-05-16 | 2009-11-26 | Fujikura Ltd | 半導体装置及びその製造方法並びに半導体装置積層体 |
JP5266009B2 (ja) * | 2008-10-14 | 2013-08-21 | 株式会社フジクラ | 部品内蔵形回路配線基板 |
CN102804379B (zh) * | 2010-05-24 | 2015-12-09 | 全视科技有限公司 | 双面图像传感器 |
CN103155136B (zh) | 2010-09-29 | 2015-03-04 | Nxp股份有限公司 | Ic封装件的分离 |
FR2967814A1 (fr) * | 2010-11-23 | 2012-05-25 | St Microelectronics Grenoble 2 | Dispositif semi-conducteur a puce sur plaque support |
US9153507B2 (en) * | 2012-01-31 | 2015-10-06 | Broadcom Corporation | Semiconductor package with improved testability |
JP2014120612A (ja) * | 2012-12-17 | 2014-06-30 | Toshiba Corp | 半導体装置、およびそれを用いた半導体モジュール |
JP6278251B2 (ja) * | 2013-09-27 | 2018-02-14 | 富士電機株式会社 | 接合組立装置 |
US9881962B2 (en) * | 2013-12-10 | 2018-01-30 | Sony Corporation | Semiconductor apparatus, solid state imaging device, imaging apparatus and electronic equipment, and manufacturing method thereof |
US9972558B1 (en) | 2017-04-04 | 2018-05-15 | Stmicroelectronics, Inc. | Leadframe package with side solder ball contact and method of manufacturing |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5847930A (en) * | 1995-10-13 | 1998-12-08 | Hei, Inc. | Edge terminals for electronic circuit modules |
JP3599950B2 (ja) * | 1997-04-16 | 2004-12-08 | 株式会社アルバック | 金属ペーストの焼成方法 |
JP2002075999A (ja) | 2000-08-31 | 2002-03-15 | Ulvac Japan Ltd | 銅配線パターンの形成方法 |
US7177137B2 (en) * | 2002-04-15 | 2007-02-13 | Avx Corporation | Plated terminations |
JP2004303884A (ja) * | 2003-03-31 | 2004-10-28 | Seiko Epson Corp | 三次元実装モジュールの製造方法とその方法で得られる三次元実装モジュール |
JP3574450B1 (ja) | 2003-05-16 | 2004-10-06 | 沖電気工業株式会社 | 半導体装置、及び半導体装置の製造方法 |
JP2005005488A (ja) | 2003-06-12 | 2005-01-06 | Dainippon Printing Co Ltd | 半導体モジュールおよびそれらの製造方法 |
JP3646719B2 (ja) * | 2003-06-19 | 2005-05-11 | セイコーエプソン株式会社 | 半導体装置及びその製造方法、回路基板並びに電子機器 |
SG120123A1 (en) * | 2003-09-30 | 2006-03-28 | Micron Technology Inc | Castellated chip-scale packages and methods for fabricating the same |
JP2005340647A (ja) * | 2004-05-28 | 2005-12-08 | Nec Compound Semiconductor Devices Ltd | インターポーザ基板、半導体パッケージ及び半導体装置並びにそれらの製造方法 |
-
2006
- 2006-04-04 KR KR1020077024617A patent/KR101189100B1/ko active IP Right Grant
- 2006-04-04 WO PCT/JP2006/307087 patent/WO2006117961A1/ja active Application Filing
- 2006-04-04 JP JP2007514522A patent/JP4635209B2/ja not_active Expired - Fee Related
- 2006-04-04 US US11/911,990 patent/US7838983B2/en active Active
- 2006-04-24 TW TW095114554A patent/TW200703589A/zh not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101930929B (zh) * | 2009-06-26 | 2012-07-18 | 日月光半导体(上海)股份有限公司 | 具有侧表面线路的封装用基板制造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20090140364A1 (en) | 2009-06-04 |
WO2006117961A1 (ja) | 2006-11-09 |
KR101189100B1 (ko) | 2012-10-10 |
KR20080003832A (ko) | 2008-01-08 |
JPWO2006117961A1 (ja) | 2008-12-18 |
JP4635209B2 (ja) | 2011-02-23 |
TWI305034B (zh) | 2009-01-01 |
US7838983B2 (en) | 2010-11-23 |
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