TW200634926A - Structure and method to optimize strain in CMOSFETs - Google Patents

Structure and method to optimize strain in CMOSFETs

Info

Publication number
TW200634926A
TW200634926A TW095101578A TW95101578A TW200634926A TW 200634926 A TW200634926 A TW 200634926A TW 095101578 A TW095101578 A TW 095101578A TW 95101578 A TW95101578 A TW 95101578A TW 200634926 A TW200634926 A TW 200634926A
Authority
TW
Taiwan
Prior art keywords
strain
mosfets
coating
inducing
pmosfets
Prior art date
Application number
TW095101578A
Other languages
English (en)
Chinese (zh)
Inventor
Xiang-Dong Chen
Hai-Ning S Yang
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of TW200634926A publication Critical patent/TW200634926A/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Thin Film Transistor (AREA)
TW095101578A 2005-01-19 2006-01-16 Structure and method to optimize strain in CMOSFETs TW200634926A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/905,745 US7432553B2 (en) 2005-01-19 2005-01-19 Structure and method to optimize strain in CMOSFETs

Publications (1)

Publication Number Publication Date
TW200634926A true TW200634926A (en) 2006-10-01

Family

ID=36683015

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095101578A TW200634926A (en) 2005-01-19 2006-01-16 Structure and method to optimize strain in CMOSFETs

Country Status (6)

Country Link
US (3) US7432553B2 (https=)
EP (1) EP1842239A4 (https=)
JP (1) JP4884397B2 (https=)
CN (1) CN101496176A (https=)
TW (1) TW200634926A (https=)
WO (1) WO2006078740A2 (https=)

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Also Published As

Publication number Publication date
EP1842239A2 (en) 2007-10-10
CN101496176A (zh) 2009-07-29
JP4884397B2 (ja) 2012-02-29
US20080251853A1 (en) 2008-10-16
US20060157795A1 (en) 2006-07-20
JP2008527755A (ja) 2008-07-24
US7432553B2 (en) 2008-10-07
EP1842239A4 (en) 2009-07-01
US20080070357A1 (en) 2008-03-20
WO2006078740A3 (en) 2007-11-01
WO2006078740A2 (en) 2006-07-27

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