TW200633133A - Substrate processing method and method of manufacturing semiconductor device - Google Patents

Substrate processing method and method of manufacturing semiconductor device

Info

Publication number
TW200633133A
TW200633133A TW094141295A TW94141295A TW200633133A TW 200633133 A TW200633133 A TW 200633133A TW 094141295 A TW094141295 A TW 094141295A TW 94141295 A TW94141295 A TW 94141295A TW 200633133 A TW200633133 A TW 200633133A
Authority
TW
Taiwan
Prior art keywords
semiconductor device
substrate processing
manufacturing semiconductor
etched
resist pattern
Prior art date
Application number
TW094141295A
Other languages
English (en)
Inventor
Kaoru Maekawa
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of TW200633133A publication Critical patent/TW200633133A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)
TW094141295A 2004-11-25 2005-11-24 Substrate processing method and method of manufacturing semiconductor device TW200633133A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004340998A JP2006156486A (ja) 2004-11-25 2004-11-25 基板処理方法および半導体装置の製造方法

Publications (1)

Publication Number Publication Date
TW200633133A true TW200633133A (en) 2006-09-16

Family

ID=36497973

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094141295A TW200633133A (en) 2004-11-25 2005-11-24 Substrate processing method and method of manufacturing semiconductor device

Country Status (3)

Country Link
JP (1) JP2006156486A (zh)
TW (1) TW200633133A (zh)
WO (1) WO2006057236A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI422003B (zh) * 2010-05-21 2014-01-01 Napra Co Ltd 電子裝置及其製造方法
TWI475641B (zh) * 2008-06-09 2015-03-01 Tokyo Electron Ltd Manufacturing method of semiconductor device

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090094368A (ko) * 2006-12-11 2009-09-04 어플라이드 머티어리얼스, 인코포레이티드 건식 포토레지스트 스트립핑 프로세스 및 장치
US7942969B2 (en) * 2007-05-30 2011-05-17 Applied Materials, Inc. Substrate cleaning chamber and components
JP5251033B2 (ja) * 2007-08-14 2013-07-31 ソニー株式会社 半導体装置の製造方法
JP5343369B2 (ja) 2008-03-03 2013-11-13 東京エレクトロン株式会社 半導体装置の製造方法、半導体製造装置及び記憶媒体
KR101046335B1 (ko) * 2008-07-29 2011-07-05 피에스케이 주식회사 할로우 캐소드 플라즈마 발생방법 및 할로우 캐소드플라즈마를 이용한 대면적 기판 처리방법
DE112015006381T5 (de) 2015-03-27 2017-12-14 Mitsubishi Electric Corporation Halbleitereinheit und verfahren zur herstellung derselben
JP2017059750A (ja) 2015-09-18 2017-03-23 東京エレクトロン株式会社 被処理体を処理する方法
US10297496B2 (en) 2017-03-15 2019-05-21 Tokyo Electron Limited Method for processing target objection
JP2018157188A (ja) 2017-03-15 2018-10-04 東京エレクトロン株式会社 被加工物を処理する方法
KR102599015B1 (ko) * 2019-09-11 2023-11-06 주식회사 테스 기판 처리 방법
WO2023123499A1 (zh) * 2021-12-31 2023-07-06 华为技术有限公司 芯片及其制备方法、电子设备

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2715869B2 (ja) * 1993-11-25 1998-02-18 日本電気株式会社 半導体装置の製造方法
JPH1116912A (ja) * 1997-06-25 1999-01-22 Hitachi Ltd 半導体集積回路装置の製造方法および半導体集積回路装置の製造装置
JPH11251294A (ja) * 1998-02-27 1999-09-17 Sony Corp 半導体装置の製造方法
JPH11330046A (ja) * 1998-05-08 1999-11-30 Mitsubishi Electric Corp 半導体装置の製造方法及び半導体装置
JP3475100B2 (ja) * 1998-11-26 2003-12-08 シャープ株式会社 半導体装置の製造方法
US6204192B1 (en) * 1999-03-29 2001-03-20 Lsi Logic Corporation Plasma cleaning process for openings formed in at least one low dielectric constant insulation layer over copper metallization in integrated circuit structures
US6180518B1 (en) * 1999-10-29 2001-01-30 Lucent Technologies Inc. Method for forming vias in a low dielectric constant material
JP2003203974A (ja) * 2002-01-10 2003-07-18 Seiko Epson Corp 半導体装置の製造方法
US7214609B2 (en) * 2002-12-05 2007-05-08 Texas Instruments Incorporated Methods for forming single damascene via or trench cavities and for forming dual damascene via cavities

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI475641B (zh) * 2008-06-09 2015-03-01 Tokyo Electron Ltd Manufacturing method of semiconductor device
TWI422003B (zh) * 2010-05-21 2014-01-01 Napra Co Ltd 電子裝置及其製造方法

Also Published As

Publication number Publication date
JP2006156486A (ja) 2006-06-15
WO2006057236A1 (ja) 2006-06-01

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